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library: Cosmetic changes for modules that use ad_serdes_* 

Edited in:
 * axi_ad9122
 * axi_ad9434
 * axi_ad9684
 * axi_ad9739a
 * axi_ad9783
 * axi_adrv9001
 * ad_serdes_clk
 * ad_serdes_in
 * ad_serdes_out

Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
main
Iulia Moldovan 2022-12-13 15:23:24 +02:00 committed by imoldovan
parent 173f4a83d4
commit 45346b1957
13 changed files with 144 additions and 142 deletions
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2
library/axi_ad9122/axi_ad9122_if.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

3
library/axi_ad9434/axi_ad9434.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -38,7 +38,6 @@
module axi_ad9434 #(
parameter ID = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,

4
library/axi_ad9434/axi_ad9434_if.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -195,7 +195,7 @@ module axi_ad9434_if #(
// adc status: adc is up, if both the MMCM_OR_BUFR_N and DELAY blocks are up
always @(posedge adc_div_clk) begin
if(adc_rst == 1'b1) begin
if (adc_rst == 1'b1) begin
adc_status_m1 <= 1'b0;
adc_status <= 1'b0;
end else begin

2
library/axi_ad9684/axi_ad9684_if.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

2
library/axi_ad9739a/axi_ad9739a_if.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

2
library/axi_ad9783/axi_ad9783_if.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2021 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2021 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

2
library/axi_adrv9001/adrv9001_rx.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

2
library/axi_adrv9001/adrv9001_tx.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

2
library/axi_adrv9001/axi_adrv9001.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are

16
library/axi_adrv9001/axi_adrv9001_if.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -205,8 +205,8 @@ module axi_adrv9001_if #(
wire rx_ssi_sync_out;
adrv9001_rx
#(.CMOS_LVDS_N (CMOS_LVDS_N),
adrv9001_rx #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.NUM_LANES (NUM_LANES),
.DRP_WIDTH (DRP_WIDTH),
@ -247,8 +247,7 @@ module axi_adrv9001_if #(
.mssi_sync (mssi_sync),
.ssi_sync_out (rx_ssi_sync_out),
.ssi_sync_in (rx_ssi_sync_out),
.ssi_rst (adc_1_ssi_rst)
);
.ssi_rst (adc_1_ssi_rst));
adrv9001_rx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N)
@ -272,8 +271,8 @@ module axi_adrv9001_if #(
.rx_symb_8_16b (rx1_symb_8_16b));
generate if (DISABLE_RX2_SSI == 0) begin
adrv9001_rx
#(.CMOS_LVDS_N (CMOS_LVDS_N),
adrv9001_rx #(
.CMOS_LVDS_N (CMOS_LVDS_N),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.NUM_LANES (NUM_LANES),
.DRP_WIDTH (DRP_WIDTH),
@ -312,8 +311,7 @@ module axi_adrv9001_if #(
.mssi_sync (1'b0),
.ssi_sync_out (),
.ssi_sync_in (rx_ssi_sync_out),
.ssi_rst (adc_2_ssi_rst)
);
.ssi_rst (adc_2_ssi_rst));
adrv9001_rx_link #(
.CMOS_LVDS_N (CMOS_LVDS_N)

4
library/xilinx/common/ad_serdes_clk.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -40,6 +40,8 @@ module ad_serdes_clk #(
parameter FPGA_TECHNOLOGY = 0,
parameter DDR_OR_SDR_N = 1,
// single ended - 0
// differential - 1
parameter CLKIN_DS_OR_SE_N = 1,
parameter SERDES_FACTOR = 8,
parameter MMCM_OR_BUFR_N = 1,

28
library/xilinx/common/ad_serdes_in.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -36,6 +36,7 @@
`timescale 1ps/1ps
module ad_serdes_in #(
parameter FPGA_TECHNOLOGY = 0,
parameter CMOS_LVDS_N = 0,
parameter DDR_OR_SDR_N = 0,
@ -97,6 +98,9 @@ module ad_serdes_in #(
FPGA_TECHNOLOGY == ULTRASCALE ? "ULTRASCALE" :
FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE" :
"UNSUPPORTED";
// internal registers
reg [6:0] serdes_rst_seq;
// internal signals
@ -104,6 +108,7 @@ module ad_serdes_in #(
wire [(DATA_WIDTH-1):0] data_in_idelay_s;
wire [(DATA_WIDTH-1):0] data_shift1_s;
wire [(DATA_WIDTH-1):0] data_shift2_s;
wire serdes_rst = serdes_rst_seq[6];
// delay controller
@ -149,18 +154,18 @@ module ad_serdes_in #(
end
endgenerate
reg [6:0] serdes_rst_seq;
wire serdes_rst = serdes_rst_seq [6];
always @ (posedge div_clk)
begin
if (rst) serdes_rst_seq [6:0] <= 7'b0001110;
else serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
always @ (posedge div_clk) begin
if (rst) begin
serdes_rst_seq [6:0] <= 7'b0001110;
end else begin
serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
end
end
// idelay + iserdes
generate if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
generate
if (FPGA_TECHNOLOGY == SEVEN_SERIES) begin
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
if (IODELAY_ENABLE == 1) begin
@ -241,8 +246,8 @@ module ad_serdes_in #(
end
endgenerate
generate if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
generate
if (FPGA_TECHNOLOGY == ULTRASCALE || FPGA_TECHNOLOGY == ULTRASCALE_PLUS) begin
for (l_inst = 0; l_inst <= (DATA_WIDTH-1); l_inst = l_inst + 1) begin: g_data
wire div_dld;
@ -329,5 +334,4 @@ module ad_serdes_in #(
end
end
endgenerate
endmodule

29
library/xilinx/common/ad_serdes_out.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -76,6 +76,10 @@ module ad_serdes_out #(
FPGA_TECHNOLOGY == ULTRASCALE_PLUS ? "ULTRASCALE_PLUS" :
"UNSUPPORTED";
// internal registers
reg [6:0] serdes_rst_seq;
// internal signals
wire [(DATA_WIDTH-1):0] data_out_s;
@ -83,19 +87,19 @@ module ad_serdes_out #(
wire [(DATA_WIDTH-1):0] serdes_shift2_s;
wire [(DATA_WIDTH-1):0] data_t;
wire buffer_disable;
wire serdes_rst = serdes_rst_seq[6];
assign data_out_se = data_out_s;
assign buffer_disable = ~data_oe;
// instantiations
reg [6:0] serdes_rst_seq;
wire serdes_rst = serdes_rst_seq [6];
assign data_out_se = data_out_s;
assign buffer_disable = ~data_oe;
always @ (posedge div_clk)
begin
if (rst) serdes_rst_seq [6:0] <= 7'b0001110;
else serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
always @ (posedge div_clk) begin
if (rst) begin
serdes_rst_seq [6:0] <= 7'b0001110;
end else begin
serdes_rst_seq [6:0] <= {serdes_rst_seq [5:0], 1'b0};
end
end
// transmit data path: oserdes -> obuf
@ -172,17 +176,12 @@ module ad_serdes_out #(
.I (data_out_s[l_inst]),
.O (data_out_p[l_inst]),
.OB (data_out_n[l_inst]));
end else begin
OBUFT i_obuf (
.T (data_t[l_inst]),
.I (data_out_s[l_inst]),
.O (data_out_p[l_inst]));
end
end
endgenerate
endmodule