pluto: Enable phaser integration
This commit adds support for ADALM-PHASER, allowing the user to choose between the default PlutoSDR mode and Phaser mode through a software controlled GPIO pin: phaser_enable. The Generic TDD Engine was integrated to output a logic signal on the L10P pin, which connects to the input of the ADF4159, when receiving an external synchronization signal on the L12N pin from the Raspberry Pi. Two additional TDD channels are used to synchronize the TX/RX DMA transfer start: - TDD CH1 is connected to the RX DMA, triggering the synchronization flag; - TDD CH2 is connected to the TX unpacker's reset, backpressuring the TX DMA until deasserted. Signed-off-by: Ionut Podgoreanu <ionut.podgoreanu@analog.com>main
Ionut Podgoreanu
podgori
parent
cde9956948
commit
455bfbcafb
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@ -12,10 +12,12 @@ M_DEPS += ../../library/util_cdc/sync_bits.v
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M_DEPS += ../../library/common/util_pulse_gen.v
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M_DEPS += ../../library/common/ad_iobuf.v
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M_DEPS += ../../library/common/ad_bus_mux.v
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M_DEPS += ../../library/axi_tdd/scripts/axi_tdd.tcl
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M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl
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LIB_DEPS += axi_ad9361
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LIB_DEPS += axi_dmac
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LIB_DEPS += axi_tdd
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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@ -2,7 +2,9 @@
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Here are some pointers to help you:
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* [Board Product Page](https://www.analog.com/adalm-pluto)
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* [Board Product Page](https://www.analog.com/cn0566)
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* Parts : [RF Agile Transceiver](https://www.analog.com/ad9363)
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* Project Doc: https://wiki.analog.com/university/tools/pluto
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* Project Doc: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0566
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* HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl
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* Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361
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@ -5,6 +5,7 @@
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# create board design
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source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
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source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl
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# default ports
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@ -21,9 +22,9 @@ create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir I -from 16 -to 0 gpio_i
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create_bd_port -dir O -from 16 -to 0 gpio_o
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create_bd_port -dir O -from 16 -to 0 gpio_t
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create_bd_port -dir I -from 17 -to 0 gpio_i
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create_bd_port -dir O -from 17 -to 0 gpio_o
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create_bd_port -dir O -from 17 -to 0 gpio_t
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create_bd_port -dir O spi_csn_o
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create_bd_port -dir I spi_csn_i
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@ -33,6 +34,9 @@ create_bd_port -dir I spi_sdo_i
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create_bd_port -dir O spi_sdo_o
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create_bd_port -dir I spi_sdi_i
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create_bd_port -dir O txdata_o
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create_bd_port -dir I tdd_ext_sync
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# instance: sys_ps7
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ad_ip_instance processing_system7 sys_ps7
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@ -49,7 +53,7 @@ ad_ip_parameter sys_ps7 CONFIG.PCW_EN_RST1_PORT 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ 100.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ 200.0
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE 1
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 17
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ad_ip_parameter sys_ps7 CONFIG.PCW_GPIO_EMIO_GPIO_IO 18
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ad_ip_parameter sys_ps7 CONFIG.PCW_SPI1_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 0
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ad_ip_parameter sys_ps7 CONFIG.PCW_UART1_PERIPHERAL_ENABLE 1
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@ -219,6 +223,7 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9361_adc_dma CONFIG.SYNC_TRANSFER_START {true}
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ad_add_decimation_filter "rx_fir_decimator" 8 2 1 {61.44} {61.44} \
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"$ad_hdl_dir/library/util_fir_int/coefile_int.coe"
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@ -279,7 +284,6 @@ ad_connect axi_ad9361/dac_valid_q0 tx_fir_interpolator/dac_valid_1
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ad_connect axi_ad9361/dac_data_q0 tx_fir_interpolator/data_out_1
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ad_connect axi_ad9361/l_clk tx_upack/clk
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ad_connect axi_ad9361/rst tx_upack/reset
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ad_connect tx_upack/fifo_rd_data_0 tx_fir_interpolator/data_in_0
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ad_connect tx_upack/enable_0 tx_fir_interpolator/enable_out_0
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@ -309,12 +313,50 @@ ad_connect axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
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ad_connect axi_ad9361/l_clk axi_ad9361_dac_dma/m_axis_aclk
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ad_connect cpack/fifo_wr_overflow axi_ad9361/adc_dovf
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# External TDD
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set TDD_CHANNEL_CNT 3
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set TDD_DEFAULT_POL 0b010
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set TDD_REG_WIDTH 32
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set TDD_BURST_WIDTH 32
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set TDD_SYNC_WIDTH 0
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set TDD_SYNC_INT 0
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set TDD_SYNC_EXT 1
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set TDD_SYNC_EXT_CDC 1
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ad_tdd_gen_create axi_tdd_0 $TDD_CHANNEL_CNT \
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$TDD_DEFAULT_POL \
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$TDD_REG_WIDTH \
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$TDD_BURST_WIDTH \
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$TDD_SYNC_WIDTH \
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$TDD_SYNC_INT \
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$TDD_SYNC_EXT \
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$TDD_SYNC_EXT_CDC
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ad_ip_instance util_vector_logic logic_inv [list \
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C_OPERATION {not} \
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C_SIZE 1]
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ad_ip_instance util_vector_logic logic_or_1 [list \
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C_OPERATION {or} \
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C_SIZE 1]
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ad_connect logic_inv/Op1 axi_ad9361/rst
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ad_connect logic_inv/Res axi_tdd_0/resetn
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ad_connect axi_ad9361/l_clk axi_tdd_0/clk
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ad_connect axi_tdd_0/sync_in tdd_ext_sync
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ad_connect axi_tdd_0/tdd_channel_0 txdata_o
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ad_connect axi_tdd_0/tdd_channel_1 axi_ad9361_adc_dma/fifo_wr_sync
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ad_connect logic_or_1/Op1 axi_ad9361/rst
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ad_connect logic_or_1/Op2 axi_tdd_0/tdd_channel_2
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ad_connect logic_or_1/Res tx_upack/reset
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# interconnects
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ad_cpu_interconnect 0x79020000 axi_ad9361
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ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
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ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
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ad_cpu_interconnect 0x7C430000 axi_spi
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ad_cpu_interconnect 0x7C440000 axi_tdd_0
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ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1}
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ad_connect sys_cpu_clk sys_ps7/S_AXI_HP1_ACLK
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@ -345,4 +387,3 @@ ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
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ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
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ad_cpu_interrupt ps-11 mb-11 axi_spi/ip2intc_irpt
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@ -56,17 +56,26 @@ set_property -dict {PACKAGE_PIN P9 IOSTANDARD LVCMOS18} [get_ports gpio_rese
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set_property -dict {PACKAGE_PIN K12 IOSTANDARD LVCMOS18} [get_ports enable]
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set_property -dict {PACKAGE_PIN K11 IOSTANDARD LVCMOS18} [get_ports txnrx]
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set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_scl]
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set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports iic_sda]
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set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports spi_csn]
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set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports spi_clk]
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports spi_mosi]
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS18} [get_ports spi_miso]
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set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS18} [get_ports pl_spi_clk_o]
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set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports pl_spi_miso]
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports pl_spi_mosi]
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# PL GPIOs
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#
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# Pin | Package Pin | GPIO | Pluto | Phaser |
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# -----|-------------|----------|----------|---------|
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# L10P | K13 | PL_GPIO0 | SPI MOSI | TXDATA |
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# L12N | M12 | PL_GPIO1 | SPI MISO | BURST |
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# L24N | R10 | PL_GPIO2 | SPI CLKO | MUXOUT |
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# L7N | N14 | PL_GPIO3 | IIC SDA | IIC SDA |
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# L9N | M14 | PL_GPIO4 | IIC SCL | IIC SCL |
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set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports pl_gpio0]
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set_property -dict {PACKAGE_PIN M12 IOSTANDARD LVCMOS18} [get_ports pl_gpio1]
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set_property -dict {PACKAGE_PIN R10 IOSTANDARD LVCMOS18} [get_ports pl_gpio2]
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set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports pl_gpio3]
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set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS18 PULLTYPE PULLUP} [get_ports pl_gpio4]
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set_property -dict {PACKAGE_PIN P8 IOSTANDARD LVCMOS18} [get_ports clk_out]
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@ -60,9 +60,6 @@ module system_top (
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout iic_scl,
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inout iic_sda,
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input rx_clk_in,
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input rx_frame_in,
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input [11:0] rx_data_in,
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@ -84,16 +81,28 @@ module system_top (
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output spi_mosi,
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input spi_miso,
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output pl_spi_clk_o,
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output pl_spi_mosi,
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input pl_spi_miso
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output pl_gpio0,
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input pl_gpio1,
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inout pl_gpio2,
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inout pl_gpio3,
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inout pl_gpio4
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);
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// internal signals
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wire [16:0] gpio_i;
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wire [16:0] gpio_o;
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wire [16:0] gpio_t;
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wire [17:0] gpio_i;
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wire [17:0] gpio_o;
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wire [17:0] gpio_t;
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wire iic_scl;
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wire iic_sda;
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wire phaser_enable;
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wire pl_burst;
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wire pl_muxout;
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wire pl_spi_clk_o;
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wire pl_spi_miso;
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wire pl_spi_mosi;
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wire pl_txdata;
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// instantiations
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@ -109,6 +118,27 @@ module system_top (
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gpio_status})); // 7: 0
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assign gpio_i[16:14] = gpio_o[16:14];
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assign gpio_i[17] = pl_muxout;
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assign phaser_enable = gpio_o[14];
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assign pl_gpio4 = iic_scl; //PL_GPIO4
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assign pl_gpio3 = iic_sda; //PL_GPIO3
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//PL_GPIO2
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ad_iobuf #(
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.DATA_WIDTH(1)
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) i_pl_gpio_iobuf (
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.dio_t (phaser_enable),
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.dio_i (pl_spi_clk_o),
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.dio_o (pl_muxout),
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.dio_p (pl_gpio2));
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//PL_GPIO1
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assign pl_spi_miso = pl_gpio1 & ~phaser_enable;
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assign pl_burst = pl_gpio1 & phaser_enable;
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//PL_GPIO0
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assign pl_gpio0 = phaser_enable ? pl_txdata : pl_spi_mosi;
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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@ -160,6 +190,9 @@ module system_top (
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.spi_sdo_i(1'b0),
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.spi_sdo_o(pl_spi_mosi),
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.tdd_ext_sync(pl_burst),
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.txdata_o(pl_txdata),
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.tx_clk_out (tx_clk_out),
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.tx_data_out (tx_data_out),
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.tx_frame_out (tx_frame_out),
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