ad9081_fmca_ebz/common: Connect sync at TPL level
Reset CPACK from ADC TPL so during armed capture clear the cpack to avoid capturing old samples. Reset UNPACK with TPL to clear upack during armed transfers to avoid sending old data.main
Laszlo Nagy
Laszlo Nagy
parent
8ec657315c
commit
45dae0f3d3
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@ -347,8 +347,6 @@ ad_connect $sys_dma_resetn $adc_data_offload_name/m_axis_aresetn
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ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
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ad_connect tx_device_clk_rstgen/peripheral_aresetn $dac_data_offload_name/m_axis_aresetn
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ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn
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ad_connect $sys_dma_resetn $dac_data_offload_name/s_axis_aresetn
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ad_connect rx_device_clk_rstgen/peripheral_reset util_mxfe_cpack/reset
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ad_connect tx_device_clk_rstgen/peripheral_reset util_mxfe_upack/reset
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ad_connect $sys_dma_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
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ad_connect $sys_dma_resetn axi_mxfe_rx_dma/m_dest_axi_aresetn
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ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn
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ad_connect $sys_dma_resetn axi_mxfe_tx_dma/m_src_axi_aresetn
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ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
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ad_connect $sys_cpu_resetn $dac_data_offload_name/s_axi_aresetn
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@ -445,6 +443,57 @@ if {$ADI_PHY_SEL == 1} {
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make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial]
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make_bd_intf_pins_external [get_bd_intf_pins jesd204_phy/GT_Serial]
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}
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}
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#
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# Sync at TPL level
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#
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create_bd_port -dir I ext_sync_in
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# Enable ADC external sync
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ad_ip_parameter rx_mxfe_tpl_core/adc_tpl_core CONFIG.EXT_SYNC 1
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ad_connect ext_sync_in rx_mxfe_tpl_core/adc_tpl_core/adc_sync_in
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# Enable DAC external sync
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ad_ip_parameter tx_mxfe_tpl_core/dac_tpl_core CONFIG.EXT_SYNC 1
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ad_connect ext_sync_in tx_mxfe_tpl_core/dac_tpl_core/dac_sync_in
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ad_ip_instance util_vector_logic manual_sync_or [list \
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C_SIZE 1 \
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C_OPERATION {or} \
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]
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ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out manual_sync_or/Op1
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ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out manual_sync_or/Op2
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ad_connect manual_sync_or/Res tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in
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ad_connect manual_sync_or/Res rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in
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# Reset pack cores
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ad_ip_instance util_reduced_logic cpack_rst_logic
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ad_ip_parameter cpack_rst_logic config.c_operation {or}
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ad_ip_parameter cpack_rst_logic config.c_size {2}
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ad_ip_instance xlconcat cpack_reset_sources
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ad_ip_parameter cpack_reset_sources config.num_ports {2}
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ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0
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ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1
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ad_connect cpack_reset_sources/dout cpack_rst_logic/op1
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ad_connect cpack_rst_logic/res util_mxfe_cpack/reset
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# Reset unpack cores
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ad_ip_instance util_reduced_logic upack_rst_logic
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ad_ip_parameter upack_rst_logic config.c_operation {or}
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ad_ip_parameter upack_rst_logic config.c_size {2}
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ad_ip_instance xlconcat upack_reset_sources
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ad_ip_parameter upack_reset_sources config.num_ports {2}
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ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0
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ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1
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ad_connect upack_reset_sources/dout upack_rst_logic/op1
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ad_connect upack_rst_logic/res util_mxfe_upack/reset
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if {$TDD_SUPPORT} {
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if {$TDD_SUPPORT} {
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ad_ip_instance util_tdd_sync tdd_sync_0
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ad_ip_instance util_tdd_sync tdd_sync_0
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ad_connect tx_device_clk tdd_sync_0/clk
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ad_connect tx_device_clk tdd_sync_0/clk
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@ -467,11 +516,8 @@ if {$TDD_SUPPORT} {
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ad_connect axi_tdd_0/tdd_tx_valid $dac_data_offload_name/sync_ext
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ad_connect axi_tdd_0/tdd_tx_valid $dac_data_offload_name/sync_ext
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ad_connect axi_tdd_0/tdd_rx_valid $adc_data_offload_name/sync_ext
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ad_connect axi_tdd_0/tdd_rx_valid $adc_data_offload_name/sync_ext
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delete_bd_objs [get_bd_nets rx_device_clk_rstgen_peripheral_reset]
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ad_ip_parameter cpack_rst_logic CONFIG.C_SIZE {3}
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ad_ip_parameter cpack_reset_sources CONFIG.NUM_PORTS {3}
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ad_ip_instance util_vector_logic cpack_rst_logic
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ad_ip_parameter cpack_rst_logic CONFIG.C_OPERATION {OR}
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ad_ip_parameter cpack_rst_logic CONFIG.C_SIZE {1}
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if {[get_files -quiet "ad_edge_detect.v"] == ""} {
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if {[get_files -quiet "ad_edge_detect.v"] == ""} {
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add_files -norecurse -fileset sources_1 "$ad_hdl_dir/library/common/ad_edge_detect.v"
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add_files -norecurse -fileset sources_1 "$ad_hdl_dir/library/common/ad_edge_detect.v"
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@ -483,9 +529,7 @@ if {$TDD_SUPPORT} {
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ad_connect axi_tdd_0/tdd_rx_valid mxfe_cpack_edge_detector/signal_in
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ad_connect axi_tdd_0/tdd_rx_valid mxfe_cpack_edge_detector/signal_in
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ad_connect rx_device_clk_rstgen/peripheral_reset cpack_rst_logic/Op1
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ad_connect mxfe_cpack_edge_detector/signal_out cpack_reset_sources/In2
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ad_connect mxfe_cpack_edge_detector/signal_out cpack_rst_logic/Op2
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ad_connect cpack_rst_logic/Res util_mxfe_cpack/reset
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} else {
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} else {
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ad_connect GND $dac_data_offload_name/sync_ext
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ad_connect GND $dac_data_offload_name/sync_ext
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