From 45f2fbf3c04388aa0271d4ec3b86bc6030221489 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 8 Nov 2017 14:34:30 +0200 Subject: [PATCH] fmcjesdadc1: Update A10GX/A10SOC projects to the ADI JESD framework --- projects/fmcjesdadc1/a10gx/system_constr.sdc | 4 +- projects/fmcjesdadc1/a10gx/system_top.v | 6 +- projects/fmcjesdadc1/a10soc/system_constr.sdc | 5 +- projects/fmcjesdadc1/a10soc/system_top.v | 6 +- .../fmcjesdadc1/common/fmcjesdadc1_qsys.tcl | 106 ++++++++---------- 5 files changed, 53 insertions(+), 74 deletions(-) diff --git a/projects/fmcjesdadc1/a10gx/system_constr.sdc b/projects/fmcjesdadc1/a10gx/system_constr.sdc index ba29d7387..d97b807e4 100644 --- a/projects/fmcjesdadc1/a10gx/system_constr.sdc +++ b/projects/fmcjesdadc1/a10gx/system_constr.sdc @@ -1,14 +1,12 @@ create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}] derive_pll_clocks derive_clock_uncertainty set_false_path -to [get_registers *sysref_en_m1*] set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*] -set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}] -set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*] # flash interface diff --git a/projects/fmcjesdadc1/a10gx/system_top.v b/projects/fmcjesdadc1/a10gx/system_top.v index bec85e074..0348eee25 100644 --- a/projects/fmcjesdadc1/a10gx/system_top.v +++ b/projects/fmcjesdadc1/a10gx/system_top.v @@ -161,13 +161,9 @@ module system_top ( system_bd i_system_bd ( .rx_core_clk_clk (rx_clk), - .rx_data_0_rx_serial_data (rx_data[0]), - .rx_data_1_rx_serial_data (rx_data[1]), - .rx_data_2_rx_serial_data (rx_data[2]), - .rx_data_3_rx_serial_data (rx_data[3]), + .rx_serial_data_rx_serial_data (rx_data), .rx_ip_data_data (rx_ip_data), .rx_ip_data_valid (), - .rx_ip_data_ready (1'b1), .rx_ip_data_0_data (rx_ip_data[63:0]), .rx_ip_data_0_valid (1'b1), .rx_ip_data_0_ready (), diff --git a/projects/fmcjesdadc1/a10soc/system_constr.sdc b/projects/fmcjesdadc1/a10soc/system_constr.sdc index 72c287cc6..0f6db4782 100644 --- a/projects/fmcjesdadc1/a10soc/system_constr.sdc +++ b/projects/fmcjesdadc1/a10soc/system_constr.sdc @@ -2,13 +2,12 @@ # qsys- automatically infers these clocks create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "4.000 ns" -name ref_clk [get_ports {ref_clk}] derive_pll_clocks derive_clock_uncertainty set_false_path -to [get_registers *sysref_en_m1*] set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] -set_false_path -from [get_clocks {sys_clk_100mhz}] -through [get_nets *altera_jesd204*] -to [get_clocks *outclk0*] -set_false_path -from [get_clocks *outclk0*] -through [get_nets *altera_jesd204*] -to [get_clocks {sys_clk_100mhz}] -set_false_path -to [get_registers *altera_jesd204_rx_csr_inst|phy_csr_rx_pcfifo_full_latched*] + diff --git a/projects/fmcjesdadc1/a10soc/system_top.v b/projects/fmcjesdadc1/a10soc/system_top.v index c0d2b2333..6e410a858 100644 --- a/projects/fmcjesdadc1/a10soc/system_top.v +++ b/projects/fmcjesdadc1/a10soc/system_top.v @@ -160,13 +160,9 @@ module system_top ( system_bd i_system_bd ( .rx_core_clk_clk (rx_clk), - .rx_data_0_rx_serial_data (rx_data[0]), - .rx_data_1_rx_serial_data (rx_data[1]), - .rx_data_2_rx_serial_data (rx_data[2]), - .rx_data_3_rx_serial_data (rx_data[3]), + .rx_serial_data_rx_serial_data (rx_data), .rx_ip_data_data (rx_ip_data), .rx_ip_data_valid (), - .rx_ip_data_ready (1'b1), .rx_ip_data_0_data (rx_ip_data[63:0]), .rx_ip_data_0_valid (1'b1), .rx_ip_data_0_ready (), diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl index 1101f7fdb..ab23898b9 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_qsys.tcl @@ -1,76 +1,52 @@ # ad9250-xcvr -add_instance avl_ad9250_xcvr avl_adxcvr -set_instance_parameter_value avl_ad9250_xcvr {ID} {0} -set_instance_parameter_value avl_ad9250_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value avl_ad9250_xcvr {PCS_CONFIG} {JESD_PCS_CFG2} -set_instance_parameter_value avl_ad9250_xcvr {LANE_RATE} {5000.0} -set_instance_parameter_value avl_ad9250_xcvr {REFCLK_FREQUENCY} {250.0} -set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_LANES} {4} -set_instance_parameter_value avl_ad9250_xcvr {NUM_OF_CONVS} {4} -set_instance_parameter_value avl_ad9250_xcvr {FRM_BCNT} {4} -set_instance_parameter_value avl_ad9250_xcvr {FRM_SCNT} {1} -set_instance_parameter_value avl_ad9250_xcvr {MF_FCNT} {32} -set_instance_parameter_value avl_ad9250_xcvr {HD} {0} +add_instance ad9250_jesd204 adi_jesd204 +set_instance_parameter_value ad9250_jesd204 {ID} {0} +set_instance_parameter_value ad9250_jesd204 {TX_OR_RX_N} {0} +set_instance_parameter_value ad9250_jesd204 {LANE_RATE} {5000.0} +set_instance_parameter_value ad9250_jesd204 {REFCLK_FREQUENCY} {250.0} +set_instance_parameter_value ad9250_jesd204 {NUM_OF_LANES} {4} +set_instance_parameter_value ad9250_jesd204 {SOFT_PCS} {false} -add_connection sys_clk.clk avl_ad9250_xcvr.sys_clk -add_connection sys_clk.clk_reset avl_ad9250_xcvr.sys_resetn +add_connection sys_clk.clk ad9250_jesd204.sys_clk +add_connection sys_clk.clk_reset ad9250_jesd204.sys_resetn add_interface rx_ref_clk clock sink -set_interface_property rx_ref_clk EXPORT_OF avl_ad9250_xcvr.ref_clk -add_interface rx_data_0 conduit end -set_interface_property rx_data_0 EXPORT_OF avl_ad9250_xcvr.rx_data_0 -add_interface rx_data_1 conduit end -set_interface_property rx_data_1 EXPORT_OF avl_ad9250_xcvr.rx_data_1 -add_interface rx_data_2 conduit end -set_interface_property rx_data_2 EXPORT_OF avl_ad9250_xcvr.rx_data_2 -add_interface rx_data_3 conduit end -set_interface_property rx_data_3 EXPORT_OF avl_ad9250_xcvr.rx_data_3 +set_interface_property rx_ref_clk EXPORT_OF ad9250_jesd204.ref_clk +add_interface rx_serial_data conduit end +set_interface_property rx_serial_data EXPORT_OF ad9250_jesd204.serial_data add_interface rx_sysref conduit end -set_interface_property rx_sysref EXPORT_OF avl_ad9250_xcvr.sysref +set_interface_property rx_sysref EXPORT_OF ad9250_jesd204.sysref add_interface rx_sync conduit end -set_interface_property rx_sync EXPORT_OF avl_ad9250_xcvr.sync +set_interface_property rx_sync EXPORT_OF ad9250_jesd204.sync add_interface rx_ip_sof conduit end -set_interface_property rx_ip_sof EXPORT_OF avl_ad9250_xcvr.ip_sof +set_interface_property rx_ip_sof EXPORT_OF ad9250_jesd204.link_sof add_interface rx_ip_data avalon_streaming source -set_interface_property rx_ip_data EXPORT_OF avl_ad9250_xcvr.ip_data - -# ad9250-xcvr - -add_instance axi_ad9250_xcvr axi_adxcvr -set_instance_parameter_value axi_ad9250_xcvr {ID} {0} -set_instance_parameter_value axi_ad9250_xcvr {TX_OR_RX_N} {0} -set_instance_parameter_value axi_ad9250_xcvr {NUM_OF_LANES} {4} - -add_connection sys_clk.clk axi_ad9250_xcvr.s_axi_clock -add_connection sys_clk.clk_reset axi_ad9250_xcvr.s_axi_reset -add_connection axi_ad9250_xcvr.if_up_rst avl_ad9250_xcvr.rst -add_connection avl_ad9250_xcvr.ready axi_ad9250_xcvr.ready -add_connection axi_ad9250_xcvr.core_pll_locked avl_ad9250_xcvr.core_pll_locked +set_interface_property rx_ip_data EXPORT_OF ad9250_jesd204.link_data # ad9250 add_instance axi_ad9250_core_0 axi_ad9250 set_instance_parameter_value axi_ad9250_core_0 {ID} {0} -add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_0.if_rx_clk +add_connection ad9250_jesd204.link_clk axi_ad9250_core_0.if_rx_clk +add_connection sys_clk.clk_reset axi_ad9250_core_0.s_axi_reset +add_connection sys_clk.clk axi_ad9250_core_0.s_axi_clock add_interface rx_ip_sof_0 conduit end set_interface_property rx_ip_sof_0 EXPORT_OF axi_ad9250_core_0.if_rx_sof add_interface rx_ip_data_0 avalon_streaming sink set_interface_property rx_ip_data_0 EXPORT_OF axi_ad9250_core_0.if_rx_data -add_connection sys_clk.clk_reset axi_ad9250_core_0.s_axi_reset -add_connection sys_clk.clk axi_ad9250_core_0.s_axi_clock add_instance axi_ad9250_core_1 axi_ad9250 set_instance_parameter_value axi_ad9250_core_1 {ID} {1} -add_connection avl_ad9250_xcvr.core_clk axi_ad9250_core_1.if_rx_clk +add_connection ad9250_jesd204.link_clk axi_ad9250_core_1.if_rx_clk +add_connection sys_clk.clk_reset axi_ad9250_core_1.s_axi_reset +add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock add_interface rx_ip_sof_1 conduit end set_interface_property rx_ip_sof_1 EXPORT_OF axi_ad9250_core_1.if_rx_sof add_interface rx_ip_data_1 avalon_streaming sink set_interface_property rx_ip_data_1 EXPORT_OF axi_ad9250_core_1.if_rx_data -add_connection sys_clk.clk_reset axi_ad9250_core_1.s_axi_reset -add_connection sys_clk.clk axi_ad9250_core_1.s_axi_clock # ad9250-pack @@ -79,7 +55,7 @@ set_instance_parameter_value util_ad9250_cpack_0 {CHANNEL_DATA_WIDTH} {32} set_instance_parameter_value util_ad9250_cpack_0 {NUM_OF_CHANNELS} {2} add_connection sys_clk.clk_reset util_ad9250_cpack_0.if_adc_rst -add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_0.if_adc_clk +add_connection ad9250_jesd204.link_clk util_ad9250_cpack_0.if_adc_clk add_connection axi_ad9250_core_0.adc_ch_0 util_ad9250_cpack_0.adc_ch_0 add_connection axi_ad9250_core_0.adc_ch_1 util_ad9250_cpack_0.adc_ch_1 @@ -88,7 +64,7 @@ set_instance_parameter_value util_ad9250_cpack_1 {CHANNEL_DATA_WIDTH} {32} set_instance_parameter_value util_ad9250_cpack_1 {NUM_OF_CHANNELS} {2} add_connection sys_clk.clk_reset util_ad9250_cpack_1.if_adc_rst -add_connection avl_ad9250_xcvr.core_clk util_ad9250_cpack_1.if_adc_clk +add_connection ad9250_jesd204.link_clk util_ad9250_cpack_1.if_adc_clk add_connection axi_ad9250_core_1.adc_ch_0 util_ad9250_cpack_1.adc_ch_0 add_connection axi_ad9250_core_1.adc_ch_1 util_ad9250_cpack_1.adc_ch_1 @@ -102,8 +78,10 @@ set_instance_parameter_value axi_ad9250_dma_0 {SYNC_TRANSFER_START} {1} set_instance_parameter_value axi_ad9250_dma_0 {DMA_LENGTH_WIDTH} {24} set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_SRC} {64} set_instance_parameter_value axi_ad9250_dma_0 {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_ad9250_dma_0 {CYCLIC} {0} +set_instance_parameter_value axi_ad9250_dma_0 {DMA_2D_TRANSFER} {0} -add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_0.if_fifo_wr_clk +add_connection ad9250_jesd204.link_clk axi_ad9250_dma_0.if_fifo_wr_clk add_connection util_ad9250_cpack_0.if_adc_valid axi_ad9250_dma_0.if_fifo_wr_en add_connection util_ad9250_cpack_0.if_adc_sync axi_ad9250_dma_0.if_fifo_wr_sync add_connection util_ad9250_cpack_0.if_adc_data axi_ad9250_dma_0.if_fifo_wr_din @@ -120,8 +98,10 @@ set_instance_parameter_value axi_ad9250_dma_1 {DMA_TYPE_DEST} {0} set_instance_parameter_value axi_ad9250_dma_1 {SYNC_TRANSFER_START} {1} set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_SRC} {64} set_instance_parameter_value axi_ad9250_dma_1 {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_ad9250_dma_1 {CYCLIC} {0} +set_instance_parameter_value axi_ad9250_dma_1 {DMA_2D_TRANSFER} {0} -add_connection avl_ad9250_xcvr.core_clk axi_ad9250_dma_1.if_fifo_wr_clk +add_connection ad9250_jesd204.link_clk axi_ad9250_dma_1.if_fifo_wr_clk add_connection util_ad9250_cpack_1.if_adc_valid axi_ad9250_dma_1.if_fifo_wr_en add_connection util_ad9250_cpack_1.if_adc_sync axi_ad9250_dma_1.if_fifo_wr_sync add_connection util_ad9250_cpack_1.if_adc_data axi_ad9250_dma_1.if_fifo_wr_din @@ -134,19 +114,28 @@ add_connection sys_dma_clk.clk axi_ad9250_dma_1.m_dest_axi_clock # core-clock add_instance rx_core_clk altera_clock_bridge -add_connection avl_ad9250_xcvr.core_clk rx_core_clk.in_clk +add_connection ad9250_jesd204.link_clk rx_core_clk.in_clk add_interface rx_core_clk clock source set_interface_property rx_core_clk EXPORT_OF rx_core_clk.out_clk +# +# reconfig sharing + +for {set i 0} {$i < 4} {incr i} { + add_instance avl_adxcfg_${i} avl_adxcfg + add_connection sys_clk.clk avl_adxcfg_${i}.rcfg_clk + add_connection sys_clk.clk_reset avl_adxcfg_${i}.rcfg_reset_n + add_connection avl_adxcfg_${i}.rcfg_m0 ad9250_jesd204.phy_reconfig_${i} +} # addresses -ad_cpu_interconnect 0x00010000 avl_ad9250_xcvr.phy_reconfig_0 -ad_cpu_interconnect 0x00012000 avl_ad9250_xcvr.phy_reconfig_1 -ad_cpu_interconnect 0x00014000 avl_ad9250_xcvr.phy_reconfig_2 -ad_cpu_interconnect 0x00016000 avl_ad9250_xcvr.phy_reconfig_3 -ad_cpu_interconnect 0x0001b000 avl_ad9250_xcvr.core_pll_reconfig -ad_cpu_interconnect 0x0001c000 avl_ad9250_xcvr.ip_reconfig -ad_cpu_interconnect 0x00030000 axi_ad9250_xcvr.s_axi +ad_cpu_interconnect 0x00030000 ad9250_jesd204.link_reconfig +ad_cpu_interconnect 0x00034000 ad9250_jesd204.link_management +ad_cpu_interconnect 0x00035000 ad9250_jesd204.link_pll_reconfig +ad_cpu_interconnect 0x00038000 avl_adxcfg_0.rcfg_s0 +ad_cpu_interconnect 0x00039000 avl_adxcfg_1.rcfg_s0 +ad_cpu_interconnect 0x0003a000 avl_adxcfg_2.rcfg_s0 +ad_cpu_interconnect 0x0003b000 avl_adxcfg_3.rcfg_s0 ad_cpu_interconnect 0x00040000 axi_ad9250_core_0.s_axi ad_cpu_interconnect 0x00050000 axi_ad9250_core_1.s_axi ad_cpu_interconnect 0x00060000 axi_ad9250_dma_0.s_axi @@ -159,6 +148,7 @@ ad_dma_interconnect axi_ad9250_dma_1.m_dest_axi # interrupts +ad_cpu_interrupt 10 ad9250_jesd204.interrupt ad_cpu_interrupt 11 axi_ad9250_dma_0.interrupt_sender ad_cpu_interrupt 12 axi_ad9250_dma_1.interrupt_sender