From 46271a76208f31ad40e990df6f5e28985e7fab83 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 2 Mar 2015 16:44:42 +0200 Subject: [PATCH] motcon2_fmc: added xadc, added constraints for several IP internal clocks --- .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 32 ++--- projects/motcon2_fmc/zed/system_constr.xdc | 128 ++++++++++-------- projects/motcon2_fmc/zed/system_top.v | 15 +- 3 files changed, 98 insertions(+), 77 deletions(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 5e8be1a6b..e3ffa0597 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -83,8 +83,8 @@ set spi_miso_i [create_bd_port -dir I spi_miso_i] # xadc interface - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 #create_bd_port -dir O -from 4 -to 0 muxaddr_out @@ -217,14 +217,14 @@ set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] # xadc - #set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ] - #set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core - #set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core - #set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core - #set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core - #set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core - #set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core - #set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core + set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ] + set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core + set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {false} ] $xadc_core + set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_core + set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core + set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core + set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core + set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core # additional interconnect set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ] @@ -587,10 +587,10 @@ connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_r] # xadc - #connect_bd_net -net sys_100m_clk [get_bd_pins xadc_core/s_axi_aclk] $sys_100m_clk_source - #connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_core/s_axi_aresetn] $sys_100m_resetn_source - #connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_core/Vaux0] [get_bd_intf_ports Vaux0] - #connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_core/Vaux8] [get_bd_intf_ports Vaux8] + connect_bd_net -net sys_100m_clk [get_bd_pins xadc_core/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_core/s_axi_aresetn] $sys_100m_resetn_source + connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_core/Vaux0] [get_bd_intf_ports Vaux0] + connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_core/Vaux8] [get_bd_intf_ports Vaux8] #connect_bd_net -net xadc_muxout [get_bd_pins /xadc_core/muxaddr_out] [get_bd_ports muxaddr_out] # iic @@ -640,7 +640,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M20_ARESETN] $sys_100m_resetn_source connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins iic_ee2/S_AXI] -boundary_type upper [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] -# connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins xadc_core/s_axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins xadc_core/s_axi_lite] connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins speed_detector_m1/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins speed_detector_m1_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins speed_detector_m2/s_axi] @@ -695,7 +695,7 @@ create_bd_addr_seg -range 0x10000 -offset 0x40540000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2_dma/s_axi/axi_lite] SEG_data_s_d2_dma create_bd_addr_seg -range 0x10000 -offset 0x40550000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2_dma/s_axi/axi_lite] SEG_data_c_m2_dma create_bd_addr_seg -range 0x10000 -offset 0x40560000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2_dma/s_axi/axi_lite] SEG_data_c2_dma -# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_core/s_axi_lite/Reg] SEG_data_xadc + create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_core/s_axi_lite/Reg] SEG_data_xadc create_bd_addr_seg -range 0x10000 -offset 0x41510000 $sys_addr_cntrl_space [get_bd_addr_segs iic_ee2/S_AXI/Reg] SEG_iic_ee2_Reg create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index 5b41ab5c8..d4546f3f6 100644 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -1,11 +1,5 @@ -#DEBUG - # Motor Control -#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 -#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 -#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 -#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[0]}] set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[1]}] @@ -55,15 +49,19 @@ set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}] set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}] +#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 #set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}] #set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}] #set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}] #set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}] -#set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] -#set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] -#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] -#set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8] # SPI set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sel1_rdc ] @@ -111,20 +109,51 @@ set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_ set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}] set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}] +create_generated_clock -name pwm_ctrl_1 -source [get_pins i_system_wrapper/system_i/controller_m1/inst/ref_clk] \ +-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m1/inst/pwm_gen_clk_reg/Q] +create_generated_clock -name pwm_ctrl_2 -source [get_pins i_system_wrapper/system_i/controller_m2/inst/ref_clk] \ +-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m2/inst/pwm_gen_clk_reg/Q] +set_clock_groups -asynchronous \ + -group [get_clocks {pwm_ctrl_1}] \ + -group [get_clocks {pwm_ctrl_2}] + +create_generated_clock -name cm1_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ia_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm1_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ib_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm1_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/vbus_if/filter/word_count_reg[7]/Q] + +set_clock_groups -asynchronous \ + -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] + +create_generated_clock -name cm2_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ia_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ib_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm2_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/vbus_if/filter/word_count_reg[7]/Q] + +set_clock_groups -asynchronous \ + -group [get_clocks {cm2_ia cm2_ib cm2_vbus }] + # Ethernet common set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] -set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2] -set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2] -set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3] -set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3] -set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] +create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] + +set_clock_groups -logically_exclusive \ + -group [get_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks {clk_out4_system_sys_audio_clkgen_0_1 }] + +set_clock_groups -asynchronous \ + -group [get_clocks {mdio_mdc}] \ + -group [get_clocks -include_generated_clocks {clk_out1_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks -include_generated_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks -include_generated_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks -include_generated_clocks {clk_out4_system_sys_audio_clkgen_0_1}] # Ethernet 1 @@ -140,27 +169,22 @@ set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_et set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max 1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -hold +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -setup +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -setup +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -hold +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -hold -set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -setup 0 -set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -hold -1 +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -setup +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -setup +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -hold +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -hold -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay - -# Ethernet 2 - -# Clock Period Constraints +set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to [get_clocks rgmii_rx_ctl_clk_s] -setup 0 create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] #set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] #set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] @@ -169,28 +193,26 @@ create_clock -name eth2_rx_clk_vir -period 8 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] + set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max 1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -0.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -0.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -hold +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold -set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -setup 0 -set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -hold -1 - -set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup -set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup -set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold -set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -setup +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -setup +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -hold +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -hold set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] diff --git a/projects/motcon2_fmc/zed/system_top.v b/projects/motcon2_fmc/zed/system_top.v index 2d5db19bc..e4801d956 100644 --- a/projects/motcon2_fmc/zed/system_top.v +++ b/projects/motcon2_fmc/zed/system_top.v @@ -118,11 +118,11 @@ module system_top ( pwm_m2_dh_o, pwm_m2_dl_o, vt_enable, -/* vauxn0, + vauxn0, vauxn8, vauxp0, vauxp8, - muxaddr_out,*/ +/* muxaddr_out,*/ i2s_mclk, i2s_bclk, @@ -226,14 +226,14 @@ module system_top ( output pwm_m2_cl_o; output pwm_m2_dh_o; output pwm_m2_dl_o; - + output vt_enable; -/* input vauxn0; + input vauxn0; input vauxn8; input vauxp0; input vauxp8; - output [ 3:0] muxaddr_out;*/ +/* output [ 3:0] muxaddr_out;*/ output spdif; @@ -243,7 +243,6 @@ module system_top ( output i2s_sdata_out; input i2s_sdata_in; - inout iic_scl; inout iic_sda; inout [ 1:0] iic_mux_scl; @@ -437,11 +436,11 @@ module system_top ( .pwm_m2_bl_o(pwm_m2_bl_o), .pwm_m2_ch_o(pwm_m2_ch_o), .pwm_m2_cl_o(pwm_m2_cl_o), -/* .Vaux0_v_n(vauxn0), + .Vaux0_v_n(vauxn0), .Vaux0_v_p(vauxp0), .Vaux8_v_n(vauxn8), .Vaux8_v_p(vauxp8), - .muxaddr_out(muxaddr_out),*/ + /*.muxaddr_out(muxaddr_out),*/ .i2s_bclk (i2s_bclk), .i2s_lrclk (i2s_lrclk), .i2s_mclk (i2s_mclk),