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cftl_std: Updated project. Switched to PS7 gpio. Renamed signals.

main
Adrian Costina 2015-01-23 14:11:33 +02:00
parent 9672271155
commit 463a3bbc88
3 changed files with 102 additions and 77 deletions
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66
projects/cftl_std/common/cftl_std_bd.tcl
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@ -3,27 +3,41 @@
set gpio_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_cftl ] set gpio_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 gpio_cftl ]
set iic_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cftl ] set iic_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cftl ]
set spi1_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi1_cftl ]
set spi_cftl [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:spi_rtl:1.0 spi_cftl ]
set spi0_cftl_csn_i [create_bd_port -dir I spi0_cftl_csn_i]
set spi0_cftl_csn_o [create_bd_port -dir O spi0_cftl_csn_o]
set spi0_cftl_sclk_i [create_bd_port -dir I spi0_cftl_sclk_i]
set spi0_cftl_sclk_o [create_bd_port -dir O spi0_cftl_sclk_o]
set spi0_cftl_mosi_i [create_bd_port -dir I spi0_cftl_mosi_i]
set spi0_cftl_mosi_o [create_bd_port -dir O spi0_cftl_mosi_o]
set spi0_cftl_miso_i [create_bd_port -dir I spi0_cftl_miso_i]
set spi1_cftl_sclk_i [create_bd_port -dir I spi1_cftl_sclk_i]
set spi1_cftl_sclk_o [create_bd_port -dir O spi1_cftl_sclk_o]
set spi1_cftl_csn_i [create_bd_port -dir I spi1_cftl_csn_i]
set spi1_cftl_csn0_o [create_bd_port -dir O spi1_cftl_csn0_o]
set spi1_cftl_csn1_o [create_bd_port -dir O spi1_cftl_csn1_o]
set spi1_cftl_mosi_i [create_bd_port -dir I spi1_cftl_mosi_i]
set spi1_cftl_mosi_o [create_bd_port -dir O spi1_cftl_mosi_o]
set spi1_cftl_miso_i [create_bd_port -dir I spi1_cftl_miso_i]
# gpio_cftl # gpio_cftl
set axi_gpio_cftl [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_cftl ] set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {34}] $sys_ps7
set_property -dict [ list CONFIG.C_GPIO_WIDTH {2} ] $axi_gpio_cftl set_property LEFT 33 [get_bd_ports GPIO_I]
set_property LEFT 33 [get_bd_ports GPIO_O]
set_property LEFT 33 [get_bd_ports GPIO_T]
# spi0, spi1, iic # spi0, spi1, iic
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} ] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} ] $sys_ps7 set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} ] $sys_ps7
set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} ] $sys_ps7 set_property -dict [list CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {1} ] $sys_ps7
# interconnect # interconnect
set_property -dict [list CONFIG.NUM_MI {8}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
# gpio_cftl
connect_bd_intf_net -intf_net axi_gpio_cftl_GPIO [get_bd_intf_ports gpio_cftl] [get_bd_intf_pins axi_gpio_cftl/GPIO]
# iic cftl # iic cftl
@ -31,25 +45,21 @@
# spi0 cftl # spi0 cftl
connect_bd_intf_net -intf_net sys_ps7_SPI_0 [get_bd_intf_ports spi_cftl] [get_bd_intf_pins sys_ps7/SPI_0] connect_bd_net -net spi0_cftl_csn_i [get_bd_ports spi0_cftl_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi0_cftl_csn_o [get_bd_ports spi0_cftl_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O]
connect_bd_net -net spi0_cftl_sclk_i [get_bd_ports spi0_cftl_sclk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi0_cftl_sclk_o [get_bd_ports spi0_cftl_sclk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi0_cftl_mosi_i [get_bd_ports spi0_cftl_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi0_cftl_mosi_o [get_bd_ports spi0_cftl_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi0_cftl_miso_i [get_bd_ports spi0_cftl_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I]
# spi1 cftl # spi1 cftl
connect_bd_intf_net -intf_net sys_ps7_SPI_1 [get_bd_intf_ports spi1_cftl] [get_bd_intf_pins sys_ps7/SPI_1] connect_bd_net -net spi1_cftl_csn_i [get_bd_ports spi1_cftl_csn_i] [get_bd_pins sys_ps7/SPI1_SS_I]
connect_bd_net -net spi1_cftl_csn0_o [get_bd_ports spi1_cftl_csn0_o] [get_bd_pins sys_ps7/SPI1_SS_O]
# interconnect (cpu) connect_bd_net -net spi1_cftl_csn1_o [get_bd_ports spi1_cftl_csn1_o] [get_bd_pins sys_ps7/SPI1_SS1_O]
connect_bd_net -net spi1_cftl_sclk_i [get_bd_ports spi1_cftl_sclk_i] [get_bd_pins sys_ps7/SPI1_SCLK_I]
connect_bd_intf_net -intf_net axi_cpu_interconnect_M07_AXI [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_gpio_cftl/S_AXI] connect_bd_net -net spi1_cftl_sclk_o [get_bd_ports spi1_cftl_sclk_o] [get_bd_pins sys_ps7/SPI1_SCLK_O]
connect_bd_net -net spi1_cftl_mosi_i [get_bd_ports spi1_cftl_mosi_i] [get_bd_pins sys_ps7/SPI1_MOSI_I]
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source connect_bd_net -net spi1_cftl_mosi_o [get_bd_ports spi1_cftl_mosi_o] [get_bd_pins sys_ps7/SPI1_MOSI_O]
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source connect_bd_net -net spi1_cftl_miso_i [get_bd_ports spi1_cftl_miso_i] [get_bd_pins sys_ps7/SPI1_MISO_I]
# interconnects (gpio_cftl)
connect_bd_net -net sys_100m_clk [get_bd_pins axi_gpio_cftl/s_axi_aclk] $sys_100m_clk_source
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_gpio_cftl/s_axi_aresetn] $sys_100m_resetn_source
# address map
create_bd_addr_seg -range 0x10000 -offset 0x41200000 [get_bd_addr_spaces sys_ps7/Data] [get_bd_addr_segs axi_gpio_cftl/S_AXI/Reg] SEG_axi_gpio_cftl_Reg

26
projects/cftl_std/zed/system_constr.xdc
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@ -1,17 +1,17 @@
# CFTL # CFTL
set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi_cftl_ss_io]; # "JA1" set_property -dict {PACKAGE_PIN Y11 IOSTANDARD LVCMOS33} [get_ports spi0_csn]; # "JA1"
set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi_cftl_mosi_io]; # "JA2" set_property -dict {PACKAGE_PIN AA11 IOSTANDARD LVCMOS33} [get_ports spi0_mosi]; # "JA2"
set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi_cftl_miso_io]; # "JA3" set_property -dict {PACKAGE_PIN Y10 IOSTANDARD LVCMOS33} [get_ports spi0_miso]; # "JA3"
set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi_cftl_sck_io]; # "JA4" set_property -dict {PACKAGE_PIN AA9 IOSTANDARD LVCMOS33} [get_ports spi0_clk]; # "JA4"
set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports gpio_cftl_tri_io[0]]; # "JA9" set_property -dict {PACKAGE_PIN AB9 IOSTANDARD LVCMOS33} [get_ports gpio_cftl[0]]; # "JA9"
set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports gpio_cftl_tri_io[1]]; # "JA10" set_property -dict {PACKAGE_PIN AA8 IOSTANDARD LVCMOS33} [get_ports gpio_cftl[1]]; # "JA10"
set_property -dict {PACKAGE_PIN W12 IOSTANDARD LVCMOS33} [get_ports iic_cftl_scl_io]; # "JB1" set_property -dict {PACKAGE_PIN V10 IOSTANDARD LVCMOS33} [get_ports iic_cftl_scl_io]; # "JB3"
set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS33} [get_ports iic_cftl_sda_io]; # "JB2" set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS33} [get_ports iic_cftl_sda_io]; # "JB4"
set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_ss_io]; # "JC1_P" set_property -dict {PACKAGE_PIN AB7 IOSTANDARD LVCMOS33} [get_ports spi1_csn0]; # "JC1_P"
set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_mosi_io]; # "JC1_N" set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS33} [get_ports spi1_mosi]; # "JC1_N"
set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_miso_io]; # "JC2_P" set_property -dict {PACKAGE_PIN Y4 IOSTANDARD LVCMOS33} [get_ports spi1_miso]; # "JC2_P"
set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_sck_io]; # "JC2_N" set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS33} [get_ports spi1_clk]; # "JC2_N"
set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports spi1_cftl_ss1_o]; # "JC4_N" set_property -dict {PACKAGE_PIN U4 IOSTANDARD LVCMOS33} [get_ports spi1_csn1]; # "JC4_N"

87
projects/cftl_std/zed/system_top.v
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@ -88,18 +88,18 @@ module system_top (
iic_cftl_scl_io, iic_cftl_scl_io,
iic_cftl_sda_io, iic_cftl_sda_io,
spi_cftl_mosi_io, spi0_mosi,
spi_cftl_miso_io, spi0_miso,
spi_cftl_sck_io, spi0_clk,
spi_cftl_ss_io, spi0_csn,
spi1_cftl_mosi_io, spi1_mosi,
spi1_cftl_miso_io, spi1_miso,
spi1_cftl_sck_io, spi1_clk,
spi1_cftl_ss_io, spi1_csn0,
spi1_cftl_ss1_o, spi1_csn1,
gpio_cftl_tri_io, gpio_cftl,
otg_vbusoc); otg_vbusoc);
@ -150,26 +150,26 @@ module system_top (
inout iic_cftl_scl_io; inout iic_cftl_scl_io;
inout iic_cftl_sda_io; inout iic_cftl_sda_io;
inout spi_cftl_mosi_io; output spi0_mosi;
inout spi_cftl_miso_io; input spi0_miso;
inout spi_cftl_sck_io; output spi0_clk;
inout spi_cftl_ss_io; output spi0_csn;
inout spi1_cftl_mosi_io; output spi1_mosi;
inout spi1_cftl_miso_io; input spi1_miso;
inout spi1_cftl_sck_io; output spi1_clk;
inout spi1_cftl_ss_io; output spi1_csn0;
output spi1_cftl_ss1_o; output spi1_csn1;
inout [ 1:0] gpio_cftl_tri_io; inout [ 1:0] gpio_cftl;
input otg_vbusoc; input otg_vbusoc;
// internal signals // internal signals
wire [31:0] gpio_i; wire [33:0] gpio_i;
wire [31:0] gpio_o; wire [33:0] gpio_o;
wire [31:0] gpio_t; wire [33:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s; wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s; wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s; wire iic_mux_scl_t_s;
@ -183,11 +183,19 @@ module system_top (
ad_iobuf #( ad_iobuf #(
.DATA_WIDTH(32)) .DATA_WIDTH(32))
i_gpio_bd ( i_gpio_bd (
.dt(gpio_t), .dt(gpio_t[31:0]),
.di(gpio_o), .di(gpio_o[31:0]),
.do(gpio_i), .do(gpio_i[31:0]),
.dio(gpio_bd)); .dio(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2))
i_gpio_cftl (
.dt(gpio_t[33:32]),
.di(gpio_o[33:32]),
.do(gpio_i[33:32]),
.dio(gpio_cftl));
ad_iobuf #( ad_iobuf #(
.DATA_WIDTH(2)) .DATA_WIDTH(2))
i_iic_mux_scl ( i_iic_mux_scl (
@ -261,19 +269,26 @@ module system_top (
.ps_intr_8 (ps_intrs[8]), .ps_intr_8 (ps_intrs[8]),
.ps_intr_9 (ps_intrs[9]), .ps_intr_9 (ps_intrs[9]),
.iic_fmc_intr(ps_intrs[11]), .iic_fmc_intr(ps_intrs[11]),
.spi_cftl_io0_io(spi_cftl_mosi_io),
.spi_cftl_io1_io(spi_cftl_miso_io),
.spi_cftl_sck_io(spi_cftl_sck_io),
.spi_cftl_ss_io(spi_cftl_ss_io),
.spi1_cftl_io0_io(spi1_cftl_mosi_io),
.spi1_cftl_io1_io(spi1_cftl_miso_io),
.spi1_cftl_sck_io(spi1_cftl_sck_io),
.spi1_cftl_ss1_o(spi1_cftl_ss1_o),
.spi1_cftl_ss_io(spi1_cftl_ss_io),
.gpio_cftl_tri_io(gpio_cftl_tri_io),
.otg_vbusoc (otg_vbusoc), .otg_vbusoc (otg_vbusoc),
.spi0_cftl_csn_i (1'b1),
.spi0_cftl_csn_o (spi0_csn),
.spi0_cftl_miso_i (spi0_miso),
.spi0_cftl_mosi_i (1'b0),
.spi0_cftl_mosi_o (spi0_mosi),
.spi0_cftl_sclk_i (1'b0),
.spi0_cftl_sclk_o (spi0_clk),
.spi1_cftl_csn_i (1'b1),
.spi1_cftl_csn0_o (spi1_csn0),
.spi1_cftl_csn1_o (spi1_csn1),
.spi1_cftl_miso_i (spi1_miso),
.spi1_cftl_mosi_i (spi1_mosi),
.spi1_cftl_mosi_o (spi1_mosi),
.spi1_cftl_sclk_i (1'b0),
.spi1_cftl_sclk_o (spi1_clk),
.spdif (spdif)); .spdif (spdif));
endmodule endmodule
// *************************************************************************** // ***************************************************************************