diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl
index 81d0e63b0..b68b1ccbd 100755
--- a/library/axi_ad9144/axi_ad9144_hw.tcl
+++ b/library/axi_ad9144/axi_ad9144_hw.tcl
@@ -87,8 +87,6 @@ add_interface if_tx_clk clock end
 add_interface_port if_tx_clk tx_clk clk Input 1
 
 add_interface if_tx_data avalon_streaming start
-set_interface_property if_tx_data associatedClock if_tx_clk
-set_interface_property if_tx_data dataBitsPerSymbol 128*(PCORE_QUAD_DUAL_N+1)
 add_interface_port if_tx_data tx_data data Output 128*(PCORE_QUAD_DUAL_N+1)
 
 # dma interface
@@ -105,6 +103,10 @@ ad_alt_intf signal  dac_dunf      input   1
 
 proc p_axi_ad9144 {} {
 
+  set p_pcore_quad_dual_n [get_parameter_value "PCORE_QUAD_DUAL_N"]
+  set_interface_property if_tx_data associatedClock if_tx_clk
+  set_interface_property if_tx_data dataBitsPerSymbol [expr (128*($p_pcore_quad_dual_n+1))]
+
   if {[get_parameter_value PCORE_QUAD_DUAL_N] == 1} {
     ad_alt_intf signal  dac_valid_2   output  1
     ad_alt_intf signal  dac_enable_2  output  1
diff --git a/library/util_jesd_align/util_jesd_align.v b/library/util_jesd_align/util_jesd_align.v
new file mode 100644
index 000000000..b78e5383a
--- /dev/null
+++ b/library/util_jesd_align/util_jesd_align.v
@@ -0,0 +1,79 @@
+// ***************************************************************************
+// ***************************************************************************
+// Copyright 2011(c) Analog Devices, Inc.
+// 
+// All rights reserved.
+// 
+// Redistribution and use in source and binary forms, with or without modification,
+// are permitted provided that the following conditions are met:
+//     - Redistributions of source code must retain the above copyright
+//       notice, this list of conditions and the following disclaimer.
+//     - Redistributions in binary form must reproduce the above copyright
+//       notice, this list of conditions and the following disclaimer in
+//       the documentation and/or other materials provided with the
+//       distribution.
+//     - Neither the name of Analog Devices, Inc. nor the names of its
+//       contributors may be used to endorse or promote products derived
+//       from this software without specific prior written permission.
+//     - The use of this software may or may not infringe the patent rights
+//       of one or more patent holders.  This license does not release you
+//       from the requirement that you obtain separate licenses from these
+//       patent holders to use this software.
+//     - Use of the software either in source or binary form, must be run
+//       on or directly connected to an Analog Devices Inc. component.
+//    
+// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED.
+//
+// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
+// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 
+// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
+// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ***************************************************************************
+// ***************************************************************************
+
+`timescale 1ns/100ps
+
+module util_jesd_align (
+
+  // xcvr interface
+
+  rx_clk,
+  rx_ip_sof,
+  rx_ip_data,
+  rx_sof,
+  rx_data);
+
+  // parameters
+
+  parameter   NUM_OF_LANES = 2;
+
+  // xcvr interface
+
+  input                               rx_clk;
+  input   [ 3:0]                      rx_ip_sof;
+  input   [((NUM_OF_LANES*32)-1):0]   rx_ip_data;
+  output  [((NUM_OF_LANES* 1)-1):0]   rx_sof;
+  output  [((NUM_OF_LANES*32)-1):0]   rx_data;
+
+  // only for altera, xcvr+jesd do not frame align
+
+  genvar n;
+  generate
+  for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane
+  ad_jesd_align i_jesd_align (
+    .rx_clk (rx_clk),
+    .rx_ip_sof (rx_ip_sof),
+    .rx_ip_data (rx_ip_data[n*32+31:n*32]),
+    .rx_sof (rx_sof[n]),
+    .rx_data (rx_data[n*32+31:n*32]));
+  end
+  endgenerate
+
+endmodule
+
+// ***************************************************************************
+// ***************************************************************************
diff --git a/library/util_jesd_align/util_jesd_align_constr.xdc b/library/util_jesd_align/util_jesd_align_constr.xdc
new file mode 100644
index 000000000..e69de29bb
diff --git a/library/util_jesd_align/util_jesd_align_hw.tcl b/library/util_jesd_align/util_jesd_align_hw.tcl
new file mode 100644
index 000000000..82d64ded6
--- /dev/null
+++ b/library/util_jesd_align/util_jesd_align_hw.tcl
@@ -0,0 +1,51 @@
+
+
+package require -exact qsys 13.0
+source ../scripts/adi_env.tcl
+source ../scripts/adi_ip_alt.tcl
+
+
+set_module_property NAME util_jesd_align
+set_module_property DESCRIPTION "JESD Align Utility"
+set_module_property VERSION 1.0
+set_module_property DISPLAY_NAME util_jesd_align
+set_module_property ELABORATION_CALLBACK p_util_jesd_align
+
+# files
+
+add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
+set_fileset_property quartus_synth TOP_LEVEL util_jesd_align
+add_fileset_file ad_jesd_align.v         VERILOG PATH $ad_hdl_dir/library/common/altera/ad_jesd_align.v
+add_fileset_file util_jesd_align.v       VERILOG PATH util_jesd_align.v TOP_LEVEL_FILE
+
+# parameters
+
+add_parameter NUM_OF_LANES INTEGER 0
+set_parameter_property NUM_OF_LANES DEFAULT_VALUE 2
+set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
+set_parameter_property NUM_OF_LANES TYPE INTEGER
+set_parameter_property NUM_OF_LANES UNITS None
+set_parameter_property NUM_OF_LANES HDL_PARAMETER true
+
+# transceiver interface
+
+add_interface if_rx_clk clock end
+add_interface_port if_rx_clk rx_clk clk Input 1
+
+add_interface if_rx_ip_data avalon_streaming end
+add_interface_port if_rx_ip_data rx_ip_data data Input 32*NUM_OF_LANES
+
+add_interface if_rx_data avalon_streaming start
+add_interface_port if_rx_data rx_data data Output 32*NUM_OF_LANES
+
+ad_alt_intf signal rx_ip_sof input 4 export
+ad_alt_intf signal rx_sof output NUM_OF_LANES export
+
+proc p_util_jesd_align {} {
+
+  set p_num_of_lanes [get_parameter_value "NUM_OF_LANES"]
+  set_interface_property if_rx_ip_data associatedClock if_rx_clk
+  set_interface_property if_rx_ip_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
+  set_interface_property if_rx_data associatedClock if_rx_clk
+  set_interface_property if_rx_data dataBitsPerSymbol [expr (32*$p_num_of_lanes)]
+}
diff --git a/library/util_jesd_align/util_jesd_align_ip.tcl b/library/util_jesd_align/util_jesd_align_ip.tcl
new file mode 100644
index 000000000..3165ae1b2
--- /dev/null
+++ b/library/util_jesd_align/util_jesd_align_ip.tcl
@@ -0,0 +1,18 @@
+# ip
+
+source ../scripts/adi_env.tcl
+source $ad_hdl_dir/library/scripts/adi_ip.tcl
+
+adi_ip_create util_jesd_align
+adi_ip_files util_jesd_align [list \
+  "$ad_hdl_dir/library/common/ad_jesd_align.v" \
+  "util_jesd_align.v" \
+  "util_jesd_align_constr.xdc" ]
+
+adi_ip_properties_lite util_jesd_align
+adi_ip_constraints util_jesd_align [list \
+  "util_jesd_align_constr.xdc" ]
+
+ipx::save_core [ipx::current_core]
+
+