ad_rst: Update the reset synchronizer module

For a proper reset synchronization, the asynchronous reset signal should
be connected to the reset pins of the two synchronizer flop, and the
data input of the first flop should be connected to VCC.

In the first stage  we're synchronizing just the reset de-assertion, avoiding
the scenario when different parts of the design are reseting at different time,
causing unwanted behaviours.

In the second stage we're synchronizing the reset assertion.

The module expects an ACTIVE_HIGH input reset signal, and provides an ACTIVE_LOW
(rstn) and an ACTIVE_HIGH (rst) synchronized reset output signal.

library/altera/common/up_rst_constr.sdc

@@ -1,2 +1,4 @@
 
-set_false_path  -from [get_registers *up_*preset*]                                    -to [get_registers *ad_rst:i_core_rst_reg|ad_rst_sync_m1*]
+set_false_path  -from [get_registers *up_*rst_async*] -to [get_registers *ad_rst:i_core_rst_reg|rst_sync_d]
+set_false_path  -from [get_registers *up_*rst_async*] -to [get_registers *ad_rst:i_core_rst_reg|rstn]
+

library/common/ad_rst.v

@@ -39,23 +39,38 @@ module ad_rst (
 
   // clock reset
 
-  input                   preset,
+  input                   rst_async,
   input                   clk,
+  output                  rstn,
   output  reg             rst);
 
   // internal registers
+  reg             rst_async_d1 = 'd0;
+  reg             rst_async_d2 = 'd0;
+  reg             rst_sync = 'd0;
+  reg             rst_sync_d = 'd0 /* synthesis preserve */;
 
-  reg             ad_rst_sync_m1 = 'd0 /* synthesis preserve */;
-  reg             ad_rst_sync = 'd0 /* synthesis preserve */;
-
-  // simple reset gen
-
-  always @(posedge clk) begin
-    ad_rst_sync_m1 <= preset;
-    ad_rst_sync <= ad_rst_sync_m1;
-    rst <= ad_rst_sync;
+  // simple reset synchronizer
+  always @(posedge clk or posedge rst_async) begin
+    if (rst_async) begin
+      rst_async_d1 <= 1'b1;
+      rst_async_d2 <= 1'b1;
+      rst_sync <= 1'b1;
+    end else begin
+      rst_async_d1 <= 1'b0;
+      rst_async_d2 <= rst_async_d1;
+      rst_sync <= rst_async_d2;
+    end
   end
 
+  // two-stage synchronizer to prevent metastability on the falling edge
+  always @(posedge clk) begin
+    rst_sync_d <= rst_sync;
+    rst <= rst_sync_d;
+  end
+
+  assign rstn = ~rst;
+
 endmodule
 
 // ***************************************************************************

library/xilinx/common/ad_rst_constr.xdc

@@ -1,7 +1,9 @@
 
-set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
+set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *rst_sync*}]
 
+set_false_path -to [get_cells -hier -filter {name =~ *rst_sync_d_reg && IS_SEQUENTIAL}]
 
-set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *ad_rst_sync*}]
+set_false_path -to [get_pins *rst_sync_reg/PRE]
+set_false_path -to [get_pins *rst_async_d1_reg/PRE]
+set_false_path -to [get_pins *rst_async_d2_reg/PRE]
 
-set_false_path -to [get_cells -hier -filter {name =~ *ad_rst_sync_m1_reg     && IS_SEQUENTIAL}]