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cn0577/zed: Update xdc to diff_term true. Disable csn in system_top 

* Update xdc to use diff_term true instead of diff_term 1
 * Generated xdc using adi_fmc_constr_generator.tcl
 * Make CSN to be inactive
 * Cosmetic changes also

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
main
Iulia Moldovan 2022-06-17 14:07:17 +01:00 committed by imoldovan
parent 6b94259a52
commit 474b8d5bed
4 changed files with 68 additions and 58 deletions
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17
projects/cn0577/common/cn0577_bd.tcl
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@ -52,23 +52,22 @@ ad_connect ref_clk axi_ltc2387/ref_clk
ad_connect clk_gate axi_ltc2387/clk_gate ad_connect clk_gate axi_ltc2387/clk_gate
ad_connect dco_p axi_ltc2387/dco_p ad_connect dco_p axi_ltc2387/dco_p
ad_connect dco_n axi_ltc2387/dco_n ad_connect dco_n axi_ltc2387/dco_n
ad_connect da_n axi_ltc2387/da_n
ad_connect da_p axi_ltc2387/da_p ad_connect da_p axi_ltc2387/da_p
ad_connect db_n axi_ltc2387/db_n ad_connect da_n axi_ltc2387/da_n
ad_connect db_p axi_ltc2387/db_p ad_connect db_p axi_ltc2387/db_p
ad_connect db_n axi_ltc2387/db_n
ad_connect cnv axi_pwm_gen/pwm_0
ad_connect clk_gate axi_pwm_gen/pwm_1
ad_connect ref_clk axi_pwm_gen/ext_clk
ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn
ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk
ad_connect ref_clk axi_ltc2387_dma/fifo_wr_clk ad_connect ref_clk axi_ltc2387_dma/fifo_wr_clk
ad_connect axi_ltc2387/adc_valid axi_ltc2387_dma/fifo_wr_en ad_connect axi_ltc2387/adc_valid axi_ltc2387_dma/fifo_wr_en
ad_connect axi_ltc2387/adc_data axi_ltc2387_dma/fifo_wr_din ad_connect axi_ltc2387/adc_data axi_ltc2387_dma/fifo_wr_din
ad_connect axi_ltc2387/adc_dovf axi_ltc2387_dma/fifo_wr_overflow ad_connect axi_ltc2387/adc_dovf axi_ltc2387_dma/fifo_wr_overflow
ad_connect cnv axi_pwm_gen/pwm_0
ad_connect clk_gate axi_pwm_gen/pwm_1
ad_connect ref_clk axi_pwm_gen/ext_clk
ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn
ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk
# address mapping # address mapping
ad_cpu_interconnect 0x44A00000 axi_ltc2387 ad_cpu_interconnect 0x44A00000 axi_ltc2387

2
projects/cn0577/zed/system_bd.tcl
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@ -1,4 +1,4 @@
# specify number of channels -- the design supports one lane/two lanes # specify number of channels - the design supports one lane/two lanes
set two_lanes 1 set two_lanes 1
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl

44
projects/cn0577/zed/system_constr.xdc
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@ -1,24 +1,32 @@
# cn0577 # cn0577
# pin connections # clocks
set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_p]; #G02 FMC_LPC_CLK1_M2C_P set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## G2 FMC_CLK1_M2C_P IO_L12P_T1_MRCC_35
set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports ref_clk_n]; #G03 FMC_LPC_CLK1_M2C_N set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## G3 FMC_CLK1_M2C_N IO_L12N_T1_MRCC_35
set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_p]; #H04 FMC_LPC_CLK0_M2C_P set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p] ; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34
set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports dco_n]; #H05 FMC_LPC_CLK0_M2C_N set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n] ; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34
set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports da_p]; #H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports da_n]; #H08 FMC_LPC_LA02_N # cnv
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports db_p]; #H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM 1} [get_ports db_n]; #H11 FMC_LPC_LA04_N set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34
set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p]; #G06 FMC_LPC_LA00_CC_P set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n] ; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34
set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n]; #G07 FMC_LPC_LA00_CC_N set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports cnv_en] ; ## G10 FMC_LA03_N IO_L16N_T2_34
set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p]; #D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n]; #D09 FMC_LPC_LA01_CC_N # dco, da, db
set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports cnv_en]; #G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports pd_cntrl]; #G18 FMC_LPC_LA16_P set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dco_p] ; ## H4 FMC_CLK0_M2C_P IO_L12P_T1_MRCC_34
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports testpat_cntrl]; #G21 FMC_LPC_LA20_P set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dco_n] ; ## H5 FMC_CLK0_M2C_N IO_L12N_T1_MRCC_34
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports twolanes_cntrl]; #G24 FMC_LPC_LA22_P set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports da_p] ; ## H7 FMC_LA02_P IO_L20P_T3_34
set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports da_n] ; ## H8 FMC_LA02_N IO_L20N_T3_34
set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db_p] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34
set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db_n] ; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34
# control signals
set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports pd_cntrl] ; ## G18 FMC_LA16_P IO_L9P_T1_DQS_34
set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports testpat_cntrl] ; ## G21 FMC_LA20_P IO_L22P_T3_AD7P_35
set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports twolanes_cntrl] ; ## G24 FMC_LA22_P IO_L20P_T3_AD6P_35
# 120MHz clock # 120MHz clock
set clk_period 8.333 set clk_period 8.333

7
projects/cn0577/zed/system_top.v
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@ -122,6 +122,9 @@ module system_top (
wire ltc_clk; wire ltc_clk;
assign gpio_i[63:34] = gpio_o[63:34]; assign gpio_i[63:34] = gpio_o[63:34];
// hardcode GPIO to always use two lanes configuration
assign twolanes_cntrl = 1'b1; assign twolanes_cntrl = 1'b1;
assign cnv_en = cnv; assign cnv_en = cnv;
@ -260,7 +263,7 @@ module system_top (
.spi0_csn_0_o (), .spi0_csn_0_o (),
.spi0_csn_1_o (), .spi0_csn_1_o (),
.spi0_csn_2_o (), .spi0_csn_2_o (),
.spi0_csn_i (1'b0), .spi0_csn_i (1'b1),
.spi0_sdi_i (1'b0), .spi0_sdi_i (1'b0),
.spi0_sdo_i (1'b0), .spi0_sdo_i (1'b0),
.spi0_sdo_o (), .spi0_sdo_o (),
@ -269,7 +272,7 @@ module system_top (
.spi1_csn_0_o (), .spi1_csn_0_o (),
.spi1_csn_1_o (), .spi1_csn_1_o (),
.spi1_csn_2_o (), .spi1_csn_2_o (),
.spi1_csn_i (1'b0), .spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0), .spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0), .spi1_sdo_i (1'b0),
.spi1_sdo_o ()); .spi1_sdo_o ());