diff --git a/library/axi_gpreg/axi_gpreg.v b/library/axi_gpreg/axi_gpreg.v
index 9626f9b6a..8b5d5852e 100644
--- a/library/axi_gpreg/axi_gpreg.v
+++ b/library/axi_gpreg/axi_gpreg.v
@@ -41,7 +41,15 @@ module axi_gpreg #(
 
   parameter   integer ID = 0,
   parameter   integer NUM_OF_IO = 8,
-  parameter   integer NUM_OF_CLK_MONS = 8)
+  parameter   integer NUM_OF_CLK_MONS = 8,
+  parameter   integer BUF_ENABLE_0 = 1,
+  parameter   integer BUF_ENABLE_1 = 1,
+  parameter   integer BUF_ENABLE_2 = 1,
+  parameter   integer BUF_ENABLE_3 = 1,
+  parameter   integer BUF_ENABLE_4 = 1,
+  parameter   integer BUF_ENABLE_5 = 1,
+  parameter   integer BUF_ENABLE_6 = 1,
+  parameter   integer BUF_ENABLE_7 = 1)
 
  (
 
@@ -107,7 +115,9 @@ module axi_gpreg #(
 
   // version
 
-  localparam  PCORE_VERSION = 32'h00040063;
+  localparam  [31:0]  PCORE_VERSION = 32'h00040063;
+  localparam  integer BUF_ENABLE[7:0] = {BUF_ENABLE_7, BUF_ENABLE_6, BUF_ENABLE_5, BUF_ENABLE_4,
+    BUF_ENABLE_3, BUF_ENABLE_2, BUF_ENABLE_1, BUF_ENABLE_0};
 
   // internal registers
 
@@ -288,7 +298,10 @@ module axi_gpreg #(
   end
 
   for (n = 0; n < NUM_OF_CLK_MONS; n = n + 1) begin: g_clock_mon
-  axi_gpreg_clock_mon #(.ID (32+n)) i_gpreg_clock_mon (
+  axi_gpreg_clock_mon #(
+    .ID (32+n),
+    .BUF_ENABLE (BUF_ENABLE[n]))
+  i_gpreg_clock_mon (
     .d_clk (d_clk_s[n]),
     .up_rstn (up_rstn),
     .up_clk (up_clk),
diff --git a/library/axi_gpreg/axi_gpreg_clock_mon.v b/library/axi_gpreg/axi_gpreg_clock_mon.v
index ec28eac9e..5549e704d 100644
--- a/library/axi_gpreg/axi_gpreg_clock_mon.v
+++ b/library/axi_gpreg/axi_gpreg_clock_mon.v
@@ -59,6 +59,7 @@ module axi_gpreg_clock_mon (
   // parameters
 
   parameter   ID = 0;
+  parameter   BUF_ENABLE = 0;
 
   // clock
 
@@ -91,6 +92,7 @@ module axi_gpreg_clock_mon (
   wire            up_rreq_s;
   wire    [31:0]  up_d_count_s;
   wire            d_rst;
+  wire            d_clk_g;
 
   // decode block select
 
@@ -140,13 +142,23 @@ module axi_gpreg_clock_mon (
     .up_clk (up_clk),
     .up_d_count (up_d_count_s),
     .d_rst (d_rst),
-    .d_clk (d_clk));
+    .d_clk (d_clk_g));
 
   ad_rst i_d_rst_reg (
     .preset (up_d_preset),
-    .clk (d_clk),
+    .clk (d_clk_g),
     .rst (d_rst));
 
+  generate
+  if (BUF_ENABLE == 1) begin
+  BUFG i_bufg (
+    .I (d_clk),
+    .O (d_clk_g));
+  end else begin
+  assign d_clk_g = d_clk;
+  end
+  endgenerate
+
 endmodule
 
 // ***************************************************************************