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cn0540/coraz7s: Time the SPI interface of AD7768-1

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Istvan Csomortani 2020-09-14 12:22:48 +01:00 committed by István Csomortáni
parent 0933949ad7
commit 4838ac0ac2
1 changed files with 14 additions and 3 deletions
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17
projects/cn0540/coraz7s/system_constr.xdc
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@ -16,7 +16,7 @@ set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33}
set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports cn0540_blue_led] ; ## CK_IO1 set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS33} [get_ports cn0540_blue_led] ; ## CK_IO1
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports cn0540_yellow_led] ; ## CK_IO0 set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} [get_ports cn0540_yellow_led] ; ## CK_IO0
# syncronization and timing # synchronization and timing
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports cn0540_sync_in] ; ## CK_IO6 set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports cn0540_sync_in] ; ## CK_IO6
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy] ; ## CK_IO2 set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy] ; ## CK_IO2
@ -25,5 +25,16 @@ set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33}
set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports cn0540_sda] ; ## CK_SDA set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports cn0540_sda] ; ## CK_SDA
# relax the timing between the SDO FIFO and shift-register # relax the timing between the SDO FIFO and shift-register
set_multicycle_path 2 -setup -from [get_pins -hierarchical -filter {NAME=~*/i_sdo_fifo/i_mem/m_ram_reg/CLKARDCLK}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}] set_multicycle_path 2 -setup -from [get_cells -hierarchical -filter {NAME=~*/i_sdo_fifo/i_mem/m_ram_reg}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}]
set_multicycle_path 1 -hold -from [get_pins -hierarchical -filter {NAME=~*/i_sdo_fifo/i_mem/m_ram_reg/CLKARDCLK}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}] set_multicycle_path 1 -hold -from [get_cells -hierarchical -filter {NAME=~*/i_sdo_fifo/i_mem/m_ram_reg}] -to [get_pins -hierarchical -filter {NAME=~*/data_sdo_shift_reg[*]/D}]
# rename auto-generated clock for SPI Engine to spi_clk - 40MHz
create_generated_clock -name spi_clk [get_pins -hier -filter {name=~*PS7_i/FCLKCLK1}]
# create a generated clock for SCLK - fSCLK=spi_clk/2 - 20MHz
create_generated_clock -name SCLK_clk -source [get_pins -hier -filter name=~*sclk_reg/C] -edges {1 3 5} [get_ports cn0540_spi_sclk]
# input delays for MISO lines (SDO for the device)
set_input_delay -clock [get_clocks SCLK_clk] -max 0.6 [get_ports cn0540_spi_miso] -clock_fall
set_input_delay -clock [get_clocks SCLK_clk] -min 0.1 [get_ports cn0540_spi_miso] -clock_fall