axi_adc/dacfifo: Split the intergration script file
Split the integration script file into two separate script files. Rename the integration processes names to be more meaningful.main
Istvan Csomortani
parent
ddfaff2cf5
commit
4863a04132
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@ -0,0 +1,81 @@
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# pl ddr3 (use only when dma is not capable of keeping up).
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# generic fifo interface - existence is oblivious to software.
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proc p_plddr3_adcfifo {p_name m_name adc_data_width} {
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global ad_hdl_dir
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set p_instance [get_bd_cells $p_name]
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set c_instance [current_bd_instance .]
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current_bd_instance $p_instance
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set m_instance [create_bd_cell -type hier $m_name]
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current_bd_instance $m_instance
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create_bd_pin -dir I -type rst sys_rst
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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create_bd_pin -dir I adc_rst
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create_bd_pin -dir I -type clk adc_clk
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create_bd_pin -dir I adc_wr
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create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
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create_bd_pin -dir O adc_wovf
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create_bd_pin -dir I -type clk dma_clk
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create_bd_pin -dir O dma_wr
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create_bd_pin -dir O -from 63 -to 0 dma_wdata
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create_bd_pin -dir I dma_wready
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create_bd_pin -dir I dma_xfer_req
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create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
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set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
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set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
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file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
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set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
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set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
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set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
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set axi_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_adcfifo:1.0 axi_adcfifo]
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set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_adcfifo
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set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_adcfifo
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set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo
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ad_connect sys_rst axi_ddr_cntrl/sys_rst
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ad_connect sys_clk axi_ddr_cntrl/SYS_CLK
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ad_connect ddr3 axi_ddr_cntrl/DDR3
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ad_connect axi_ddr_cntrl/S_AXI axi_adcfifo/axi
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ad_connect adc_rst axi_adcfifo/adc_rst
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ad_connect adc_rst axi_rstgen/ext_reset_in
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ad_connect adc_clk axi_adcfifo/adc_clk
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ad_connect adc_wr axi_adcfifo/adc_wr
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ad_connect adc_wdata axi_adcfifo/adc_wdata
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ad_connect adc_wovf axi_adcfifo/adc_wovf
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ad_connect dma_clk axi_adcfifo/dma_clk
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ad_connect dma_wr axi_adcfifo/dma_wr
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ad_connect dma_wdata axi_adcfifo/dma_wdata
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ad_connect dma_wready axi_adcfifo/dma_wready
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ad_connect dma_xfer_req axi_adcfifo/dma_xfer_req
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ad_connect dma_xfer_status axi_adcfifo/dma_xfer_status
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ad_connect axi_clk axi_ddr_cntrl/ui_clk
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ad_connect axi_clk axi_adcfifo/axi_clk
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ad_connect axi_clk axi_rstgen/slowest_sync_clk
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ad_connect axi_resetn axi_rstgen/peripheral_aresetn
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ad_connect axi_resetn axi_adcfifo/axi_resetn
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ad_connect axi_resetn axi_ddr_cntrl/aresetn
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ad_connect axi_ddr_cntrl/device_temp_i GND
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current_bd_instance $c_instance
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}
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@ -2,84 +2,6 @@
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# pl ddr3 (use only when dma is not capable of keeping up).
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# generic fifo interface - existence is oblivious to software.
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proc p_plddr3_fifo {p_name m_name adc_data_width} {
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global ad_hdl_dir
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set p_instance [get_bd_cells $p_name]
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set c_instance [current_bd_instance .]
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current_bd_instance $p_instance
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set m_instance [create_bd_cell -type hier $m_name]
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current_bd_instance $m_instance
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create_bd_pin -dir I -type rst sys_rst
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create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
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create_bd_pin -dir I adc_rst
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create_bd_pin -dir I -type clk adc_clk
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create_bd_pin -dir I adc_wr
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create_bd_pin -dir I -from [expr ($adc_data_width-1)] -to 0 adc_wdata
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create_bd_pin -dir O adc_wovf
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create_bd_pin -dir I -type clk dma_clk
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create_bd_pin -dir O dma_wr
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create_bd_pin -dir O -from 63 -to 0 dma_wdata
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create_bd_pin -dir I dma_wready
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create_bd_pin -dir I dma_xfer_req
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create_bd_pin -dir O -from 3 -to 0 dma_xfer_status
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set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
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set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
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file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
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set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
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set axi_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 axi_rstgen]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_rstgen
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set_property -dict [list CONFIG.RESET_BOARD_INTERFACE {reset}] $axi_rstgen
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set axi_adcfifo [create_bd_cell -type ip -vlnv analog.com:user:axi_adcfifo:1.0 axi_adcfifo]
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set_property -dict [list CONFIG.ADC_DATA_WIDTH $adc_data_width] $axi_adcfifo
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set_property -dict [list CONFIG.DMA_DATA_WIDTH {64}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_DATA_WIDTH {512}] $axi_adcfifo
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set_property -dict [list CONFIG.DMA_READY_ENABLE {1}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_adcfifo
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set_property -dict [list CONFIG.AXI_BYTE_WIDTH {64}] $axi_adcfifo
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ad_connect sys_rst axi_ddr_cntrl/sys_rst
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ad_connect sys_clk axi_ddr_cntrl/SYS_CLK
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ad_connect ddr3 axi_ddr_cntrl/DDR3
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ad_connect axi_ddr_cntrl/S_AXI axi_adcfifo/axi
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ad_connect adc_rst axi_adcfifo/adc_rst
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ad_connect adc_rst axi_rstgen/ext_reset_in
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ad_connect adc_clk axi_adcfifo/adc_clk
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ad_connect adc_wr axi_adcfifo/adc_wr
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ad_connect adc_wdata axi_adcfifo/adc_wdata
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ad_connect adc_wovf axi_adcfifo/adc_wovf
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ad_connect dma_clk axi_adcfifo/dma_clk
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ad_connect dma_wr axi_adcfifo/dma_wr
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ad_connect dma_wdata axi_adcfifo/dma_wdata
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ad_connect dma_wready axi_adcfifo/dma_wready
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ad_connect dma_xfer_req axi_adcfifo/dma_xfer_req
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ad_connect dma_xfer_status axi_adcfifo/dma_xfer_status
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ad_connect axi_clk axi_ddr_cntrl/ui_clk
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ad_connect axi_clk axi_adcfifo/axi_clk
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ad_connect axi_clk axi_rstgen/slowest_sync_clk
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ad_connect axi_resetn axi_rstgen/peripheral_aresetn
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ad_connect axi_resetn axi_adcfifo/axi_resetn
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ad_connect axi_resetn axi_ddr_cntrl/aresetn
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ad_connect axi_ddr_cntrl/device_temp_i GND
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current_bd_instance $c_instance
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}
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proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
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global ad_hdl_dir
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@ -111,7 +33,7 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
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create_bd_pin -dir I dma_xfer_req
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create_bd_pin -dir I dma_xfer_last
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set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.3 axi_ddr_cntrl]
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set axi_ddr_cntrl [create_bd_cell -type ip -vlnv xilinx.com:ip:mig_7series:2.4 axi_ddr_cntrl]
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set axi_ddr_cntrl_dir [get_property IP_DIR [get_ips [get_property CONFIG.Component_Name $axi_ddr_cntrl]]]
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file copy -force $ad_hdl_dir/projects/common/zc706/zc706_system_mig.prj "$axi_ddr_cntrl_dir/"
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set_property -dict [list CONFIG.XML_INPUT_FILE {zc706_system_mig.prj}] $axi_ddr_cntrl
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@ -168,4 +90,3 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
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current_bd_instance $c_instance
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}
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@ -1,10 +1,10 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 128 10
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p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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@ -1,9 +1,9 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
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p_sys_dacfifo [current_bd_instance .] axi_ad9152_fifo 128 10
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create_bd_port -dir I -type rst sys_rst
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@ -1,8 +1,8 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
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p_plddr3_fifo [current_bd_instance .] axi_ad9625_fifo 256
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p_plddr3_adcfifo [current_bd_instance .] axi_ad9625_fifo 256
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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@ -1,8 +1,8 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 256
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p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 256
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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@ -1,9 +1,9 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
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source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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p_plddr3_adcfifo [current_bd_instance .] axi_ad9680_fifo 128
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p_sys_dacfifo [current_bd_instance .] axi_ad9144_fifo 256 10
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create_bd_port -dir I -type rst sys_rst
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@ -1,8 +1,9 @@
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source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3.tcl
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source $ad_hdl_dir/projects/common/zc706/zc706_system_plddr3_adcfifo.tcl
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p_plddr3_fifo [current_bd_instance .] usdrx1_fifo 512
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p_plddr3_adcfifo [current_bd_instance .] usdrx1_fifo 512
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create_bd_port -dir I -type rst sys_rst
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 ddr3
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