util_adxcvr- ultrascale+ initial commit
Rejeesh Kutty
parent
0e8551545c
commit
48dd4880a3
|
|
@ -322,6 +322,182 @@ module util_adxcvr_xcm #(
|
|||
end
|
||||
endgenerate
|
||||
|
||||
generate
|
||||
if (XCVR_TYPE == 2) begin
|
||||
GTHE4_COMMON #(
|
||||
.AEN_QPLL0_FBDIV (1'b1),
|
||||
.AEN_QPLL1_FBDIV (1'b1),
|
||||
.AEN_SDM0TOGGLE (1'b0),
|
||||
.AEN_SDM1TOGGLE (1'b0),
|
||||
.A_SDM0TOGGLE (1'b0),
|
||||
.A_SDM1DATA_HIGH (9'b000000000),
|
||||
.A_SDM1DATA_LOW (16'b0000000000000000),
|
||||
.A_SDM1TOGGLE (1'b0),
|
||||
.BIAS_CFG0 (16'h0000),
|
||||
.BIAS_CFG1 (16'h0000),
|
||||
.BIAS_CFG2 (16'h0124),
|
||||
.BIAS_CFG3 (16'h0041),
|
||||
.BIAS_CFG4 (16'h0010),
|
||||
.BIAS_CFG_RSVD (16'h0000),
|
||||
.COMMON_CFG0 (16'h0000),
|
||||
.COMMON_CFG1 (16'h0000),
|
||||
.POR_CFG (16'h0006),
|
||||
.PPF0_CFG (16'h0600),
|
||||
.PPF1_CFG (16'h0600),
|
||||
.QPLL0CLKOUT_RATE ("HALF"),
|
||||
.QPLL0_CFG0 (16'h331c),
|
||||
.QPLL0_CFG1 (16'hd038),
|
||||
.QPLL0_CFG1_G3 (16'hd038),
|
||||
.QPLL0_CFG2 (16'h0fc0),
|
||||
.QPLL0_CFG2_G3 (16'h0fc0),
|
||||
.QPLL0_CFG3 (16'h0120),
|
||||
.QPLL0_CFG4 (16'h0003),
|
||||
.QPLL0_CP (10'b0001111111),
|
||||
.QPLL0_CP_G3 (10'b0000011111),
|
||||
.QPLL0_FBDIV (QPLL_FBDIV),
|
||||
.QPLL0_FBDIV_G3 (160),
|
||||
.QPLL0_INIT_CFG0 (16'h02b2),
|
||||
.QPLL0_INIT_CFG1 (8'h00),
|
||||
.QPLL0_LOCK_CFG (16'h25e8),
|
||||
.QPLL0_LOCK_CFG_G3 (16'h25e8),
|
||||
.QPLL0_LPF (10'b0100110111),
|
||||
.QPLL0_LPF_G3 (10'b0111010101),
|
||||
.QPLL0_PCI_EN (1'b0),
|
||||
.QPLL0_RATE_SW_USE_DRP (1'b1),
|
||||
.QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL0_SDM_CFG0 (16'h0080),
|
||||
.QPLL0_SDM_CFG1 (16'h0000),
|
||||
.QPLL0_SDM_CFG2 (16'h0000),
|
||||
.QPLL1CLKOUT_RATE ("HALF"),
|
||||
.QPLL1_CFG0 (16'h331c),
|
||||
.QPLL1_CFG1 (16'hd038),
|
||||
.QPLL1_CFG1_G3 (16'hd038),
|
||||
.QPLL1_CFG2 (16'h0fc0),
|
||||
.QPLL1_CFG2_G3 (16'h0fc0),
|
||||
.QPLL1_CFG3 (16'h0120),
|
||||
.QPLL1_CFG4 (16'h0003),
|
||||
.QPLL1_CP (10'b1111111111),
|
||||
.QPLL1_CP_G3 (10'b0011111111),
|
||||
.QPLL1_FBDIV (QPLL_FBDIV),
|
||||
.QPLL1_FBDIV_G3 (80),
|
||||
.QPLL1_INIT_CFG0 (16'h02b2),
|
||||
.QPLL1_INIT_CFG1 (8'h00),
|
||||
.QPLL1_LOCK_CFG (16'h25e8),
|
||||
.QPLL1_LOCK_CFG_G3 (16'h25e8),
|
||||
.QPLL1_LPF (10'b0100110101),
|
||||
.QPLL1_LPF_G3 (10'b0111010100),
|
||||
.QPLL1_PCI_EN (1'b0),
|
||||
.QPLL1_RATE_SW_USE_DRP (1'b1),
|
||||
.QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV),
|
||||
.QPLL1_SDM_CFG0 (16'h0080),
|
||||
.QPLL1_SDM_CFG1 (16'h0000),
|
||||
.QPLL1_SDM_CFG2 (16'h0000),
|
||||
.RSVD_ATTR0 (16'h0000),
|
||||
.RSVD_ATTR1 (16'h0000),
|
||||
.RSVD_ATTR2 (16'h0000),
|
||||
.RSVD_ATTR3 (16'h0000),
|
||||
.RXRECCLKOUT0_SEL (2'b00),
|
||||
.RXRECCLKOUT1_SEL (2'b00),
|
||||
.SARC_ENB (1'b0),
|
||||
.SARC_SEL (1'b0),
|
||||
.SDM0INITSEED0_0 (16'b0000000100010001),
|
||||
.SDM0INITSEED0_1 (9'b000010001),
|
||||
.SDM1INITSEED0_0 (16'b0000000100010001),
|
||||
.SDM1INITSEED0_1 (9'b000010001),
|
||||
.SIM_MODE ("FAST"),
|
||||
.SIM_RESET_SPEEDUP ("TRUE"),
|
||||
.SIM_VERSION (1))
|
||||
i_gthe4_common (
|
||||
.BGBYPASSB (1'd1),
|
||||
.BGMONITORENB (1'd1),
|
||||
.BGPDB (1'd1),
|
||||
.BGRCALOVRD (5'b11111),
|
||||
.BGRCALOVRDENB (1'd1),
|
||||
.DRPADDR ({4'd0, up_addr_int}),
|
||||
.DRPCLK (up_clk),
|
||||
.DRPDI (up_wdata_int),
|
||||
.DRPDO (up_rdata_s),
|
||||
.DRPEN (up_enb_int),
|
||||
.DRPRDY (up_ready_s),
|
||||
.DRPWE (up_wr_int),
|
||||
.GTGREFCLK0 (1'd0),
|
||||
.GTGREFCLK1 (1'd0),
|
||||
.GTNORTHREFCLK00 (1'd0),
|
||||
.GTNORTHREFCLK01 (1'd0),
|
||||
.GTNORTHREFCLK10 (1'd0),
|
||||
.GTNORTHREFCLK11 (1'd0),
|
||||
.GTREFCLK00 (qpll_ref_clk),
|
||||
.GTREFCLK01 (1'd0),
|
||||
.GTREFCLK10 (1'd0),
|
||||
.GTREFCLK11 (1'd0),
|
||||
.GTSOUTHREFCLK00 (1'd0),
|
||||
.GTSOUTHREFCLK01 (1'd0),
|
||||
.GTSOUTHREFCLK10 (1'd0),
|
||||
.GTSOUTHREFCLK11 (1'd0),
|
||||
.PCIERATEQPLL0 (3'd0),
|
||||
.PCIERATEQPLL1 (3'd0),
|
||||
.PMARSVD0 (8'd0),
|
||||
.PMARSVD1 (8'd0),
|
||||
.PMARSVDOUT0 (),
|
||||
.PMARSVDOUT1 (),
|
||||
.QPLL0CLKRSVD0 (1'd0),
|
||||
.QPLL0CLKRSVD1 (1'd0),
|
||||
.QPLL0FBCLKLOST (),
|
||||
.QPLL0FBDIV (8'd0),
|
||||
.QPLL0LOCK (qpll2ch_locked),
|
||||
.QPLL0LOCKDETCLK (up_clk),
|
||||
.QPLL0LOCKEN (1'd1),
|
||||
.QPLL0OUTCLK (qpll2ch_clk),
|
||||
.QPLL0OUTREFCLK (qpll2ch_ref_clk),
|
||||
.QPLL0PD (1'd0),
|
||||
.QPLL0REFCLKLOST (),
|
||||
.QPLL0REFCLKSEL (3'b001),
|
||||
.QPLL0RESET (up_qpll_rst),
|
||||
.QPLL1CLKRSVD0 (1'd0),
|
||||
.QPLL1CLKRSVD1 (1'd0),
|
||||
.QPLL1FBCLKLOST (),
|
||||
.QPLL1FBDIV (8'd0),
|
||||
.QPLL1LOCK (),
|
||||
.QPLL1LOCKDETCLK (1'd0),
|
||||
.QPLL1LOCKEN (1'd0),
|
||||
.QPLL1OUTCLK (),
|
||||
.QPLL1OUTREFCLK (),
|
||||
.QPLL1PD (1'd1),
|
||||
.QPLL1REFCLKLOST (),
|
||||
.QPLL1REFCLKSEL (3'b001),
|
||||
.QPLL1RESET (1'd1),
|
||||
.QPLLDMONITOR0 (),
|
||||
.QPLLDMONITOR1 (),
|
||||
.QPLLRSVD1 (8'd0),
|
||||
.QPLLRSVD2 (5'd0),
|
||||
.QPLLRSVD3 (5'd0),
|
||||
.QPLLRSVD4 (8'd0),
|
||||
.RCALENB (1'd1),
|
||||
.REFCLKOUTMONITOR0 (),
|
||||
.REFCLKOUTMONITOR1 (),
|
||||
.RXRECCLK0SEL (),
|
||||
.RXRECCLK1SEL (),
|
||||
.SDM0DATA (25'd0),
|
||||
.SDM0FINALOUT (),
|
||||
.SDM0RESET (1'd0),
|
||||
.SDM0TESTDATA (),
|
||||
.SDM0TOGGLE (1'd0),
|
||||
.SDM0WIDTH (2'd0),
|
||||
.SDM1DATA (25'd0),
|
||||
.SDM1FINALOUT (),
|
||||
.SDM1RESET (1'd0),
|
||||
.SDM1TESTDATA (),
|
||||
.SDM1TOGGLE (1'd0),
|
||||
.SDM1WIDTH (2'd0),
|
||||
.TCONGPI (10'd0),
|
||||
.TCONGPO (),
|
||||
.TCONPOWERUP (1'd0),
|
||||
.TCONRESET (2'd0),
|
||||
.TCONRSVDIN1 (2'd0),
|
||||
.TCONRSVDOUT0 ());
|
||||
end
|
||||
endgenerate
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
|
|
|
|||
Loading…
Reference in New Issue