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projects- jesd-align port name change

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Rejeesh Kutty 2015-05-20 14:24:26 -04:00
parent da0409b5a6
commit 4927ca85c2
3 changed files with 31 additions and 31 deletions
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14
projects/usdrx1/a5gt/system_top.v
View File

@ -282,7 +282,7 @@ module system_top (
wire [ 7:0] rx_cal_busy_s; wire [ 7:0] rx_cal_busy_s;
wire rx_pll_locked_s; wire rx_pll_locked_s;
wire [ 22:0] rx_xcvr_status_s; wire [ 22:0] rx_xcvr_status_s;
wire [ 7:0] rx_data_sof; wire [ 7:0] rx_sof;
wire [ 3:0] sync_raddr; wire [ 3:0] sync_raddr;
wire sync_signal; wire sync_signal;
@ -357,9 +357,9 @@ module system_top (
for (n = 0; n < 8; n = n + 1) begin: g_align_1 for (n = 0; n < 8; n = n + 1) begin: g_align_1
ad_jesd_align i_jesd_align ( ad_jesd_align i_jesd_align (
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_sof (rx_ip_sof_s), .rx_ip_sof (rx_ip_sof_s),
.rx_ip_data (rx_ip_data_s[n*32+31:n*32]), .rx_ip_data (rx_ip_data_s[n*32+31:n*32]),
.rx_data_sof(rx_data_sof[n]), .rx_sof (rx_sof[n]),
.rx_data (rx_data_s[n*32+31:n*32])); .rx_data (rx_data_s[n*32+31:n*32]));
end end
endgenerate endgenerate
@ -398,10 +398,10 @@ module system_top (
always @(posedge rx_clk) always @(posedge rx_clk)
begin begin
rx_sof_0_s <= rx_data_sof[0] | rx_data_sof[1]; rx_sof_0_s <= rx_sof[0] | rx_sof[1];
rx_sof_1_s <= rx_data_sof[2] | rx_data_sof[3]; rx_sof_1_s <= rx_sof[2] | rx_sof[3];
rx_sof_2_s <= rx_data_sof[4] | rx_data_sof[5]; rx_sof_2_s <= rx_sof[4] | rx_sof[5];
rx_sof_3_s <= rx_data_sof[6] | rx_data_sof[7]; rx_sof_3_s <= rx_sof[6] | rx_sof[7];
end end
usdrx1_spi i_spi ( usdrx1_spi i_spi (

20
projects/usdrx1/common/usdrx1_bd.tcl
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@ -16,15 +16,15 @@ create_bd_port -dir I -from 7 -to 0 rx_data_p
create_bd_port -dir I -from 7 -to 0 rx_data_n create_bd_port -dir I -from 7 -to 0 rx_data_n
create_bd_port -dir O -from 255 -to 0 gt_rx_data create_bd_port -dir O -from 255 -to 0 gt_rx_data
create_bd_port -dir O -from 3 -to 0 gt_rx_data_sof create_bd_port -dir O -from 3 -to 0 gt_rx_sof
create_bd_port -dir I -from 63 -to 0 gt_rx_data_0 create_bd_port -dir I -from 63 -to 0 gt_rx_data_0
create_bd_port -dir I gt_rx_data_sof_0 create_bd_port -dir I gt_rx_sof_0
create_bd_port -dir I -from 63 -to 0 gt_rx_data_1 create_bd_port -dir I -from 63 -to 0 gt_rx_data_1
create_bd_port -dir I gt_rx_data_sof_1 create_bd_port -dir I gt_rx_sof_1
create_bd_port -dir I -from 63 -to 0 gt_rx_data_2 create_bd_port -dir I -from 63 -to 0 gt_rx_data_2
create_bd_port -dir I gt_rx_data_sof_2 create_bd_port -dir I gt_rx_sof_2
create_bd_port -dir I -from 63 -to 0 gt_rx_data_3 create_bd_port -dir I -from 63 -to 0 gt_rx_data_3
create_bd_port -dir I gt_rx_data_sof_3 create_bd_port -dir I gt_rx_sof_3
create_bd_port -dir O -from 127 -to 0 adc_data_0 create_bd_port -dir O -from 127 -to 0 adc_data_0
create_bd_port -dir O -from 127 -to 0 adc_data_1 create_bd_port -dir O -from 127 -to 0 adc_data_1
create_bd_port -dir O -from 127 -to 0 adc_data_2 create_bd_port -dir O -from 127 -to 0 adc_data_2
@ -190,15 +190,15 @@ ad_connect axi_usdrx1_gt/rx_ip_sync axi_usdrx1_jesd/rx_sync
ad_connect axi_usdrx1_gt/rx_ip_sof axi_usdrx1_jesd/rx_start_of_frame ad_connect axi_usdrx1_gt/rx_ip_sof axi_usdrx1_jesd/rx_start_of_frame
ad_connect axi_usdrx1_gt/rx_ip_data axi_usdrx1_jesd/rx_tdata ad_connect axi_usdrx1_gt/rx_ip_data axi_usdrx1_jesd/rx_tdata
ad_connect gt_rx_data axi_usdrx1_gt/rx_data ad_connect gt_rx_data axi_usdrx1_gt/rx_data
ad_connect gt_rx_data_sof axi_usdrx1_gt/rx_data_sof ad_connect gt_rx_sof axi_usdrx1_gt/rx_sof
ad_connect gt_rx_data_0 axi_ad9671_core_0/rx_data ad_connect gt_rx_data_0 axi_ad9671_core_0/rx_data
ad_connect gt_rx_data_sof_0 axi_ad9671_core_0/rx_data_sof ad_connect gt_rx_sof_0 axi_ad9671_core_0/rx_sof
ad_connect gt_rx_data_1 axi_ad9671_core_1/rx_data ad_connect gt_rx_data_1 axi_ad9671_core_1/rx_data
ad_connect gt_rx_data_sof_1 axi_ad9671_core_1/rx_data_sof ad_connect gt_rx_sof_1 axi_ad9671_core_1/rx_sof
ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data ad_connect gt_rx_data_2 axi_ad9671_core_2/rx_data
ad_connect gt_rx_data_sof_2 axi_ad9671_core_2/rx_data_sof ad_connect gt_rx_sof_2 axi_ad9671_core_2/rx_sof
ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data ad_connect gt_rx_data_3 axi_ad9671_core_3/rx_data
ad_connect gt_rx_data_sof_3 axi_ad9671_core_3/rx_data_sof ad_connect gt_rx_sof_3 axi_ad9671_core_3/rx_sof
ad_connect axi_ad9671_core_0/adc_clk axi_usdrx1_dma/fifo_wr_clk ad_connect axi_ad9671_core_0/adc_clk axi_usdrx1_dma/fifo_wr_clk
ad_connect adc_data_0 axi_ad9671_core_0/adc_data ad_connect adc_data_0 axi_ad9671_core_0/adc_data
ad_connect adc_data_1 axi_ad9671_core_1/adc_data ad_connect adc_data_1 axi_ad9671_core_1/adc_data

28
projects/usdrx1/zc706/system_top.v
View File

@ -226,15 +226,15 @@ module system_top (
wire adc_dovf_2; wire adc_dovf_2;
wire adc_dovf_3; wire adc_dovf_3;
wire [255:0] gt_rx_data; wire [255:0] gt_rx_data;
wire [7:0] gt_rx_data_sof; wire [7:0] gt_rx_sof;
wire [63:0] gt_rx_data_0; wire [63:0] gt_rx_data_0;
wire gt_rx_data_sof_0; wire gt_rx_sof_0;
wire [63:0] gt_rx_data_1; wire [63:0] gt_rx_data_1;
wire gt_rx_data_sof_1; wire gt_rx_sof_1;
wire [63:0] gt_rx_data_2; wire [63:0] gt_rx_data_2;
wire gt_rx_data_sof_2; wire gt_rx_sof_2;
wire [63:0] gt_rx_data_3; wire [63:0] gt_rx_data_3;
wire gt_rx_data_sof_3; wire gt_rx_sof_3;
wire [63:0] gpio_i; wire [63:0] gpio_i;
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
@ -270,10 +270,10 @@ module system_top (
assign gt_rx_data_2 = gt_rx_data[191:128]; assign gt_rx_data_2 = gt_rx_data[191:128];
assign gt_rx_data_1 = gt_rx_data[127: 64]; assign gt_rx_data_1 = gt_rx_data[127: 64];
assign gt_rx_data_0 = gt_rx_data[ 63: 0]; assign gt_rx_data_0 = gt_rx_data[ 63: 0];
assign gt_rx_data_sof_0 = gt_rx_data_sof [0] | gt_rx_data_sof [1]; assign gt_rx_sof_0 = gt_rx_sof [0] | gt_rx_sof [1];
assign gt_rx_data_sof_1 = gt_rx_data_sof [2] | gt_rx_data_sof [3]; assign gt_rx_sof_1 = gt_rx_sof [2] | gt_rx_sof [3];
assign gt_rx_data_sof_2 = gt_rx_data_sof [4] | gt_rx_data_sof [5]; assign gt_rx_sof_2 = gt_rx_sof [4] | gt_rx_sof [5];
assign gt_rx_data_sof_3 = gt_rx_data_sof [6] | gt_rx_data_sof [7]; assign gt_rx_sof_3 = gt_rx_sof [6] | gt_rx_sof [7];
assign adc_data = {adc_data_3, adc_data_2, adc_data_1, adc_data_0}; assign adc_data = {adc_data_3, adc_data_2, adc_data_1, adc_data_0};
assign adc_valid = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ; assign adc_valid = (|adc_valid_0) | (|adc_valid_1) | (|adc_valid_2) | (|adc_valid_3) ;
@ -404,15 +404,15 @@ module system_top (
.adc_dovf_2 (adc_dovf_2), .adc_dovf_2 (adc_dovf_2),
.adc_dovf_3 (adc_dovf_3), .adc_dovf_3 (adc_dovf_3),
.gt_rx_data (gt_rx_data), .gt_rx_data (gt_rx_data),
.gt_rx_data_sof (gt_rx_data_sof), .gt_rx_sof (gt_rx_sof),
.gt_rx_data_0 (gt_rx_data_0), .gt_rx_data_0 (gt_rx_data_0),
.gt_rx_data_sof_0(gt_rx_data_sof_0), .gt_rx_sof_0(gt_rx_sof_0),
.gt_rx_data_1 (gt_rx_data_1), .gt_rx_data_1 (gt_rx_data_1),
.gt_rx_data_sof_1(gt_rx_data_sof_1), .gt_rx_sof_1(gt_rx_sof_1),
.gt_rx_data_2 (gt_rx_data_2), .gt_rx_data_2 (gt_rx_data_2),
.gt_rx_data_sof_2(gt_rx_data_sof_2), .gt_rx_sof_2(gt_rx_sof_2),
.gt_rx_data_3 (gt_rx_data_3), .gt_rx_data_3 (gt_rx_data_3),
.gt_rx_data_sof_3(gt_rx_data_sof_3), .gt_rx_sof_3(gt_rx_sof_3),
.hdmi_data (hdmi_data), .hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e), .hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync), .hdmi_hsync (hdmi_hsync),