adrv9371x - xcvr updates
Rejeesh Kutty
parent
4a5b7fc723
commit
4950c6c773
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@ -1,38 +1,30 @@
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# ad9371
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create_bd_port -dir I rx_ref_clk
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create_bd_port -dir I rx_sysref
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create_bd_port -dir I -from 1 -to 0 rx_p
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create_bd_port -dir I -from 1 -to 0 rx_n
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create_bd_port -dir O rx_sync
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create_bd_port -dir I -from 1 -to 0 rx_os_p
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create_bd_port -dir I -from 1 -to 0 rx_os_n
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create_bd_port -dir O rx_os_sync
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create_bd_port -dir I tx_ref_clk
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create_bd_port -dir I tx_sysref
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create_bd_port -dir O -from 3 -to 0 tx_p
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create_bd_port -dir O -from 3 -to 0 tx_n
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create_bd_port -dir I tx_sync
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create_bd_port -dir I dac_fifo_bypass
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# dma clock
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150}] $sys_ps7
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set sys_dma_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_dma_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_dma_rstgen
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ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
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ad_connect sys_dma_reset sys_dma_rstgen/peripheral_reset
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ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
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ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
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ad_connect sys_dma_rstgen/ext_reset_in sys_ps7/FCLK_RESET2_N
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# dac peripherals
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set axi_ad9371_tx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_tx_clkgen]
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set_property -dict [list CONFIG.ID {2}] $axi_ad9371_tx_clkgen
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set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_tx_clkgen
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set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_tx_clkgen
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set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_tx_clkgen
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set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_tx_clkgen
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set axi_ad9371_tx_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_tx_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9371_tx_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {1}] $axi_ad9371_tx_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {1}] $axi_ad9371_tx_xcvr
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set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_tx_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd
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set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
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set axi_ad9371_tx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_tx_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9371_tx_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {1}] $axi_ad9371_tx_dma
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@ -45,28 +37,31 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_tx_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_tx_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9371_tx_dma
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set util_ad9371_tx_upack [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_ad9371_tx_upack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_tx_upack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_tx_upack
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set axi_ad9371_tx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_tx_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {1}] $axi_ad9371_tx_jesd
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9371_tx_jesd
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# adc peripherals
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set axi_ad9371_rx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_rx_clkgen]
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set_property -dict [list CONFIG.ID {2}] $axi_ad9371_rx_clkgen
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set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_rx_clkgen
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set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_rx_clkgen
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set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_rx_clkgen
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set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_rx_clkgen
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set axi_ad9371_rx_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_rx_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad9371_rx_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9371_rx_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9371_rx_xcvr
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set axi_ad9371_rx_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_jesd
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set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_os_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd
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set util_ad9371_rx_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9371_rx_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_rx_cpack
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set axi_ad9371_rx_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_dma
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set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9371_rx_dma
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set_property -dict [list CONFIG.SYNC_TRANSFER_START {1}] $axi_ad9371_rx_dma
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set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9371_rx_dma
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@ -77,6 +72,28 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_dma
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# adc-os peripherals
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set axi_ad9371_rx_os_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_ad9371_rx_os_clkgen]
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set_property -dict [list CONFIG.ID {2}] $axi_ad9371_rx_os_clkgen
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set_property -dict [list CONFIG.CLKIN_PERIOD {8}] $axi_ad9371_rx_os_clkgen
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set_property -dict [list CONFIG.VCO_DIV {1}] $axi_ad9371_rx_os_clkgen
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set_property -dict [list CONFIG.VCO_MUL {8}] $axi_ad9371_rx_os_clkgen
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set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_ad9371_rx_os_clkgen
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set axi_ad9371_rx_os_xcvr [create_bd_cell -type ip -vlnv analog.com:user:axi_adxcvr:1.0 axi_ad9371_rx_os_xcvr]
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $axi_ad9371_rx_os_xcvr
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set_property -dict [list CONFIG.QPLL_ENABLE {0}] $axi_ad9371_rx_os_xcvr
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set_property -dict [list CONFIG.TX_OR_RX_N {0}] $axi_ad9371_rx_os_xcvr
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set axi_ad9371_rx_os_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:7.0 axi_ad9371_rx_os_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9371_rx_os_jesd
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set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9371_rx_os_jesd
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set util_ad9371_rx_os_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_os_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_rx_os_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9371_rx_os_cpack
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set axi_ad9371_rx_os_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9371_rx_os_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9371_rx_os_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9371_rx_os_dma
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@ -90,155 +107,68 @@ set_property -dict [list CONFIG.ASYNC_CLK_REQ_SRC {1}] $axi_ad9371_rx_os_dma
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set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9371_rx_os_dma
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set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9371_rx_os_dma
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set util_ad9371_rx_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $util_ad9371_rx_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {4}] $util_ad9371_rx_cpack
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set util_ad9371_rx_os_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_ad9371_rx_os_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_ad9371_rx_os_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_ad9371_rx_os_cpack
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# ad9371 gt & core
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# common cores
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set axi_ad9371_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9371:1.0 axi_ad9371_core]
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set axi_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9371_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $axi_ad9371_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $axi_ad9371_gt
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set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_ad9371_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_0 {4}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_0 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_0 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_0 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_0 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_0 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_0 {3}] $axi_ad9371_gt
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set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_ad9371_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_1 {4}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_1 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_1 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_1 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_1 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_1 {0}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_1 {0}] $axi_ad9371_gt
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set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_ad9371_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_2 {4}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_2 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_2 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_2 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_2 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_2 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_2 {0}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_2 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_ad9371_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_3 {4}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_OUT_DIV_3 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_3 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_OUT_DIV_3 {1}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLK25_DIV_3 {5}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_CLKBUF_ENABLE_3 {0}] $axi_ad9371_gt
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set_property -dict [list CONFIG.TX_DATA_SEL_3 {2}] $axi_ad9371_gt
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set util_ad9371_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad9371_xcvr]
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {4}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.CPLL_FBDIV {4}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.RX_CLK25_DIV {5}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.TX_CLK25_DIV {5}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.PMA_RSV {0x00018480}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_ad9371_xcvr
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set_property -dict [list CONFIG.QPLL_FBDIV {"0100100000"}] $util_ad9371_xcvr
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set util_ad9371_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_gt]
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set_property -dict [list CONFIG.QPLL0_ENABLE {1}] $util_ad9371_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {4}] $util_ad9371_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_gt
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set_property -dict [list CONFIG.TX_ENABLE {1}] $util_ad9371_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {4}] $util_ad9371_gt
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# xcvr interfaces
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set util_ad9371_os_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_ad9371_os_gt]
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set_property -dict [list CONFIG.QPLL0_ENABLE {0}] $util_ad9371_os_gt
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set_property -dict [list CONFIG.QPLL1_ENABLE {0}] $util_ad9371_os_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {2}] $util_ad9371_os_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_ad9371_os_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {2}] $util_ad9371_os_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_ad9371_os_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {2}] $util_ad9371_os_gt
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ad_connect sys_cpu_resetn util_ad9371_xcvr/up_rstn
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ad_connect sys_cpu_clk util_ad9371_xcvr/up_clk
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# ad9371 data path clocks
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ad_xcvrcon util_ad9371_xcvr axi_ad9371_tx_xcvr axi_ad9371_tx_jesd
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ad_reconct util_ad9371_xcvr/tx_out_clk_0 axi_ad9371_tx_clkgen/clk
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ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_0
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ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_1
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ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_2
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ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_xcvr/tx_clk_3
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ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
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ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_tx_jesd_rstgen/slowest_sync_clk
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ad_reconct util_ad9371_xcvr/tx_0 axi_ad9371_tx_jesd/gt3_tx
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ad_reconct util_ad9371_xcvr/tx_1 axi_ad9371_tx_jesd/gt0_tx
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ad_reconct util_ad9371_xcvr/tx_2 axi_ad9371_tx_jesd/gt1_tx
|
||||
ad_reconct util_ad9371_xcvr/tx_3 axi_ad9371_tx_jesd/gt2_tx
|
||||
ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_xcvr axi_ad9371_rx_jesd
|
||||
ad_reconct util_ad9371_xcvr/rx_out_clk_0 axi_ad9371_rx_clkgen/clk
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_0
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_xcvr/rx_clk_1
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_jesd_rstgen/slowest_sync_clk
|
||||
ad_xcvrcon util_ad9371_xcvr axi_ad9371_rx_os_xcvr axi_ad9371_rx_os_jesd
|
||||
ad_reconct util_ad9371_xcvr/rx_out_clk_2 axi_ad9371_rx_os_clkgen/clk
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_2
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_xcvr/rx_clk_3
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd_rstgen/slowest_sync_clk
|
||||
|
||||
set axi_tx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_tx_clkgen]
|
||||
set_property -dict [list CONFIG.ID {2}] $axi_tx_clkgen
|
||||
set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_tx_clkgen
|
||||
set_property -dict [list CONFIG.VCO_DIV {1}] $axi_tx_clkgen
|
||||
set_property -dict [list CONFIG.VCO_MUL {8}] $axi_tx_clkgen
|
||||
set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_tx_clkgen
|
||||
# dma clock & reset
|
||||
|
||||
set axi_rx_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_clkgen]
|
||||
set_property -dict [list CONFIG.ID {2}] $axi_rx_clkgen
|
||||
set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_clkgen
|
||||
set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_clkgen
|
||||
set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_clkgen
|
||||
set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_clkgen
|
||||
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {150}] $sys_ps7
|
||||
|
||||
set axi_rx_os_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_rx_os_clkgen]
|
||||
set_property -dict [list CONFIG.ID {2}] $axi_rx_os_clkgen
|
||||
set_property -dict [list CONFIG.CLKIN_PERIOD {8.0}] $axi_rx_os_clkgen
|
||||
set_property -dict [list CONFIG.VCO_DIV {1}] $axi_rx_os_clkgen
|
||||
set_property -dict [list CONFIG.VCO_MUL {8}] $axi_rx_os_clkgen
|
||||
set_property -dict [list CONFIG.CLK0_DIV {8}] $axi_rx_os_clkgen
|
||||
set sys_dma_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_dma_rstgen]
|
||||
set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_dma_rstgen
|
||||
|
||||
# connections (gt)
|
||||
|
||||
ad_connect util_ad9371_gt/qpll_ref_clk rx_ref_clk
|
||||
ad_connect util_ad9371_gt/cpll_ref_clk tx_ref_clk
|
||||
ad_connect util_ad9371_os_gt/qpll_ref_clk rx_ref_clk
|
||||
ad_connect util_ad9371_os_gt/cpll_ref_clk tx_ref_clk
|
||||
|
||||
ad_connect axi_ad9371_gt/gt_qpll_0 util_ad9371_gt/gt_qpll_0
|
||||
ad_connect axi_ad9371_gt/gt_pll_0 util_ad9371_gt/gt_pll_0
|
||||
ad_connect axi_ad9371_gt/gt_pll_1 util_ad9371_gt/gt_pll_1
|
||||
ad_connect axi_ad9371_gt/gt_pll_2 util_ad9371_gt/gt_pll_2
|
||||
ad_connect axi_ad9371_gt/gt_pll_3 util_ad9371_gt/gt_pll_3
|
||||
ad_connect axi_ad9371_gt/gt_rx_0 util_ad9371_gt/gt_rx_0
|
||||
ad_connect axi_ad9371_gt/gt_rx_1 util_ad9371_gt/gt_rx_1
|
||||
ad_connect axi_ad9371_gt/gt_rx_ip_0 axi_ad9371_rx_jesd/gt0_rx
|
||||
ad_connect axi_ad9371_gt/gt_rx_ip_1 axi_ad9371_rx_jesd/gt1_rx
|
||||
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_0 axi_ad9371_rx_jesd/rxencommaalign_out
|
||||
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_1 axi_ad9371_rx_jesd/rxencommaalign_out
|
||||
ad_connect axi_ad9371_gt/gt_rx_2 util_ad9371_os_gt/gt_rx_0
|
||||
ad_connect axi_ad9371_gt/gt_rx_3 util_ad9371_os_gt/gt_rx_1
|
||||
ad_connect axi_ad9371_gt/gt_rx_ip_2 axi_ad9371_rx_os_jesd/gt0_rx
|
||||
ad_connect axi_ad9371_gt/gt_rx_ip_3 axi_ad9371_rx_os_jesd/gt1_rx
|
||||
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_2 axi_ad9371_rx_os_jesd/rxencommaalign_out
|
||||
ad_connect axi_ad9371_gt/rx_gt_comma_align_enb_3 axi_ad9371_rx_os_jesd/rxencommaalign_out
|
||||
ad_connect axi_ad9371_gt/gt_tx_0 util_ad9371_gt/gt_tx_0
|
||||
ad_connect axi_ad9371_gt/gt_tx_1 util_ad9371_gt/gt_tx_1
|
||||
ad_connect axi_ad9371_gt/gt_tx_2 util_ad9371_gt/gt_tx_2
|
||||
ad_connect axi_ad9371_gt/gt_tx_3 util_ad9371_gt/gt_tx_3
|
||||
ad_connect axi_ad9371_gt/gt_tx_ip_0 axi_ad9371_tx_jesd/gt0_tx
|
||||
ad_connect axi_ad9371_gt/gt_tx_ip_1 axi_ad9371_tx_jesd/gt1_tx
|
||||
ad_connect axi_ad9371_gt/gt_tx_ip_2 axi_ad9371_tx_jesd/gt2_tx
|
||||
ad_connect axi_ad9371_gt/gt_tx_ip_3 axi_ad9371_tx_jesd/gt3_tx
|
||||
ad_connect sys_dma_clk sys_ps7/FCLK_CLK2
|
||||
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
|
||||
ad_connect sys_ps7/FCLK_RESET2_N sys_dma_rstgen/ext_reset_in
|
||||
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
|
||||
|
||||
# connections (dac)
|
||||
|
||||
ad_connect util_ad9371_gt/tx_sysref tx_sysref
|
||||
ad_connect util_ad9371_gt/tx_p tx_p
|
||||
ad_connect util_ad9371_gt/tx_n tx_n
|
||||
ad_connect util_ad9371_gt/tx_sync tx_sync
|
||||
ad_connect util_ad9371_gt/tx_out_clk axi_tx_clkgen/clk
|
||||
ad_connect axi_tx_clkgen/clk_0 util_ad9371_gt/tx_clk
|
||||
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_tx_jesd/tx_core_clk
|
||||
ad_connect util_ad9371_gt/tx_ip_rst axi_ad9371_tx_jesd/tx_reset
|
||||
ad_connect util_ad9371_gt/tx_ip_rst_done axi_ad9371_tx_jesd/tx_reset_done
|
||||
ad_connect util_ad9371_gt/tx_ip_sysref axi_ad9371_tx_jesd/tx_sysref
|
||||
ad_connect util_ad9371_gt/tx_ip_sync axi_ad9371_tx_jesd/tx_sync
|
||||
ad_connect util_ad9371_gt/tx_ip_data axi_ad9371_tx_jesd/tx_tdata
|
||||
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_core/dac_clk
|
||||
ad_connect util_ad9371_gt/tx_data axi_ad9371_core/dac_tx_data
|
||||
ad_connect axi_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk
|
||||
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_core/dac_clk
|
||||
ad_connect axi_ad9371_tx_jesd/tx_tdata axi_ad9371_core/dac_tx_data
|
||||
ad_connect axi_ad9371_tx_clkgen/clk_0 util_ad9371_tx_upack/dac_clk
|
||||
ad_connect axi_ad9371_core/dac_valid_i0 util_ad9371_tx_upack/dac_valid_0
|
||||
ad_connect axi_ad9371_core/dac_enable_i0 util_ad9371_tx_upack/dac_enable_0
|
||||
ad_connect axi_ad9371_core/dac_data_i0 util_ad9371_tx_upack/dac_data_0
|
||||
|
|
@ -251,60 +181,29 @@ ad_connect axi_ad9371_core/dac_data_i1 util_ad9371_tx_upack/dac_data_2
|
|||
ad_connect axi_ad9371_core/dac_valid_q1 util_ad9371_tx_upack/dac_valid_3
|
||||
ad_connect axi_ad9371_core/dac_enable_q1 util_ad9371_tx_upack/dac_enable_3
|
||||
ad_connect axi_ad9371_core/dac_data_q1 util_ad9371_tx_upack/dac_data_3
|
||||
|
||||
ad_connect pl_ddr_clk axi_ad9371_dacfifo/ddr_clk
|
||||
ad_connect pl_ddr_clk axi_ad9371_tx_dma/m_axis_aclk
|
||||
ad_connect pl_ddr_clk axi_ad9371_dacfifo/dma_clk
|
||||
ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
|
||||
ad_connect util_ad9371_gt/tx_rst axi_ad9371_dacfifo/dac_rst
|
||||
ad_connect util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
|
||||
ad_connect axi_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
|
||||
ad_connect axi_ad9371_tx_clkgen/clk_0 axi_ad9371_dacfifo/dac_clk
|
||||
ad_connect axi_ad9371_rx_jesd_rstgen/peripheral_reset axi_ad9371_dacfifo/dac_rst
|
||||
ad_connect util_ad9371_tx_upack/dac_valid axi_ad9371_dacfifo/dac_valid
|
||||
ad_connect util_ad9371_tx_upack/dac_data axi_ad9371_dacfifo/dac_data
|
||||
|
||||
ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
|
||||
ad_connect axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready
|
||||
ad_connect axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data
|
||||
ad_connect util_ad9371_tx_upack/dma_xfer_in axi_ad9371_dacfifo/dac_xfer_out
|
||||
ad_connect axi_ad9371_dacfifo/ddr_clk axi_ad9371_dacfifo/dma_clk
|
||||
ad_connect axi_ad9371_dacfifo/ddr_clk axi_ad9371_tx_dma/m_axis_aclk
|
||||
ad_connect axi_ad9371_dacfifo/dma_rvalid axi_ad9371_tx_dma/m_axis_valid
|
||||
ad_connect axi_ad9371_dacfifo/dma_rdata axi_ad9371_tx_dma/m_axis_data
|
||||
ad_connect axi_ad9371_dacfifo/dma_rready axi_ad9371_tx_dma/m_axis_ready
|
||||
ad_connect axi_ad9371_dacfifo/dma_xfer_req axi_ad9371_tx_dma/m_axis_xfer_req
|
||||
ad_connect axi_ad9371_dacfifo/dma_xfer_last axi_ad9371_tx_dma/m_axis_last
|
||||
|
||||
ad_connect dac_fifo_bypass axi_ad9371_dacfifo/dac_fifo_bypass
|
||||
ad_connect axi_ad9371_dacfifo/dac_dunf axi_ad9371_core/dac_dunf
|
||||
ad_connect axi_ad9371_dacfifo/dac_fifo_bypass dac_fifo_bypass
|
||||
ad_connect sys_dma_resetn axi_ad9371_tx_dma/m_src_axi_aresetn
|
||||
|
||||
# connections (adc)
|
||||
|
||||
ad_connect util_ad9371_gt/rx_sysref rx_sysref
|
||||
ad_connect util_ad9371_gt/rx_p rx_p
|
||||
ad_connect util_ad9371_gt/rx_n rx_n
|
||||
ad_connect util_ad9371_gt/rx_sync rx_sync
|
||||
ad_connect util_ad9371_os_gt/rx_p rx_os_p
|
||||
ad_connect util_ad9371_os_gt/rx_n rx_os_n
|
||||
ad_connect util_ad9371_os_gt/rx_sysref rx_sysref
|
||||
ad_connect util_ad9371_os_gt/rx_sync rx_os_sync
|
||||
ad_connect util_ad9371_gt/rx_out_clk axi_rx_clkgen/clk
|
||||
ad_connect axi_rx_clkgen/clk_0 util_ad9371_gt/rx_clk
|
||||
ad_connect axi_rx_clkgen/clk_0 axi_ad9371_rx_jesd/rx_core_clk
|
||||
ad_connect util_ad9371_gt/rx_ip_rst axi_ad9371_rx_jesd/rx_reset
|
||||
ad_connect util_ad9371_gt/rx_ip_rst_done axi_ad9371_rx_jesd/rx_reset_done
|
||||
ad_connect util_ad9371_gt/rx_ip_sysref axi_ad9371_rx_jesd/rx_sysref
|
||||
ad_connect util_ad9371_gt/rx_ip_sync axi_ad9371_rx_jesd/rx_sync
|
||||
ad_connect util_ad9371_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
|
||||
ad_connect util_ad9371_gt/rx_ip_data axi_ad9371_rx_jesd/rx_tdata
|
||||
ad_connect util_ad9371_os_gt/rx_out_clk axi_rx_os_clkgen/clk
|
||||
ad_connect axi_rx_os_clkgen/clk_0 util_ad9371_os_gt/rx_clk
|
||||
ad_connect axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_jesd/rx_core_clk
|
||||
ad_connect util_ad9371_os_gt/rx_ip_rst axi_ad9371_rx_os_jesd/rx_reset
|
||||
ad_connect util_ad9371_os_gt/rx_ip_rst_done axi_ad9371_rx_os_jesd/rx_reset_done
|
||||
ad_connect util_ad9371_os_gt/rx_ip_sysref axi_ad9371_rx_os_jesd/rx_sysref
|
||||
ad_connect util_ad9371_os_gt/rx_ip_sync axi_ad9371_rx_os_jesd/rx_sync
|
||||
ad_connect util_ad9371_os_gt/rx_ip_sof axi_ad9371_rx_jesd/rx_start_of_frame
|
||||
ad_connect util_ad9371_os_gt/rx_ip_data axi_ad9371_rx_os_jesd/rx_tdata
|
||||
ad_connect axi_rx_clkgen/clk_0 axi_ad9371_core/adc_clk
|
||||
ad_connect util_ad9371_gt/rx_data axi_ad9371_core/adc_rx_data
|
||||
ad_connect axi_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk
|
||||
ad_connect util_ad9371_os_gt/rx_data axi_ad9371_core/adc_rx_os_data
|
||||
ad_connect axi_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk
|
||||
ad_connect util_ad9371_gt/rx_rst util_ad9371_rx_cpack/adc_rst
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_core/adc_clk
|
||||
ad_connect axi_ad9371_rx_jesd/rx_start_of_frame axi_ad9371_core/adc_rx_sof
|
||||
ad_connect axi_ad9371_rx_jesd/rx_tdata axi_ad9371_core/adc_rx_data
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 util_ad9371_rx_cpack/adc_clk
|
||||
ad_connect axi_ad9371_rx_jesd_rstgen/peripheral_reset util_ad9371_rx_cpack/adc_rst
|
||||
ad_connect axi_ad9371_core/adc_enable_i0 util_ad9371_rx_cpack/adc_enable_0
|
||||
ad_connect axi_ad9371_core/adc_valid_i0 util_ad9371_rx_cpack/adc_valid_0
|
||||
ad_connect axi_ad9371_core/adc_data_i0 util_ad9371_rx_cpack/adc_data_0
|
||||
|
|
@ -317,45 +216,54 @@ ad_connect axi_ad9371_core/adc_data_i1 util_ad9371_rx_cpack/adc_data_2
|
|||
ad_connect axi_ad9371_core/adc_enable_q1 util_ad9371_rx_cpack/adc_enable_3
|
||||
ad_connect axi_ad9371_core/adc_valid_q1 util_ad9371_rx_cpack/adc_valid_3
|
||||
ad_connect axi_ad9371_core/adc_data_q1 util_ad9371_rx_cpack/adc_data_3
|
||||
ad_connect axi_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
|
||||
ad_connect sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 axi_ad9371_rx_dma/fifo_wr_clk
|
||||
ad_connect util_ad9371_rx_cpack/adc_valid axi_ad9371_rx_dma/fifo_wr_en
|
||||
ad_connect util_ad9371_rx_cpack/adc_sync axi_ad9371_rx_dma/fifo_wr_sync
|
||||
ad_connect util_ad9371_rx_cpack/adc_data axi_ad9371_rx_dma/fifo_wr_din
|
||||
ad_connect axi_ad9371_rx_dma/fifo_wr_overflow axi_ad9371_core/adc_dovf
|
||||
ad_connect axi_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk
|
||||
ad_connect util_ad9371_os_gt/rx_rst util_ad9371_rx_os_cpack/adc_rst
|
||||
ad_connect sys_dma_resetn axi_ad9371_rx_dma/m_dest_axi_aresetn
|
||||
|
||||
# connections (adc-os)
|
||||
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_core/adc_os_clk
|
||||
ad_connect axi_ad9371_rx_os_jesd/rx_start_of_frame axi_ad9371_core/adc_rx_os_sof
|
||||
ad_connect axi_ad9371_rx_os_jesd/rx_tdata axi_ad9371_core/adc_rx_os_data
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 util_ad9371_rx_os_cpack/adc_clk
|
||||
ad_connect axi_ad9371_rx_os_jesd_rstgen/peripheral_reset util_ad9371_rx_os_cpack/adc_rst
|
||||
ad_connect axi_ad9371_core/adc_os_enable_i0 util_ad9371_rx_os_cpack/adc_enable_0
|
||||
ad_connect axi_ad9371_core/adc_os_valid_i0 util_ad9371_rx_os_cpack/adc_valid_0
|
||||
ad_connect axi_ad9371_core/adc_os_data_i0 util_ad9371_rx_os_cpack/adc_data_0
|
||||
ad_connect axi_ad9371_core/adc_os_enable_q0 util_ad9371_rx_os_cpack/adc_enable_1
|
||||
ad_connect axi_ad9371_core/adc_os_valid_q0 util_ad9371_rx_os_cpack/adc_valid_1
|
||||
ad_connect axi_ad9371_core/adc_os_data_q0 util_ad9371_rx_os_cpack/adc_data_1
|
||||
ad_connect axi_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk
|
||||
ad_connect sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 axi_ad9371_rx_os_dma/fifo_wr_clk
|
||||
ad_connect util_ad9371_rx_os_cpack/adc_valid axi_ad9371_rx_os_dma/fifo_wr_en
|
||||
ad_connect util_ad9371_rx_os_cpack/adc_sync axi_ad9371_rx_os_dma/fifo_wr_sync
|
||||
ad_connect util_ad9371_rx_os_cpack/adc_data axi_ad9371_rx_os_dma/fifo_wr_din
|
||||
ad_connect axi_ad9371_rx_os_dma/fifo_wr_overflow axi_ad9371_core/adc_os_dovf
|
||||
ad_connect sys_dma_resetn axi_ad9371_rx_os_dma/m_dest_axi_aresetn
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
ad_cpu_interconnect 0x44A60000 axi_ad9371_gt
|
||||
ad_cpu_interconnect 0x44A00000 axi_ad9371_core
|
||||
ad_cpu_interconnect 0x43C00000 axi_tx_clkgen
|
||||
ad_cpu_interconnect 0x44A60000 axi_ad9371_tx_xcvr
|
||||
ad_cpu_interconnect 0x43C00000 axi_ad9371_tx_clkgen
|
||||
ad_cpu_interconnect 0x44A90000 axi_ad9371_tx_jesd
|
||||
ad_cpu_interconnect 0x7c420000 axi_ad9371_tx_dma
|
||||
ad_cpu_interconnect 0x43C10000 axi_rx_clkgen
|
||||
ad_cpu_interconnect 0x43C20000 axi_rx_os_clkgen
|
||||
ad_cpu_interconnect 0x44A61000 axi_ad9371_rx_xcvr
|
||||
ad_cpu_interconnect 0x43C10000 axi_ad9371_rx_clkgen
|
||||
ad_cpu_interconnect 0x44A91000 axi_ad9371_rx_jesd
|
||||
ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
|
||||
ad_cpu_interconnect 0x7c400000 axi_ad9371_rx_dma
|
||||
ad_cpu_interconnect 0x44A62000 axi_ad9371_rx_os_xcvr
|
||||
ad_cpu_interconnect 0x43C20000 axi_ad9371_rx_os_clkgen
|
||||
ad_cpu_interconnect 0x44A92000 axi_ad9371_rx_os_jesd
|
||||
ad_cpu_interconnect 0x7c440000 axi_ad9371_rx_os_dma
|
||||
|
||||
# gt uses hp3, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_gt/m_axi
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_xcvr/m_axi
|
||||
ad_mem_hp3_interconnect sys_cpu_clk axi_ad9371_rx_os_xcvr/m_axi
|
||||
|
||||
# interconnect (mem/dac)
|
||||
|
||||
|
|
@ -365,22 +273,6 @@ ad_mem_hp2_interconnect sys_dma_clk sys_ps7/S_AXI_HP2
|
|||
ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_dma/m_dest_axi
|
||||
ad_mem_hp2_interconnect sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi
|
||||
|
||||
ad_disconnect sys_cpu_resetn axi_hp1_interconnect/ARESETN
|
||||
ad_disconnect sys_cpu_resetn axi_hp1_interconnect/M00_ARESETN
|
||||
ad_disconnect sys_cpu_resetn axi_hp1_interconnect/S00_ARESETN
|
||||
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/ARESETN
|
||||
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/M00_ARESETN
|
||||
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S00_ARESETN
|
||||
ad_disconnect sys_cpu_resetn axi_hp2_interconnect/S01_ARESETN
|
||||
|
||||
ad_connect sys_dma_resetn axi_hp1_interconnect/ARESETN
|
||||
ad_connect sys_dma_resetn axi_hp1_interconnect/M00_ARESETN
|
||||
ad_connect sys_dma_resetn axi_hp1_interconnect/S00_ARESETN
|
||||
ad_connect sys_dma_resetn axi_hp2_interconnect/ARESETN
|
||||
ad_connect sys_dma_resetn axi_hp2_interconnect/M00_ARESETN
|
||||
ad_connect sys_dma_resetn axi_hp2_interconnect/S00_ARESETN
|
||||
ad_connect sys_dma_resetn axi_hp2_interconnect/S01_ARESETN
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-11 mb-11 axi_ad9371_rx_os_dma/irq
|
||||
|
|
@ -399,11 +291,11 @@ set_property -dict [list CONFIG.C_PROBE3_WIDTH {16}] $ila_adc
|
|||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_adc
|
||||
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_adc
|
||||
|
||||
ad_connect axi_rx_clkgen/clk_0 ila_adc/clk
|
||||
ad_connect axi_ad9371_core/adc_data_i0 ila_adc/probe0
|
||||
ad_connect axi_ad9371_core/adc_data_q0 ila_adc/probe1
|
||||
ad_connect axi_ad9371_core/adc_data_i1 ila_adc/probe2
|
||||
ad_connect axi_ad9371_core/adc_data_q1 ila_adc/probe3
|
||||
ad_connect axi_ad9371_rx_clkgen/clk_0 ila_adc/clk
|
||||
ad_connect axi_ad9371_core/adc_data_i0 ila_adc/probe0
|
||||
ad_connect axi_ad9371_core/adc_data_q0 ila_adc/probe1
|
||||
ad_connect axi_ad9371_core/adc_data_i1 ila_adc/probe2
|
||||
ad_connect axi_ad9371_core/adc_data_q1 ila_adc/probe3
|
||||
|
||||
set bsplit_os_adc_0 [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 bsplit_os_adc_0]
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {16}] $bsplit_os_adc_0
|
||||
|
|
@ -425,13 +317,13 @@ set_property -dict [list CONFIG.C_PROBE5_WIDTH {16}] $ila_os_adc
|
|||
set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_os_adc
|
||||
set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_os_adc
|
||||
|
||||
ad_connect axi_ad9371_core/adc_os_data_i0 bsplit_os_adc_0/data
|
||||
ad_connect axi_ad9371_core/adc_os_data_q0 bsplit_os_adc_1/data
|
||||
ad_connect axi_rx_os_clkgen/clk_0 ila_os_adc/clk
|
||||
ad_connect axi_ad9371_core/adc_os_valid_i0 ila_os_adc/probe0
|
||||
ad_connect bsplit_os_adc_0/split_data_0 ila_os_adc/probe1
|
||||
ad_connect bsplit_os_adc_0/split_data_1 ila_os_adc/probe2
|
||||
ad_connect axi_ad9371_core/adc_os_valid_q0 ila_os_adc/probe3
|
||||
ad_connect bsplit_os_adc_1/split_data_0 ila_os_adc/probe4
|
||||
ad_connect bsplit_os_adc_1/split_data_1 ila_os_adc/probe5
|
||||
ad_connect axi_ad9371_core/adc_os_data_i0 bsplit_os_adc_0/data
|
||||
ad_connect axi_ad9371_core/adc_os_data_q0 bsplit_os_adc_1/data
|
||||
ad_connect axi_ad9371_rx_os_clkgen/clk_0 ila_os_adc/clk
|
||||
ad_connect axi_ad9371_core/adc_os_valid_i0 ila_os_adc/probe0
|
||||
ad_connect bsplit_os_adc_0/split_data_0 ila_os_adc/probe1
|
||||
ad_connect bsplit_os_adc_0/split_data_1 ila_os_adc/probe2
|
||||
ad_connect axi_ad9371_core/adc_os_valid_q0 ila_os_adc/probe3
|
||||
ad_connect bsplit_os_adc_1/split_data_0 ila_os_adc/probe4
|
||||
ad_connect bsplit_os_adc_1/split_data_1 ila_os_adc/probe5
|
||||
|
||||
|
|
|
|||
|
|
@ -68,13 +68,10 @@ set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVCMOS25} [get_ports ad9371_g
|
|||
|
||||
# clocks
|
||||
|
||||
create_clock -name tx_ref_clk -period 6.25 [get_ports ref_clk0_p]
|
||||
create_clock -name rx_ref_clk -period 6.25 [get_ports ref_clk1_p]
|
||||
create_clock -name tx_div_clk -period 6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 6.25 [get_pins i_system_wrapper/system_i/axi_ad9371_gt/inst/g_lane_1[0].i_channel/i_gt/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name tx_ref_clk -period 8.00 [get_ports ref_clk0_p]
|
||||
create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk1_p]
|
||||
create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK]
|
||||
create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
|
||||
create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK]
|
||||
|
||||
# sync is also sampled at the cpu clock by the ip.
|
||||
|
||||
set_false_path -from [get_cells -hier -filter {name =~ *axi_ad9371_gt*tx_ip_sync* && IS_SEQUENTIAL}] \
|
||||
-to [get_cells -hier -filter {name =~ *axi_ad9371_tx_jesd*sync_tx_sync*data_sync* && IS_SEQUENTIAL}]
|
||||
|
||||
|
|
|
|||
|
|
@ -346,6 +346,22 @@ module system_top (
|
|||
.dio_p (gpio_bd));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.dac_fifo_bypass (gpio_o[60]),
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
.ddr3_ck_n (ddr3_ck_n),
|
||||
.ddr3_ck_p (ddr3_ck_p),
|
||||
.ddr3_cke (ddr3_cke),
|
||||
.ddr3_cs_n (ddr3_cs_n),
|
||||
.ddr3_dm (ddr3_dm),
|
||||
.ddr3_dq (ddr3_dq),
|
||||
.ddr3_dqs_n (ddr3_dqs_n),
|
||||
.ddr3_dqs_p (ddr3_dqs_p),
|
||||
.ddr3_odt (ddr3_odt),
|
||||
.ddr3_ras_n (ddr3_ras_n),
|
||||
.ddr3_reset_n (ddr3_reset_n),
|
||||
.ddr3_we_n (ddr3_we_n),
|
||||
.ddr_addr (ddr_addr),
|
||||
.ddr_ba (ddr_ba),
|
||||
.ddr_cas_n (ddr_cas_n),
|
||||
|
|
@ -388,14 +404,20 @@ module system_top (
|
|||
.ps_intr_08 (1'b0),
|
||||
.ps_intr_09 (1'b0),
|
||||
.ps_intr_10 (1'b0),
|
||||
.rx_n (rx_data_n[1:0]),
|
||||
.rx_os_n (rx_data_n[3:2]),
|
||||
.rx_os_p (rx_data_p[3:2]),
|
||||
.rx_os_sync (rx_os_sync),
|
||||
.rx_p (rx_data_p[1:0]),
|
||||
.rx_ref_clk (ref_clk1),
|
||||
.rx_sync (rx_sync),
|
||||
.rx_sysref (sysref),
|
||||
.rx_data_0_n (rx_data_n[0]),
|
||||
.rx_data_0_p (rx_data_p[0]),
|
||||
.rx_data_1_n (rx_data_n[1]),
|
||||
.rx_data_1_p (rx_data_p[1]),
|
||||
.rx_data_2_n (rx_data_n[2]),
|
||||
.rx_data_2_p (rx_data_p[2]),
|
||||
.rx_data_3_n (rx_data_n[3]),
|
||||
.rx_data_3_p (rx_data_p[3]),
|
||||
.rx_ref_clk_0 (ref_clk1),
|
||||
.rx_ref_clk_2 (ref_clk1),
|
||||
.rx_sync_0 (rx_sync),
|
||||
.rx_sync_2 (rx_os_sync),
|
||||
.rx_sysref_0 (sysref),
|
||||
.rx_sysref_2 (sysref),
|
||||
.spdif (spdif),
|
||||
.spi0_clk_i (spi_clk),
|
||||
.spi0_clk_o (spi_clk),
|
||||
|
|
@ -415,30 +437,20 @@ module system_top (
|
|||
.spi1_sdi_i (1'd0),
|
||||
.spi1_sdo_i (1'd0),
|
||||
.spi1_sdo_o (),
|
||||
.tx_n (tx_data_n),
|
||||
.tx_p (tx_data_p),
|
||||
.tx_ref_clk (ref_clk1),
|
||||
.tx_sync (tx_sync),
|
||||
.tx_sysref (sysref),
|
||||
.dac_fifo_bypass(gpio_o[60]),
|
||||
.sys_rst(sys_rst),
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.sys_clk_clk_n (sys_clk_n),
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
.ddr3_ck_n (ddr3_ck_n),
|
||||
.ddr3_ck_p (ddr3_ck_p),
|
||||
.ddr3_cke (ddr3_cke),
|
||||
.ddr3_cs_n (ddr3_cs_n),
|
||||
.ddr3_dm (ddr3_dm),
|
||||
.ddr3_dq (ddr3_dq),
|
||||
.ddr3_dqs_n (ddr3_dqs_n),
|
||||
.ddr3_dqs_p (ddr3_dqs_p),
|
||||
.ddr3_odt (ddr3_odt),
|
||||
.ddr3_ras_n (ddr3_ras_n),
|
||||
.ddr3_reset_n (ddr3_reset_n),
|
||||
.ddr3_we_n (ddr3_we_n));
|
||||
.sys_clk_clk_p (sys_clk_p),
|
||||
.sys_rst(sys_rst),
|
||||
.tx_data_0_n (tx_data_n[0]),
|
||||
.tx_data_0_p (tx_data_p[0]),
|
||||
.tx_data_1_n (tx_data_n[1]),
|
||||
.tx_data_1_p (tx_data_p[1]),
|
||||
.tx_data_2_n (tx_data_n[2]),
|
||||
.tx_data_2_p (tx_data_p[2]),
|
||||
.tx_data_3_n (tx_data_n[3]),
|
||||
.tx_data_3_p (tx_data_p[3]),
|
||||
.tx_ref_clk_0 (ref_clk1),
|
||||
.tx_sync_0 (tx_sync),
|
||||
.tx_sysref_0 (sysref));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue