From 496b4ec7489d39bacd152b23151ad86557db628c Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 29 Apr 2022 08:59:33 +0100 Subject: [PATCH] ad9213_dual_ebz: Fix constraints - added sysref constraint - remove false path from the GPIO pins --- .../ad9213_dual_ebz/s10soc/system_constr.sdc | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-) diff --git a/projects/ad9213_dual_ebz/s10soc/system_constr.sdc b/projects/ad9213_dual_ebz/s10soc/system_constr.sdc index 4a6463a83..d19656493 100755 --- a/projects/ad9213_dual_ebz/s10soc/system_constr.sdc +++ b/projects/ad9213_dual_ebz/s10soc/system_constr.sdc @@ -1,25 +1,11 @@ -create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] +create_clock -period "10.000 ns" -name sys_clk_100mhz [get_ports {sys_clk}] create_clock -period "3.2 ns" -name ref_a_clk0 [get_ports {rx_ref_a_clk0}] create_clock -period "3.2 ns" -name ref_a_clk1 [get_ports {rx_ref_a_clk1}] create_clock -period "3.2 ns" -name ref_b_clk0 [get_ports {rx_ref_b_clk0}] create_clock -period "3.2 ns" -name ref_b_clk1 [get_ports {rx_ref_b_clk1}] create_clock -period "3.2 ns" -name device_clk [get_ports {rx_device_clk_0}] -# Asynchronous GPIOs +set_input_delay -clock {device_clk} 0.2 [get_ports {rx_sysref_a}] -foreach async_input {ad9213_a_gpio[*] ad9213_b_gpio[*]} { - set_false_path -to [get_ports $async_input] -} - -foreach async_output {ad9213_a_rst ad9213_b_rst ad9213_a_gpio[*] ad9213_b_gpio[*]} { - set_false_path -to [get_ports $async_output] -} - -derive_pll_clocks -derive_clock_uncertainty - -# set_false_path -to [get_registers *sys_gpio_bd|readdata[12]*] -# set_false_path -to [get_registers *sys_gpio_bd|readdata[13]*] -# set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*]