data_offload: Fix Tx bypass
Tx path was gated by the FSM also in bypass mode. This must be avoided since the bypass mode should be independent of the FSM. Write to bypass fifo only when bypass is enabledmain
parent
54a22d036c
commit
4982104982
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@ -228,7 +228,7 @@ module data_offload #(
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.wr_fsm_state_out (src_fsm_status_s),
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.rd_fsm_state_out (dst_fsm_status_s));
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assign m_axis_valid = rd_ready & ((dst_bypass_s) ? valid_bypass_s : s_storage_axis_valid);
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assign m_axis_valid = dst_bypass_s ? valid_bypass_s : (rd_ready & s_storage_axis_valid);
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// For DAC paths set zero as IDLE data on the axis bus, avoid repeating last
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// sample.
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assign m_axis_data = TX_OR_RXN_PATH[0] & ~m_axis_valid ? {DST_DATA_WIDTH{1'b0}} :
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@ -236,7 +236,7 @@ module data_offload #(
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assign m_axis_last = (dst_bypass_s) ? 1'b0 : s_storage_axis_last;
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assign m_axis_tkeep = (dst_bypass_s) ? {DST_DATA_WIDTH/8{1'b1}} : s_storage_axis_tkeep;
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assign s_axis_ready = wr_ready & ((src_bypass_s) ? ready_bypass_s : m_storage_axis_ready);
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assign s_axis_ready = src_bypass_s ? ready_bypass_s : (wr_ready & m_storage_axis_ready);
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assign m_storage_axis_valid = s_axis_valid & wr_ready;
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assign m_storage_axis_data = s_axis_data;
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@ -267,7 +267,7 @@ module data_offload #(
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.s_axis_aclk (s_axis_aclk),
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.s_axis_aresetn (src_rstn),
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.s_axis_ready (ready_bypass_s),
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.s_axis_valid (s_axis_valid),
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.s_axis_valid (s_axis_valid & src_bypass_s),
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.s_axis_data (s_axis_data),
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.s_axis_tlast (),
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.s_axis_full (),
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