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sysid_intel: Added hw.tcl for sysid IP cores

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Arpadi 2020-03-16 00:40:48 +02:00 committed by sarpadi
parent 1e537b1083
commit 4a28a4e856
2 changed files with 77 additions and 0 deletions
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39
library/axi_sysid/axi_sysid_hw.tcl Normal file
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package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_sysid
set_module_property DESCRIPTION "AXI System ID"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME axi_sysid
# source files
ad_ip_files axi_sysid [list \
"$ad_hdl_dir/library/common/up_axi.v" \
"axi_sysid.v"]
# IP parameters
add_parameter ROM_WIDTH INTEGER 32
set_parameter_property ROM_WIDTH DEFAULT_VALUE 32
set_parameter_property ROM_WIDTH DISPLAY_NAME "ROM width"
set_parameter_property ROM_WIDTH UNITS None
set_parameter_property ROM_WIDTH HDL_PARAMETER true
add_parameter ROM_ADDR_BITS INTEGER 9
set_parameter_property ROM_ADDR_BITS DEFAULT_VALUE 9
set_parameter_property ROM_ADDR_BITS DISPLAY_NAME "ROM address bits"
set_parameter_property ROM_ADDR_BITS HDL_PARAMETER true
# AXI4 Memory Mapped Interface
ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 15
# external clock and control/status ports
ad_interface signal sys_rom_data input ROM_WIDTH rom_data
ad_interface signal pr_rom_data input ROM_WIDTH rom_data
ad_interface signal rom_addr output ROM_ADDR_BITS

38
library/sysid_rom/sysid_rom_hw.tcl Normal file
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package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME sysid_rom
set_module_property DESCRIPTION "System ID ROM"
set_module_property VERSION 1.0
set_module_property GROUP "Analog Devices"
set_module_property DISPLAY_NAME sysid_rom
# source files
ad_ip_files sysid_rom [list \
"sysid_rom.v"]
# IP parameters
add_parameter ROM_WIDTH INTEGER 32
set_parameter_property ROM_WIDTH DEFAULT_VALUE 32
set_parameter_property ROM_WIDTH DISPLAY_NAME "ROM width"
set_parameter_property ROM_WIDTH UNITS None
set_parameter_property ROM_WIDTH HDL_PARAMETER true
add_parameter ROM_ADDR_BITS INTEGER 6
set_parameter_property ROM_ADDR_BITS DEFAULT_VALUE 6
set_parameter_property ROM_ADDR_BITS DISPLAY_NAME "ROM address bits"
set_parameter_property ROM_ADDR_BITS HDL_PARAMETER true
add_parameter PATH_TO_FILE STRING "path_to_mem_init_file"
set_parameter_property PATH_TO_FILE DISPLAY_NAME "Path to file"
set_parameter_property PATH_TO_FILE HDL_PARAMETER true
# external clock and control/status ports
ad_interface clock clk input 1
ad_interface signal rom_data output ROM_WIDTH rom_data
ad_interface signal rom_addr input ROM_ADDR_BITS