scripts- reconnect added
parent
ffec95f220
commit
4a5b7fc723
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@ -132,16 +132,16 @@ proc ad_xcvrcon {u_xcvr a_xcvr a_jesd} {
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set m [expr ($n + $index)]
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if {$tx_or_rx_n == 0} {
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ad_connect ${a_xcvr}/up_es_${m} ${u_xcvr}/up_es_${m}
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ad_connect ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${m}
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ad_connect ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${m}
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}
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if {(($m%4) == 0) && ($qpll_enable == 1)} {
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ad_connect ${a_xcvr}/up_cm_${m} ${u_xcvr}/up_cm_${m}
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ad_connect ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
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}
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ad_connect ${a_xcvr}/up_ch_${m} ${u_xcvr}/up_${txrx}_${m}
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ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${m}_${txrx}
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ad_connect ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${m}
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ad_connect ${u_xcvr}/${txrx}_${m} ${a_jesd}/gt${n}_${txrx}
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ad_connect ${u_xcvr}/${txrx}_out_clk_${index} ${u_xcvr}/${txrx}_clk_${m}
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if {(($m%4) == 0) && ($qpll_enable == 1)} {
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@ -181,10 +181,32 @@ proc ad_disconnect {p_name_1 p_name_2} {
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set m_name_2 [ad_connect_type $p_name_2]
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if {[get_property CLASS $m_name_1] eq "bd_net"} {
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puts "disconnect_bd_net $m_name_1 $m_name_2"
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disconnect_bd_net $m_name_1 $m_name_2
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return
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}
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}
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proc ad_reconct {p_name_1 p_name_2} {
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set m_name_1 [ad_connect_type $p_name_1]
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set m_name_2 [ad_connect_type $p_name_2]
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if {[get_property CLASS $m_name_1] eq "bd_pin"} {
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delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
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[find_bd_objs -relation connected_to $m_name_1]]
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delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
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[find_bd_objs -relation connected_to $m_name_2]]
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}
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if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
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delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
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[find_bd_objs -relation connected_to $m_name_1]]
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delete_bd_objs -quiet [get_bd_intf_nets -quiet -of_objects \
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[find_bd_objs -relation connected_to $m_name_2]]
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}
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ad_connect $p_name_1 $p_name_2
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}
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###################################################################################################
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@ -356,12 +378,17 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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set p_intf_clock ""
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}
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regsub clk $p_clk resetn p_rst
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if {[get_bd_nets -quiet $p_rst] eq ""} {
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set p_rst sys_cpu_resetn
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}
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if {$m_interconnect_index == 0} {
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set_property CONFIG.NUM_MI 1 $m_interconnect_cell
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set_property CONFIG.NUM_SI 1 $m_interconnect_cell
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ad_connect sys_cpu_resetn $m_interconnect_cell/ARESETN
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ad_connect $p_rst $m_interconnect_cell/ARESETN
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ad_connect $p_clk $m_interconnect_cell/ACLK
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ad_connect sys_cpu_resetn $m_interconnect_cell/M00_ARESETN
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ad_connect $p_rst $m_interconnect_cell/M00_ARESETN
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ad_connect $p_clk $m_interconnect_cell/M00_ACLK
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ad_connect $m_interconnect_cell/M00_AXI $p_name_int
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if {$p_intf_clock ne ""} {
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@ -369,7 +396,7 @@ proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
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}
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} else {
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set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
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ad_connect sys_cpu_resetn $m_interconnect_cell/${i_str}_ARESETN
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ad_connect $p_rst $m_interconnect_cell/${i_str}_ARESETN
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ad_connect $p_clk $m_interconnect_cell/${i_str}_ACLK
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ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
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if {$p_intf_clock ne ""} {
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