axi_adc_decimate: Initial commit
Adrian Costina
parent
35b97abc6d
commit
4a7232cbcb
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####################################################################################
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####################################################################################
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## Copyright 2011(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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####################################################################################
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M_DEPS += ../common/ad_rst.v
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M_DEPS += ../common/up_axi.v
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M_DEPS += ../common/up_xfer_cntrl.v
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M_DEPS += ../scripts/adi_env.tcl
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M_DEPS += ../scripts/adi_ip.tcl
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M_DEPS += axi_adc_decimate.v
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M_DEPS += axi_adc_decimate_constr.xdc
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M_DEPS += axi_adc_decimate_ip.tcl
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M_DEPS += axi_adc_decimate_reg.v
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M_DEPS += cic_decim.v
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M_DEPS += fir_decim.v
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M_VIVADO := vivado -mode batch -source
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M_FLIST := *.cache
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M_FLIST += *.data
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M_FLIST += *.xpr
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M_FLIST += *.log
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M_FLIST += component.xml
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M_FLIST += *.jou
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M_FLIST += xgui
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M_FLIST += *.ip_user_files
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M_FLIST += *.srcs
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M_FLIST += *.hw
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M_FLIST += *.sim
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M_FLIST += .Xil
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.PHONY: all clean clean-all
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all: axi_adc_decimate.xpr
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clean:clean-all
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clean-all:
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rm -rf $(M_FLIST)
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axi_adc_decimate.xpr: $(M_DEPS)
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-rm -rf $(M_FLIST)
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$(M_VIVADO) axi_adc_decimate_ip.tcl >> axi_adc_decimate_ip.log 2>&1
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####################################################################################
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####################################################################################
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@ -0,0 +1,272 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
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||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
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||||
// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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||||
// from this software without specific prior written permission.
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||||
// - The use of this software may or may not infringe the patent rights
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||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adc_decimate(
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input adc_clk,
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input [15:0] adc_data_a,
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input [15:0] adc_data_b,
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input adc_valid_a,
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input adc_valid_b,
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output reg [15:0] adc_dec_data_a,
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output reg [15:0] adc_dec_data_b,
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output reg adc_dec_valid_a,
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output reg adc_dec_valid_b,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [13:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [13:0] up_raddr;
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wire [31:0] decimation_ratio;
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wire [31:0] filter_mask;
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wire [105:0] adc_cic_data_a;
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wire adc_cic_valid_a;
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wire [105:0] adc_cic_data_b;
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wire adc_cic_valid_b;
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wire [25:0] adc_fir_data_a;
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wire adc_fir_valid_a;
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wire [25:0] adc_fir_data_b;
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wire adc_fir_valid_b;
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reg adc_dec_valid_a_filter;
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reg adc_dec_valid_b_filter;
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reg [31:0] decimation_counter;
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reg [15:0] decim_rate_cic;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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cic_decim cic_decimation_a (
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.clk(adc_clk),
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.clk_enable(adc_valid_a),
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.reset(adc_rst),
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.filter_in(adc_data_a[11:0]),
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.rate(decim_rate_cic),
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.load_rate(1'b0),
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.filter_out(adc_cic_data_a),
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.ce_out(adc_cic_valid_a));
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cic_decim cic_decimation_b (
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.clk(adc_clk),
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.clk_enable(adc_valid_b),
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.reset(adc_rst),
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.filter_in(adc_data_b[11:0]),
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.rate(decim_rate_cic),
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.load_rate(1'b0),
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.filter_out(adc_cic_data_b),
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.ce_out(adc_cic_valid_b));
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fir_decim fir_decimation_a (
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.clk(adc_clk),
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.clk_enable(adc_cic_valid_a),
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.reset(adc_rst),
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.filter_in(adc_cic_data_a[11:0]),
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.filter_out(adc_fir_data_a),
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.ce_out(adc_fir_valid_a));
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fir_decim fir_decimation_b (
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.clk(adc_clk),
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.clk_enable(adc_cic_valid_b),
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.reset(adc_rst),
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.filter_in(adc_cic_data_b[11:0]),
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.filter_out(adc_fir_data_b),
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.ce_out(adc_fir_valid_b));
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always @(*) begin
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case (filter_mask)
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16'h1: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h2: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h3: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h6: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h7: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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default: adc_dec_data_a = adc_data_a;
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endcase
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case (filter_mask)
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16'h1: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h2: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h3: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h6: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h7: adc_dec_valid_a_filter = adc_fir_valid_a;
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default: adc_dec_valid_a_filter = adc_valid_a;
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endcase
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case (filter_mask)
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16'h1: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h2: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h3: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h6: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h7: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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default: adc_dec_data_b = adc_data_b;
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endcase
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case (filter_mask)
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16'h1: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h2: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h3: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h6: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h7: adc_dec_valid_b_filter = adc_fir_valid_b;
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default: adc_dec_valid_b_filter = adc_valid_b;
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endcase
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case (filter_mask)
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16'h1: decim_rate_cic = 16'd5;
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16'h2: decim_rate_cic = 16'd50;
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16'h3: decim_rate_cic = 16'd500;
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16'h6: decim_rate_cic = 16'd5000;
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16'h7: decim_rate_cic = 16'd50000;
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default: decim_rate_cic = 9'd1;
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endcase
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end
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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decimation_counter <= 32'b0;
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adc_dec_valid_a <= 1'b0;
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adc_dec_valid_b <= 1'b0;
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end else begin
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if (adc_dec_valid_a_filter == 1'b1) begin
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if (decimation_counter < decimation_ratio) begin
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decimation_counter <= decimation_counter + 1;
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adc_dec_valid_a <= 1'b0;
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adc_dec_valid_b <= 1'b0;
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end else begin
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decimation_counter <= 0;
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adc_dec_valid_a <= 1'b1;
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adc_dec_valid_b <= 1'b1;
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end
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end else begin
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adc_dec_valid_a <= 1'b0;
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adc_dec_valid_b <= 1'b0;
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end
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end
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end
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axi_adc_decimate_reg axi_adc_decimate_reg (
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.clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_decimation_ratio (decimation_ratio),
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.adc_filter_mask (filter_mask),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,8 @@
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set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_state*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *d_xfer_toggle*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *up_xfer_toggle*}]
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set_property shreg_extract no [get_cells -hier -filter {name =~ *ad_rst_sync*}]
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set_false_path -from [get_cells -hier -filter {name =~ *d_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *up_xfer_state_m1_reg && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_toggle_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_xfer_toggle_m1_reg && IS_SEQUENTIAL}]
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set_false_path -from [get_cells -hier -filter {name =~ *up_xfer_data* && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *d_data_cntrl* && IS_SEQUENTIAL}]
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@ -0,0 +1,25 @@
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_adc_decimate
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adi_ip_files axi_adc_decimate [list \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"axi_adc_decimate_constr.xdc" \
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"fir_decim.v" \
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"cic_decim.v" \
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"axi_adc_decimate_reg.v" \
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"axi_adc_decimate.v" ]
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adi_ip_properties axi_adc_decimate
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adi_ip_constraints axi_adc_decimate [list \
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"axi_adc_decimate_constr.xdc" ]
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ipx::remove_bus_interface {clk} [ipx::current_core]
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ipx::associate_bus_interfaces -busif s_axi -clock s_axi_aclk [ipx::current_core]
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ipx::save_core [ipx::current_core]
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@ -0,0 +1,137 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
|
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// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
// - Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// - Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in
|
||||
// the documentation and/or other materials provided with the
|
||||
// distribution.
|
||||
// - Neither the name of Analog Devices, Inc. nor the names of its
|
||||
// contributors may be used to endorse or promote products derived
|
||||
// from this software without specific prior written permission.
|
||||
// - The use of this software may or may not infringe the patent rights
|
||||
// of one or more patent holders. This license does not release you
|
||||
// from the requirement that you obtain separate licenses from these
|
||||
// patent holders to use this software.
|
||||
// - Use of the software either in source or binary form, must be run
|
||||
// on or directly connected to an Analog Devices Inc. component.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
|
||||
// PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
//
|
||||
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
|
||||
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
|
||||
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
|
||||
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module axi_adc_decimate_reg(
|
||||
|
||||
input clk,
|
||||
output adc_rst,
|
||||
|
||||
output [31:0] adc_decimation_ratio,
|
||||
output [31:0] adc_filter_mask,
|
||||
|
||||
// bus interface
|
||||
|
||||
input up_rstn,
|
||||
input up_clk,
|
||||
input up_wreq,
|
||||
input [13:0] up_waddr,
|
||||
input [31:0] up_wdata,
|
||||
output reg up_wack,
|
||||
input up_rreq,
|
||||
input [13:0] up_raddr,
|
||||
output reg [31:0] up_rdata,
|
||||
output reg up_rack);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire up_wreq_s;
|
||||
wire up_rreq_s;
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [31:0] up_version = 32'h00010000;
|
||||
reg [31:0] up_scratch = 32'h0;
|
||||
|
||||
reg [31:0] up_decimation_ratio = 32'h0;
|
||||
reg [31:0] up_filter_mask = 32'h0;
|
||||
|
||||
assign up_wreq_s = ((up_waddr[13:5] == 6'h00)) ? up_wreq : 1'b0;
|
||||
assign up_rreq_s = ((up_raddr[13:5] == 6'h00)) ? up_rreq : 1'b0;
|
||||
|
||||
ad_rst i_core_rst_reg (.preset(~up_rstn), .clk(clk), .rst(adc_rst));
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_wack <= 'd0;
|
||||
up_scratch <= 'd0;
|
||||
up_decimation_ratio <= 'd0;
|
||||
up_filter_mask <= 'd0;
|
||||
end else begin
|
||||
up_wack <= up_wreq_s;
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h1)) begin
|
||||
up_scratch <= up_wdata;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h10)) begin
|
||||
up_decimation_ratio <= up_wdata;
|
||||
end
|
||||
if ((up_wreq_s == 1'b1) && (up_waddr[4:0] == 5'h11)) begin
|
||||
up_filter_mask <= up_wdata;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// processor read interface
|
||||
|
||||
always @(negedge up_rstn or posedge up_clk) begin
|
||||
if (up_rstn == 0) begin
|
||||
up_rack <= 'd0;
|
||||
up_rdata <= 'd0;
|
||||
end else begin
|
||||
up_rack <= up_rreq_s;
|
||||
if (up_rreq_s == 1'b1) begin
|
||||
case (up_raddr[4:0])
|
||||
5'h0: up_rdata <= up_version;
|
||||
5'h1: up_rdata <= up_scratch;
|
||||
5'h10: up_rdata <= up_decimation_ratio;
|
||||
5'h11: up_rdata <= up_filter_mask;
|
||||
default: up_rdata <= 0;
|
||||
endcase
|
||||
end else begin
|
||||
up_rdata <= 32'd0;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
up_xfer_cntrl #(.DATA_WIDTH(64)) i_xfer_cntrl (
|
||||
.up_rstn (up_rstn),
|
||||
.up_clk (up_clk),
|
||||
.up_data_cntrl ({ up_decimation_ratio, // 32
|
||||
up_filter_mask}), // 32
|
||||
|
||||
.up_xfer_done (),
|
||||
.d_rst (1'b0),
|
||||
.d_clk (clk),
|
||||
.d_data_cntrl ({ adc_decimation_ratio, // 32
|
||||
adc_filter_mask})); // 32
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
|
|
@ -0,0 +1,610 @@
|
|||
// -------------------------------------------------------------
|
||||
//
|
||||
// Module: cic_decim
|
||||
// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
|
||||
// Generated on: 2016-07-05 15:46:18
|
||||
// -------------------------------------------------------------
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Code Generation Options:
|
||||
//
|
||||
// OptimizeForHDL: on
|
||||
// EDAScriptGeneration: off
|
||||
// AddPipelineRegisters: on
|
||||
// Name: cic_decim
|
||||
// AddRatePort: on
|
||||
// InputDataType: numerictype(1,12,11)
|
||||
// TargetLanguage: Verilog
|
||||
// TestBenchName: cicdecimfilt_copy_tb
|
||||
// TestBenchStimulus: step ramp chirp noise
|
||||
// GenerateHDLTestBench: off
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Implementation : Fully parallel
|
||||
// -------------------------------------------------------------
|
||||
// Filter Settings:
|
||||
//
|
||||
// Discrete-Time FIR Multirate Filter (real)
|
||||
// -----------------------------------------
|
||||
// Filter Structure : Cascaded Integrator-Comb Decimator
|
||||
// Decimation Factor : 50000
|
||||
// Differential Delay : 1
|
||||
// Number of Sections : 6
|
||||
// Stable : Yes
|
||||
// Linear Phase : No
|
||||
//
|
||||
// -------------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module cic_decim
|
||||
(
|
||||
clk,
|
||||
clk_enable,
|
||||
reset,
|
||||
filter_in,
|
||||
rate,
|
||||
load_rate,
|
||||
filter_out,
|
||||
ce_out
|
||||
);
|
||||
|
||||
input clk;
|
||||
input clk_enable;
|
||||
input reset;
|
||||
input signed [11:0] filter_in; //sfix12_En11
|
||||
input [15:0] rate; //ufix16
|
||||
input load_rate;
|
||||
output signed [105:0] filter_out; //sfix106_En11
|
||||
output ce_out;
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
//Module Architecture: cic_decim
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Local Functions
|
||||
// Type Definitions
|
||||
// Constants
|
||||
// Signals
|
||||
reg [15:0] rate_register; // ufix16
|
||||
reg [15:0] cur_count; // ufix16
|
||||
wire phase_1; // boolean
|
||||
wire ce_delayline; // boolean
|
||||
reg int_delay_pipe [0:4] ; // boolean
|
||||
wire ce_gated; // boolean
|
||||
reg ce_out_reg; // boolean
|
||||
//
|
||||
reg signed [11:0] input_register; // sfix12_En11
|
||||
// -- Section 1 Signals
|
||||
wire signed [11:0] section_in1; // sfix12_En11
|
||||
wire signed [105:0] section_cast1; // sfix106_En11
|
||||
wire signed [105:0] sum1; // sfix106_En11
|
||||
reg signed [105:0] section_out1; // sfix106_En11
|
||||
wire signed [105:0] add_cast; // sfix106_En11
|
||||
wire signed [105:0] add_cast_1; // sfix106_En11
|
||||
wire signed [106:0] add_temp; // sfix107_En11
|
||||
// -- Section 2 Signals
|
||||
wire signed [105:0] section_in2; // sfix106_En11
|
||||
wire signed [105:0] sum2; // sfix106_En11
|
||||
reg signed [105:0] section_out2; // sfix106_En11
|
||||
wire signed [105:0] add_cast_2; // sfix106_En11
|
||||
wire signed [105:0] add_cast_3; // sfix106_En11
|
||||
wire signed [106:0] add_temp_1; // sfix107_En11
|
||||
// -- Section 3 Signals
|
||||
wire signed [105:0] section_in3; // sfix106_En11
|
||||
wire signed [105:0] sum3; // sfix106_En11
|
||||
reg signed [105:0] section_out3; // sfix106_En11
|
||||
wire signed [105:0] add_cast_4; // sfix106_En11
|
||||
wire signed [105:0] add_cast_5; // sfix106_En11
|
||||
wire signed [106:0] add_temp_2; // sfix107_En11
|
||||
// -- Section 4 Signals
|
||||
wire signed [105:0] section_in4; // sfix106_En11
|
||||
wire signed [105:0] sum4; // sfix106_En11
|
||||
reg signed [105:0] section_out4; // sfix106_En11
|
||||
wire signed [105:0] add_cast_6; // sfix106_En11
|
||||
wire signed [105:0] add_cast_7; // sfix106_En11
|
||||
wire signed [106:0] add_temp_3; // sfix107_En11
|
||||
// -- Section 5 Signals
|
||||
wire signed [105:0] section_in5; // sfix106_En11
|
||||
wire signed [105:0] sum5; // sfix106_En11
|
||||
reg signed [105:0] section_out5; // sfix106_En11
|
||||
wire signed [105:0] add_cast_8; // sfix106_En11
|
||||
wire signed [105:0] add_cast_9; // sfix106_En11
|
||||
wire signed [106:0] add_temp_4; // sfix107_En11
|
||||
// -- Section 6 Signals
|
||||
wire signed [105:0] section_in6; // sfix106_En11
|
||||
wire signed [105:0] sum6; // sfix106_En11
|
||||
reg signed [105:0] section_out6; // sfix106_En11
|
||||
wire signed [105:0] add_cast_10; // sfix106_En11
|
||||
wire signed [105:0] add_cast_11; // sfix106_En11
|
||||
wire signed [106:0] add_temp_5; // sfix107_En11
|
||||
// -- Section 7 Signals
|
||||
wire signed [105:0] section_in7; // sfix106_En11
|
||||
reg signed [105:0] diff1; // sfix106_En11
|
||||
wire signed [105:0] section_out7; // sfix106_En11
|
||||
wire signed [105:0] sub_cast; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_1; // sfix106_En11
|
||||
wire signed [106:0] sub_temp; // sfix107_En11
|
||||
reg signed [105:0] cic_pipeline7; // sfix106_En11
|
||||
// -- Section 8 Signals
|
||||
wire signed [105:0] section_in8; // sfix106_En11
|
||||
reg signed [105:0] diff2; // sfix106_En11
|
||||
wire signed [105:0] section_out8; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_2; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_3; // sfix106_En11
|
||||
wire signed [106:0] sub_temp_1; // sfix107_En11
|
||||
reg signed [105:0] cic_pipeline8; // sfix106_En11
|
||||
// -- Section 9 Signals
|
||||
wire signed [105:0] section_in9; // sfix106_En11
|
||||
reg signed [105:0] diff3; // sfix106_En11
|
||||
wire signed [105:0] section_out9; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_4; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_5; // sfix106_En11
|
||||
wire signed [106:0] sub_temp_2; // sfix107_En11
|
||||
reg signed [105:0] cic_pipeline9; // sfix106_En11
|
||||
// -- Section 10 Signals
|
||||
wire signed [105:0] section_in10; // sfix106_En11
|
||||
reg signed [105:0] diff4; // sfix106_En11
|
||||
wire signed [105:0] section_out10; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_6; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_7; // sfix106_En11
|
||||
wire signed [106:0] sub_temp_3; // sfix107_En11
|
||||
reg signed [105:0] cic_pipeline10; // sfix106_En11
|
||||
// -- Section 11 Signals
|
||||
wire signed [105:0] section_in11; // sfix106_En11
|
||||
reg signed [105:0] diff5; // sfix106_En11
|
||||
wire signed [105:0] section_out11; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_8; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_9; // sfix106_En11
|
||||
wire signed [106:0] sub_temp_4; // sfix107_En11
|
||||
reg signed [105:0] cic_pipeline11; // sfix106_En11
|
||||
// -- Section 12 Signals
|
||||
wire signed [105:0] section_in12; // sfix106_En11
|
||||
reg signed [105:0] diff6; // sfix106_En11
|
||||
wire signed [105:0] section_out12; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_10; // sfix106_En11
|
||||
wire signed [105:0] sub_cast_11; // sfix106_En11
|
||||
wire signed [106:0] sub_temp_5; // sfix107_En11
|
||||
reg [6:0] bitgain; // ufix7
|
||||
wire signed [105:0] output_typeconvert; // sfix106_En11
|
||||
wire signed [105:0] muxinput_14; // sfix106_E3
|
||||
wire signed [105:0] muxinput_34; // sfix106_E23
|
||||
wire signed [105:0] muxinput_54; // sfix106_E43
|
||||
wire signed [105:0] muxinput_74; // sfix106_E63
|
||||
wire signed [105:0] muxinput_94; // sfix106_E83
|
||||
//
|
||||
reg signed [105:0] output_register; // sfix106_En11
|
||||
|
||||
// Block Statements
|
||||
// ------------------ CE Output Generation ------------------
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_output
|
||||
if (reset == 1'b1) begin
|
||||
cur_count <= 16'b0000000000000000;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
if (load_rate == 1'b1) begin
|
||||
cur_count <= 16'b0000000000000001;
|
||||
end
|
||||
else if (cur_count == rate_register - 1) begin
|
||||
cur_count <= 16'b0000000000000000;
|
||||
end
|
||||
else begin
|
||||
cur_count <= cur_count + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
end // ce_output
|
||||
|
||||
assign phase_1 = (cur_count == 16'b0000000000000001 && clk_enable == 1'b1)? 1 : 0;
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_delay
|
||||
if (reset == 1'b1) begin
|
||||
int_delay_pipe[0] <= 1'b0;
|
||||
int_delay_pipe[1] <= 1'b0;
|
||||
int_delay_pipe[2] <= 1'b0;
|
||||
int_delay_pipe[3] <= 1'b0;
|
||||
int_delay_pipe[4] <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
int_delay_pipe[1] <= int_delay_pipe[0];
|
||||
int_delay_pipe[2] <= int_delay_pipe[1];
|
||||
int_delay_pipe[3] <= int_delay_pipe[2];
|
||||
int_delay_pipe[4] <= int_delay_pipe[3];
|
||||
int_delay_pipe[0] <= clk_enable;
|
||||
end
|
||||
end
|
||||
end // ce_delay
|
||||
assign ce_delayline = int_delay_pipe[4];
|
||||
|
||||
assign ce_gated = ce_delayline & phase_1;
|
||||
|
||||
// ------------------ CE Output Register ------------------
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_output_register
|
||||
if (reset == 1'b1) begin
|
||||
ce_out_reg <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
ce_out_reg <= ce_gated;
|
||||
end
|
||||
end // ce_output_register
|
||||
|
||||
// ------------------ Input Register ------------------
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: input_reg_process
|
||||
if (reset == 1'b1) begin
|
||||
input_register <= 0;
|
||||
rate_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
input_register <= filter_in;
|
||||
rate_register <= rate;
|
||||
end
|
||||
end
|
||||
end // input_reg_process
|
||||
|
||||
// ------------------ Section # 1 : Integrator ------------------
|
||||
|
||||
assign section_in1 = input_register;
|
||||
|
||||
assign section_cast1 = $signed({{94{section_in1[11]}}, section_in1});
|
||||
|
||||
assign add_cast = section_cast1;
|
||||
assign add_cast_1 = section_out1;
|
||||
assign add_temp = add_cast + add_cast_1;
|
||||
assign sum1 = add_temp[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section1
|
||||
if (reset == 1'b1) begin
|
||||
section_out1 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out1 <= sum1;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section1
|
||||
|
||||
// ------------------ Section # 2 : Integrator ------------------
|
||||
|
||||
assign section_in2 = section_out1;
|
||||
|
||||
assign add_cast_2 = section_in2;
|
||||
assign add_cast_3 = section_out2;
|
||||
assign add_temp_1 = add_cast_2 + add_cast_3;
|
||||
assign sum2 = add_temp_1[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section2
|
||||
if (reset == 1'b1) begin
|
||||
section_out2 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out2 <= sum2;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section2
|
||||
|
||||
// ------------------ Section # 3 : Integrator ------------------
|
||||
|
||||
assign section_in3 = section_out2;
|
||||
|
||||
assign add_cast_4 = section_in3;
|
||||
assign add_cast_5 = section_out3;
|
||||
assign add_temp_2 = add_cast_4 + add_cast_5;
|
||||
assign sum3 = add_temp_2[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section3
|
||||
if (reset == 1'b1) begin
|
||||
section_out3 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out3 <= sum3;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section3
|
||||
|
||||
// ------------------ Section # 4 : Integrator ------------------
|
||||
|
||||
assign section_in4 = section_out3;
|
||||
|
||||
assign add_cast_6 = section_in4;
|
||||
assign add_cast_7 = section_out4;
|
||||
assign add_temp_3 = add_cast_6 + add_cast_7;
|
||||
assign sum4 = add_temp_3[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section4
|
||||
if (reset == 1'b1) begin
|
||||
section_out4 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out4 <= sum4;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section4
|
||||
|
||||
// ------------------ Section # 5 : Integrator ------------------
|
||||
|
||||
assign section_in5 = section_out4;
|
||||
|
||||
assign add_cast_8 = section_in5;
|
||||
assign add_cast_9 = section_out5;
|
||||
assign add_temp_4 = add_cast_8 + add_cast_9;
|
||||
assign sum5 = add_temp_4[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section5
|
||||
if (reset == 1'b1) begin
|
||||
section_out5 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out5 <= sum5;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section5
|
||||
|
||||
// ------------------ Section # 6 : Integrator ------------------
|
||||
|
||||
assign section_in6 = section_out5;
|
||||
|
||||
assign add_cast_10 = section_in6;
|
||||
assign add_cast_11 = section_out6;
|
||||
assign add_temp_5 = add_cast_10 + add_cast_11;
|
||||
assign sum6 = add_temp_5[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: integrator_delay_section6
|
||||
if (reset == 1'b1) begin
|
||||
section_out6 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
section_out6 <= sum6;
|
||||
end
|
||||
end
|
||||
end // integrator_delay_section6
|
||||
|
||||
// ------------------ Section # 7 : Comb ------------------
|
||||
|
||||
assign section_in7 = section_out6;
|
||||
|
||||
assign sub_cast = section_in7;
|
||||
assign sub_cast_1 = diff1;
|
||||
assign sub_temp = sub_cast - sub_cast_1;
|
||||
assign section_out7 = sub_temp[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section7
|
||||
if (reset == 1'b1) begin
|
||||
diff1 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
diff1 <= section_in7;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section7
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section7
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline7 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
cic_pipeline7 <= section_out7;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section7
|
||||
|
||||
// ------------------ Section # 8 : Comb ------------------
|
||||
|
||||
assign section_in8 = cic_pipeline7;
|
||||
|
||||
assign sub_cast_2 = section_in8;
|
||||
assign sub_cast_3 = diff2;
|
||||
assign sub_temp_1 = sub_cast_2 - sub_cast_3;
|
||||
assign section_out8 = sub_temp_1[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section8
|
||||
if (reset == 1'b1) begin
|
||||
diff2 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
diff2 <= section_in8;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section8
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section8
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline8 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
cic_pipeline8 <= section_out8;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section8
|
||||
|
||||
// ------------------ Section # 9 : Comb ------------------
|
||||
|
||||
assign section_in9 = cic_pipeline8;
|
||||
|
||||
assign sub_cast_4 = section_in9;
|
||||
assign sub_cast_5 = diff3;
|
||||
assign sub_temp_2 = sub_cast_4 - sub_cast_5;
|
||||
assign section_out9 = sub_temp_2[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section9
|
||||
if (reset == 1'b1) begin
|
||||
diff3 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
diff3 <= section_in9;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section9
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section9
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline9 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
cic_pipeline9 <= section_out9;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section9
|
||||
|
||||
// ------------------ Section # 10 : Comb ------------------
|
||||
|
||||
assign section_in10 = cic_pipeline9;
|
||||
|
||||
assign sub_cast_6 = section_in10;
|
||||
assign sub_cast_7 = diff4;
|
||||
assign sub_temp_3 = sub_cast_6 - sub_cast_7;
|
||||
assign section_out10 = sub_temp_3[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section10
|
||||
if (reset == 1'b1) begin
|
||||
diff4 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
diff4 <= section_in10;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section10
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section10
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline10 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
cic_pipeline10 <= section_out10;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section10
|
||||
|
||||
// ------------------ Section # 11 : Comb ------------------
|
||||
|
||||
assign section_in11 = cic_pipeline10;
|
||||
|
||||
assign sub_cast_8 = section_in11;
|
||||
assign sub_cast_9 = diff5;
|
||||
assign sub_temp_4 = sub_cast_8 - sub_cast_9;
|
||||
assign section_out11 = sub_temp_4[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section11
|
||||
if (reset == 1'b1) begin
|
||||
diff5 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
diff5 <= section_in11;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section11
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: cic_pipeline_process_section11
|
||||
if (reset == 1'b1) begin
|
||||
cic_pipeline11 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
cic_pipeline11 <= section_out11;
|
||||
end
|
||||
end
|
||||
end // cic_pipeline_process_section11
|
||||
|
||||
// ------------------ Section # 12 : Comb ------------------
|
||||
|
||||
assign section_in12 = cic_pipeline11;
|
||||
|
||||
assign sub_cast_10 = section_in12;
|
||||
assign sub_cast_11 = diff6;
|
||||
assign sub_temp_5 = sub_cast_10 - sub_cast_11;
|
||||
assign section_out12 = sub_temp_5[105:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: comb_delay_section12
|
||||
if (reset == 1'b1) begin
|
||||
diff6 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
diff6 <= section_in12;
|
||||
end
|
||||
end
|
||||
end // comb_delay_section12
|
||||
|
||||
always @(rate_register)
|
||||
begin
|
||||
case(rate_register)
|
||||
16'b0000000000000101 : bitgain = 7'b0001110;
|
||||
16'b0000000000110010 : bitgain = 7'b0100010;
|
||||
16'b0000000111110100 : bitgain = 7'b0110110;
|
||||
16'b0001001110001000 : bitgain = 7'b1001010;
|
||||
default : bitgain = 7'b1011110;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign muxinput_14 = $signed({{14{section_out12[105]}}, section_out12[105:14]});
|
||||
|
||||
assign muxinput_34 = $signed({{34{section_out12[105]}}, section_out12[105:34]});
|
||||
|
||||
assign muxinput_54 = $signed({{54{section_out12[105]}}, section_out12[105:54]});
|
||||
|
||||
assign muxinput_74 = $signed({{74{section_out12[105]}}, section_out12[105:74]});
|
||||
|
||||
assign muxinput_94 = $signed({{94{section_out12[105]}}, section_out12[105:94]});
|
||||
|
||||
assign output_typeconvert = (bitgain == 7'b0001110) ? muxinput_14 :
|
||||
(bitgain == 7'b0100010) ? muxinput_34 :
|
||||
(bitgain == 7'b0110110) ? muxinput_54 :
|
||||
(bitgain == 7'b1001010) ? muxinput_74 :
|
||||
muxinput_94;
|
||||
// ------------------ Output Register ------------------
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: output_reg_process
|
||||
if (reset == 1'b1) begin
|
||||
output_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
output_register <= output_typeconvert;
|
||||
end
|
||||
end
|
||||
end // output_reg_process
|
||||
|
||||
// Assignment Statements
|
||||
assign ce_out = ce_out_reg;
|
||||
assign filter_out = output_register;
|
||||
endmodule // cic_decim
|
||||
|
|
@ -0,0 +1,331 @@
|
|||
// -------------------------------------------------------------
|
||||
//
|
||||
// Module: fir_decim
|
||||
// Generated by MATLAB(R) 9.0 and the Filter Design HDL Coder 3.0.
|
||||
// Generated on: 2016-07-05 15:45:22
|
||||
// -------------------------------------------------------------
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Code Generation Options:
|
||||
//
|
||||
// FIRAdderStyle: tree
|
||||
// OptimizeForHDL: on
|
||||
// EDAScriptGeneration: off
|
||||
// AddPipelineRegisters: on
|
||||
// Name: fir_decim
|
||||
// TargetLanguage: Verilog
|
||||
// TestBenchName: fo_copy_tb
|
||||
// TestBenchStimulus: step ramp chirp noise
|
||||
// GenerateHDLTestBench: off
|
||||
|
||||
// -------------------------------------------------------------
|
||||
// HDL Implementation : Fully parallel
|
||||
// Multipliers : 6
|
||||
// Folding Factor : 1
|
||||
// -------------------------------------------------------------
|
||||
// Filter Settings:
|
||||
//
|
||||
// Discrete-Time FIR Multirate Filter (real)
|
||||
// -----------------------------------------
|
||||
// Filter Structure : Direct-Form FIR Polyphase Decimator
|
||||
// Decimation Factor : 2
|
||||
// Polyphase Length : 3
|
||||
// Filter Length : 6
|
||||
// Stable : Yes
|
||||
// Linear Phase : Yes (Type 2)
|
||||
//
|
||||
// Arithmetic : fixed
|
||||
// Numerator : s12,11 -> [-1 1)
|
||||
// -------------------------------------------------------------
|
||||
|
||||
`timescale 1 ns / 1 ns
|
||||
|
||||
module fir_decim
|
||||
(
|
||||
clk,
|
||||
clk_enable,
|
||||
reset,
|
||||
filter_in,
|
||||
filter_out,
|
||||
ce_out
|
||||
);
|
||||
|
||||
input clk;
|
||||
input clk_enable;
|
||||
input reset;
|
||||
input signed [11:0] filter_in; //sfix12_En11
|
||||
output signed [25:0] filter_out; //sfix26_En22
|
||||
output ce_out;
|
||||
|
||||
////////////////////////////////////////////////////////////////
|
||||
//Module Architecture: fir_decim
|
||||
////////////////////////////////////////////////////////////////
|
||||
// Local Functions
|
||||
// Type Definitions
|
||||
// Constants
|
||||
parameter signed [11:0] coeffphase1_1 = 12'b000011010101; //sfix12_En11
|
||||
parameter signed [11:0] coeffphase1_2 = 12'b011011110010; //sfix12_En11
|
||||
parameter signed [11:0] coeffphase1_3 = 12'b110000111110; //sfix12_En11
|
||||
parameter signed [11:0] coeffphase2_1 = 12'b110000111110; //sfix12_En11
|
||||
parameter signed [11:0] coeffphase2_2 = 12'b011011110010; //sfix12_En11
|
||||
parameter signed [11:0] coeffphase2_3 = 12'b000011010101; //sfix12_En11
|
||||
|
||||
// Signals
|
||||
reg [1:0] ring_count; // ufix2
|
||||
wire phase_0; // boolean
|
||||
wire phase_1; // boolean
|
||||
reg ce_out_reg; // boolean
|
||||
reg signed [11:0] input_register; // sfix12_En11
|
||||
reg signed [11:0] input_pipeline_phase0 [0:1] ; // sfix12_En11
|
||||
reg signed [11:0] input_pipeline_phase1 [0:2] ; // sfix12_En11
|
||||
wire signed [23:0] product_phase0_1; // sfix24_En22
|
||||
wire signed [23:0] product_phase0_2; // sfix24_En22
|
||||
wire signed [23:0] product_phase0_3; // sfix24_En22
|
||||
wire signed [23:0] product_phase1_1; // sfix24_En22
|
||||
wire signed [23:0] product_phase1_2; // sfix24_En22
|
||||
wire signed [23:0] product_phase1_3; // sfix24_En22
|
||||
reg signed [23:0] product_pipeline_phase0_1; // sfix24_En22
|
||||
reg signed [23:0] product_pipeline_phase0_2; // sfix24_En22
|
||||
reg signed [23:0] product_pipeline_phase0_3; // sfix24_En22
|
||||
reg signed [23:0] product_pipeline_phase1_1; // sfix24_En22
|
||||
reg signed [23:0] product_pipeline_phase1_2; // sfix24_En22
|
||||
reg signed [23:0] product_pipeline_phase1_3; // sfix24_En22
|
||||
wire signed [25:0] sumvector1 [0:2] ; // sfix26_En22
|
||||
wire signed [23:0] add_signext; // sfix24_En22
|
||||
wire signed [23:0] add_signext_1; // sfix24_En22
|
||||
wire signed [24:0] add_temp; // sfix25_En22
|
||||
wire signed [23:0] add_signext_2; // sfix24_En22
|
||||
wire signed [23:0] add_signext_3; // sfix24_En22
|
||||
wire signed [24:0] add_temp_1; // sfix25_En22
|
||||
wire signed [23:0] add_signext_4; // sfix24_En22
|
||||
wire signed [23:0] add_signext_5; // sfix24_En22
|
||||
wire signed [24:0] add_temp_2; // sfix25_En22
|
||||
reg signed [25:0] sumdelay_pipeline1 [0:2] ; // sfix26_En22
|
||||
wire signed [25:0] sumvector2 [0:1] ; // sfix26_En22
|
||||
wire signed [25:0] add_signext_6; // sfix26_En22
|
||||
wire signed [25:0] add_signext_7; // sfix26_En22
|
||||
wire signed [26:0] add_temp_3; // sfix27_En22
|
||||
reg signed [25:0] sumdelay_pipeline2 [0:1] ; // sfix26_En22
|
||||
wire signed [25:0] sum3; // sfix26_En22
|
||||
wire signed [25:0] add_signext_8; // sfix26_En22
|
||||
wire signed [25:0] add_signext_9; // sfix26_En22
|
||||
wire signed [26:0] add_temp_4; // sfix27_En22
|
||||
reg ce_delayline1; // boolean
|
||||
reg ce_delayline2; // boolean
|
||||
reg ce_delayline3; // boolean
|
||||
reg ce_delayline4; // boolean
|
||||
reg ce_delayline5; // boolean
|
||||
reg ce_delayline6; // boolean
|
||||
reg ce_delayline7; // boolean
|
||||
reg ce_delayline8; // boolean
|
||||
wire ce_gated; // boolean
|
||||
reg signed [25:0] output_register; // sfix26_En22
|
||||
|
||||
// Block Statements
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_output
|
||||
if (reset == 1'b1) begin
|
||||
ring_count <= 1;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
ring_count <= {ring_count[0], ring_count[1]};
|
||||
end
|
||||
end
|
||||
end // ce_output
|
||||
|
||||
assign phase_0 = ring_count[0] && clk_enable;
|
||||
|
||||
assign phase_1 = ring_count[1] && clk_enable;
|
||||
|
||||
// ------------------ CE Output Register ------------------
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_output_register
|
||||
if (reset == 1'b1) begin
|
||||
ce_out_reg <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
ce_out_reg <= phase_1;
|
||||
end
|
||||
end // ce_output_register
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: input_reg_process
|
||||
if (reset == 1'b1) begin
|
||||
input_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
input_register <= filter_in;
|
||||
end
|
||||
end
|
||||
end // input_reg_process
|
||||
|
||||
always @( posedge clk or posedge reset)
|
||||
begin: Delay_Pipeline_Phase0_process
|
||||
if (reset == 1'b1) begin
|
||||
input_pipeline_phase0[0] <= 0;
|
||||
input_pipeline_phase0[1] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
input_pipeline_phase0[0] <= input_register;
|
||||
input_pipeline_phase0[1] <= input_pipeline_phase0[0];
|
||||
end
|
||||
end
|
||||
end // Delay_Pipeline_Phase0_process
|
||||
|
||||
|
||||
always @( posedge clk or posedge reset)
|
||||
begin: Delay_Pipeline_Phase1_process
|
||||
if (reset == 1'b1) begin
|
||||
input_pipeline_phase1[0] <= 0;
|
||||
input_pipeline_phase1[1] <= 0;
|
||||
input_pipeline_phase1[2] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_0 == 1'b1) begin
|
||||
input_pipeline_phase1[0] <= input_register;
|
||||
input_pipeline_phase1[1] <= input_pipeline_phase1[0];
|
||||
input_pipeline_phase1[2] <= input_pipeline_phase1[1];
|
||||
end
|
||||
end
|
||||
end // Delay_Pipeline_Phase1_process
|
||||
|
||||
|
||||
assign product_phase0_1 = input_register * coeffphase1_1;
|
||||
|
||||
assign product_phase0_2 = input_pipeline_phase0[0] * coeffphase1_2;
|
||||
|
||||
assign product_phase0_3 = input_pipeline_phase0[1] * coeffphase1_3;
|
||||
|
||||
assign product_phase1_1 = input_pipeline_phase1[0] * coeffphase2_1;
|
||||
|
||||
assign product_phase1_2 = input_pipeline_phase1[1] * coeffphase2_2;
|
||||
|
||||
assign product_phase1_3 = input_pipeline_phase1[2] * coeffphase2_3;
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: product_pipeline_process1
|
||||
if (reset == 1'b1) begin
|
||||
product_pipeline_phase0_1 <= 0;
|
||||
product_pipeline_phase1_1 <= 0;
|
||||
product_pipeline_phase0_2 <= 0;
|
||||
product_pipeline_phase1_2 <= 0;
|
||||
product_pipeline_phase0_3 <= 0;
|
||||
product_pipeline_phase1_3 <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
product_pipeline_phase0_1 <= product_phase0_1;
|
||||
product_pipeline_phase1_1 <= product_phase1_1;
|
||||
product_pipeline_phase0_2 <= product_phase0_2;
|
||||
product_pipeline_phase1_2 <= product_phase1_2;
|
||||
product_pipeline_phase0_3 <= product_phase0_3;
|
||||
product_pipeline_phase1_3 <= product_phase1_3;
|
||||
end
|
||||
end
|
||||
end // product_pipeline_process1
|
||||
|
||||
assign add_signext = product_pipeline_phase1_1;
|
||||
assign add_signext_1 = product_pipeline_phase1_2;
|
||||
assign add_temp = add_signext + add_signext_1;
|
||||
assign sumvector1[0] = $signed({{1{add_temp[24]}}, add_temp});
|
||||
|
||||
assign add_signext_2 = product_pipeline_phase1_3;
|
||||
assign add_signext_3 = product_pipeline_phase0_1;
|
||||
assign add_temp_1 = add_signext_2 + add_signext_3;
|
||||
assign sumvector1[1] = $signed({{1{add_temp_1[24]}}, add_temp_1});
|
||||
|
||||
assign add_signext_4 = product_pipeline_phase0_2;
|
||||
assign add_signext_5 = product_pipeline_phase0_3;
|
||||
assign add_temp_2 = add_signext_4 + add_signext_5;
|
||||
assign sumvector1[2] = $signed({{1{add_temp_2[24]}}, add_temp_2});
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: sumdelay_pipeline_process1
|
||||
if (reset == 1'b1) begin
|
||||
sumdelay_pipeline1[0] <= 0;
|
||||
sumdelay_pipeline1[1] <= 0;
|
||||
sumdelay_pipeline1[2] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
sumdelay_pipeline1[0] <= sumvector1[0];
|
||||
sumdelay_pipeline1[1] <= sumvector1[1];
|
||||
sumdelay_pipeline1[2] <= sumvector1[2];
|
||||
end
|
||||
end
|
||||
end // sumdelay_pipeline_process1
|
||||
|
||||
assign add_signext_6 = sumdelay_pipeline1[0];
|
||||
assign add_signext_7 = sumdelay_pipeline1[1];
|
||||
assign add_temp_3 = add_signext_6 + add_signext_7;
|
||||
assign sumvector2[0] = add_temp_3[25:0];
|
||||
|
||||
assign sumvector2[1] = sumdelay_pipeline1[2];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: sumdelay_pipeline_process2
|
||||
if (reset == 1'b1) begin
|
||||
sumdelay_pipeline2[0] <= 0;
|
||||
sumdelay_pipeline2[1] <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
sumdelay_pipeline2[0] <= sumvector2[0];
|
||||
sumdelay_pipeline2[1] <= sumvector2[1];
|
||||
end
|
||||
end
|
||||
end // sumdelay_pipeline_process2
|
||||
|
||||
assign add_signext_8 = sumdelay_pipeline2[0];
|
||||
assign add_signext_9 = sumdelay_pipeline2[1];
|
||||
assign add_temp_4 = add_signext_8 + add_signext_9;
|
||||
assign sum3 = add_temp_4[25:0];
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: ce_delay
|
||||
if (reset == 1'b1) begin
|
||||
ce_delayline1 <= 1'b0;
|
||||
ce_delayline2 <= 1'b0;
|
||||
ce_delayline3 <= 1'b0;
|
||||
ce_delayline4 <= 1'b0;
|
||||
ce_delayline5 <= 1'b0;
|
||||
ce_delayline6 <= 1'b0;
|
||||
ce_delayline7 <= 1'b0;
|
||||
ce_delayline8 <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
if (clk_enable == 1'b1) begin
|
||||
ce_delayline1 <= clk_enable;
|
||||
ce_delayline2 <= ce_delayline1;
|
||||
ce_delayline3 <= ce_delayline2;
|
||||
ce_delayline4 <= ce_delayline3;
|
||||
ce_delayline5 <= ce_delayline4;
|
||||
ce_delayline6 <= ce_delayline5;
|
||||
ce_delayline7 <= ce_delayline6;
|
||||
ce_delayline8 <= ce_delayline7;
|
||||
end
|
||||
end
|
||||
end // ce_delay
|
||||
|
||||
assign ce_gated = ce_delayline8 & ce_out_reg;
|
||||
|
||||
always @ (posedge clk or posedge reset)
|
||||
begin: output_register_process
|
||||
if (reset == 1'b1) begin
|
||||
output_register <= 0;
|
||||
end
|
||||
else begin
|
||||
if (phase_1 == 1'b1) begin
|
||||
output_register <= sum3;
|
||||
end
|
||||
end
|
||||
end // output_register_process
|
||||
|
||||
// Assignment Statements
|
||||
assign ce_out = ce_gated;
|
||||
assign filter_out = output_register;
|
||||
endmodule // fir_decim
|
||||
Loading…
Reference in New Issue