From 4a772265a9dfd031e36df5a6f6e8639c84dad61f Mon Sep 17 00:00:00 2001 From: "stefan.raus" Date: Thu, 25 Feb 2021 09:41:57 +0000 Subject: [PATCH] Update Quartus Prime version from 19.3.0 to 20.1.0 adi_project_intel.tcl: Change quartus version to 20.1.0. library: Set qsys version so that IP instances won't require a specific version. --- library/axi_ad9122/axi_ad9122_hw.tcl | 2 +- library/axi_ad9144/axi_ad9144_hw.tcl | 2 +- library/axi_ad9152/axi_ad9152_hw.tcl | 2 +- library/axi_ad9250/axi_ad9250_hw.tcl | 2 +- library/axi_ad9361/axi_ad9361_hw.tcl | 2 +- library/axi_ad9371/axi_ad9371_hw.tcl | 2 +- library/axi_ad9671/axi_ad9671_hw.tcl | 2 +- library/axi_ad9680/axi_ad9680_hw.tcl | 2 +- library/axi_ad9684/axi_ad9684_hw.tcl | 2 +- library/axi_adrv9001/axi_adrv9001_hw.tcl | 2 +- library/axi_adrv9009/axi_adrv9009_hw.tcl | 2 +- library/axi_dmac/axi_dmac_hw.tcl | 2 +- library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl | 2 +- .../axi_laser_driver/axi_laser_driver_hw.tcl | 2 +- library/axi_sysid/axi_sysid_hw.tcl | 2 +- .../intel/adi_jesd204/adi_jesd204_glue_hw.tcl | 2 +- library/intel/adi_jesd204/adi_jesd204_hw.tcl | 45 ++++++++----------- library/intel/avl_adxcfg/avl_adxcfg_hw.tcl | 2 +- library/intel/avl_adxcvr/avl_adxcvr_hw.tcl | 2 +- .../avl_adxcvr_octet_swap_hw.tcl | 2 +- library/intel/avl_adxphy/avl_adxphy_hw.tcl | 2 +- library/intel/avl_dacfifo/avl_dacfifo_hw.tcl | 2 +- library/intel/axi_adxcvr/axi_adxcvr_hw.tcl | 2 +- .../intel_mem_asym/intel_mem_asym_hw.tcl | 4 +- .../common/intel_serdes/intel_serdes_hw.tcl | 2 +- .../intel/jesd204_phy/jesd204_phy_glue_hw.tcl | 2 +- library/intel/jesd204_phy/jesd204_phy_hw.tcl | 18 +++----- .../ad_ip_jesd204_tpl_adc_hw.tcl | 2 +- .../ad_ip_jesd204_tpl_dac_hw.tcl | 2 +- .../axi_jesd204_rx/axi_jesd204_rx_hw.tcl | 2 +- .../axi_jesd204_tx/axi_jesd204_tx_hw.tcl | 2 +- library/jesd204/jesd204_rx/jesd204_rx_hw.tcl | 2 +- .../jesd204_soft_pcs_rx_hw.tcl | 2 +- .../jesd204_soft_pcs_tx_hw.tcl | 2 +- library/jesd204/jesd204_tx/jesd204_tx_hw.tcl | 2 +- .../axi_spi_engine/axi_spi_engine_hw.tcl | 2 +- .../spi_engine_execution_hw.tcl | 2 +- .../spi_engine_interconnect_hw.tcl | 2 +- .../spi_engine_offload_hw.tcl | 2 +- library/sysid_rom/sysid_rom_hw.tcl | 2 +- library/util_adcfifo/util_adcfifo_hw.tcl | 2 +- library/util_bsplit/util_bsplit_hw.tcl | 2 +- library/util_dacfifo/util_dacfifo_hw.tcl | 2 +- .../util_pack/util_cpack2/util_cpack2_hw.tcl | 2 +- .../util_pack/util_upack2/util_upack2_hw.tcl | 2 +- library/util_rfifo/util_rfifo_hw.tcl | 2 +- library/util_wfifo/util_wfifo_hw.tcl | 2 +- .../common/ad9081_fmca_ebz_qsys.tcl | 4 +- projects/common/intel/dacfifo_qsys.tcl | 2 +- projects/scripts/adi_project_intel.tcl | 2 +- 50 files changed, 76 insertions(+), 87 deletions(-) diff --git a/library/axi_ad9122/axi_ad9122_hw.tcl b/library/axi_ad9122/axi_ad9122_hw.tcl index 98eff2f29..019250c67 100644 --- a/library/axi_ad9122/axi_ad9122_hw.tcl +++ b/library/axi_ad9122/axi_ad9122_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl index cd1bcb4c9..92d9c026e 100644 --- a/library/axi_ad9144/axi_ad9144_hw.tcl +++ b/library/axi_ad9144/axi_ad9144_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl index cd60048d2..d877c0521 100644 --- a/library/axi_ad9152/axi_ad9152_hw.tcl +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_ad9250/axi_ad9250_hw.tcl b/library/axi_ad9250/axi_ad9250_hw.tcl index 21dee8eaa..cb504c242 100644 --- a/library/axi_ad9250/axi_ad9250_hw.tcl +++ b/library/axi_ad9250/axi_ad9250_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_ad9361/axi_ad9361_hw.tcl b/library/axi_ad9361/axi_ad9361_hw.tcl index 0e63176b9..c7f40236f 100644 --- a/library/axi_ad9361/axi_ad9361_hw.tcl +++ b/library/axi_ad9361/axi_ad9361_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_ad9371/axi_ad9371_hw.tcl b/library/axi_ad9371/axi_ad9371_hw.tcl index bd563a041..ac597832c 100644 --- a/library/axi_ad9371/axi_ad9371_hw.tcl +++ b/library/axi_ad9371/axi_ad9371_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_ad9671/axi_ad9671_hw.tcl b/library/axi_ad9671/axi_ad9671_hw.tcl index 464642f23..37705d50c 100644 --- a/library/axi_ad9671/axi_ad9671_hw.tcl +++ b/library/axi_ad9671/axi_ad9671_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_ad9680/axi_ad9680_hw.tcl b/library/axi_ad9680/axi_ad9680_hw.tcl index 26dbe0d7c..45faa58f7 100644 --- a/library/axi_ad9680/axi_ad9680_hw.tcl +++ b/library/axi_ad9680/axi_ad9680_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_ad9684/axi_ad9684_hw.tcl b/library/axi_ad9684/axi_ad9684_hw.tcl index 2ec3de19a..2d5136399 100644 --- a/library/axi_ad9684/axi_ad9684_hw.tcl +++ b/library/axi_ad9684/axi_ad9684_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_adrv9001/axi_adrv9001_hw.tcl b/library/axi_adrv9001/axi_adrv9001_hw.tcl index 2cfce09e3..3c3aa2348 100644 --- a/library/axi_adrv9001/axi_adrv9001_hw.tcl +++ b/library/axi_adrv9001/axi_adrv9001_hw.tcl @@ -1,4 +1,4 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_adrv9009/axi_adrv9009_hw.tcl b/library/axi_adrv9009/axi_adrv9009_hw.tcl index f2252ab96..545c39876 100644 --- a/library/axi_adrv9009/axi_adrv9009_hw.tcl +++ b/library/axi_adrv9009/axi_adrv9009_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_dmac/axi_dmac_hw.tcl b/library/axi_dmac/axi_dmac_hw.tcl index cd749e2d7..6e8b90b50 100644 --- a/library/axi_dmac/axi_dmac_hw.tcl +++ b/library/axi_dmac/axi_dmac_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl index f4f116f30..ddbdb0eb1 100644 --- a/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl +++ b/library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../scripts/adi_env.tcl diff --git a/library/axi_laser_driver/axi_laser_driver_hw.tcl b/library/axi_laser_driver/axi_laser_driver_hw.tcl index 2fefbe65b..1d083abe7 100644 --- a/library/axi_laser_driver/axi_laser_driver_hw.tcl +++ b/library/axi_laser_driver/axi_laser_driver_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/axi_sysid/axi_sysid_hw.tcl b/library/axi_sysid/axi_sysid_hw.tcl index a12441b17..8818c6eb3 100644 --- a/library/axi_sysid/axi_sysid_hw.tcl +++ b/library/axi_sysid/axi_sysid_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl index e2e8dd3c1..0d8664b98 100644 --- a/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl +++ b/library/intel/adi_jesd204/adi_jesd204_glue_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/intel/adi_jesd204/adi_jesd204_hw.tcl b/library/intel/adi_jesd204/adi_jesd204_hw.tcl index 0ba94f27c..8b1afb5de 100644 --- a/library/intel/adi_jesd204/adi_jesd204_hw.tcl +++ b/library/intel/adi_jesd204/adi_jesd204_hw.tcl @@ -42,12 +42,10 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl -set version 19.1 - # # Wrapper module that instantiates and connects all the components required to # for a JESD204 link. @@ -142,13 +140,12 @@ ad_ip_parameter TPL_DATA_PATH_WIDTH INTEGER 4 false { \ } proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} { - global version set device [get_parameter_value DEVICE_FAMILY] if {[string equal $device "Arria 10"]} { - add_instance phy_reset_control altera_xcvr_reset_control $version + add_instance phy_reset_control altera_xcvr_reset_control set_instance_property phy_reset_control SUPPRESS_ALL_WARNINGS true set_instance_parameter_value phy_reset_control {SYNCHRONIZE_RESET} {0} set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes @@ -177,7 +174,7 @@ proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} { } elseif {[string equal $device "Stratix 10"]} { - add_instance phy_reset_control altera_xcvr_reset_control_s10 $version + add_instance phy_reset_control altera_xcvr_reset_control_s10 set_instance_parameter_value phy_reset_control {CHANNELS} $num_of_lanes set_instance_parameter_value phy_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency set_instance_parameter_value phy_reset_control {TX_ENABLE} $tx @@ -212,12 +209,10 @@ proc create_phy_reset_control {tx num_of_lanes sysclk_frequency} { proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes bonding_clocks_en} { - global version - set device_family [get_parameter_value "DEVICE_FAMILY"] if {$device_family == "Arria 10"} { - add_instance lane_pll altera_xcvr_atx_pll_a10 $version + add_instance lane_pll altera_xcvr_atx_pll_a10 if {$num_lanes > 6} { set_instance_parameter_value lane_pll enable_mcgb {true} if {$bonding_clocks_en} { @@ -229,7 +224,7 @@ proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes set_instance_parameter_value lane_pll enable_hfreq_clk {true} } - add_instance glue adi_jesd204_glue 1.0 + add_instance glue adi_jesd204_glue add_connection phy_reset_control.pll_powerdown glue.in_pll_powerdown add_connection glue.out_pll_powerdown lane_pll.pll_powerdown add_connection glue.out_mcgb_rst lane_pll.mcgb_rst @@ -238,11 +233,11 @@ proc create_lane_pll {id tx_or_rx_n pllclk_frequency refclk_frequency num_lanes } set_instance_parameter_value lane_pll {enable_pll_reconfig} {1} } elseif {$device_family == "Stratix 10"} { - add_instance lane_pll altera_xcvr_atx_pll_s10_htile $version + add_instance lane_pll altera_xcvr_atx_pll_s10_htile set_instance_parameter_value lane_pll {rcfg_enable} {1} ## tie pll_select to GND - add_instance glue adi_jesd204_glue 1.0 + add_instance glue adi_jesd204_glue set_instance_parameter_value glue {IN_PLL_POWERDOWN_EN} {0} if {$tx_or_rx_n} { add_connection glue.out_pll_select_gnd phy_reset_control.pll_select @@ -338,8 +333,6 @@ proc jesd204_validate {{quiet false}} { proc jesd204_compose {} { - global version - set id [get_parameter_value "ID"] set lane_rate [get_parameter_value "LANE_RATE"] set tx_or_rx_n [get_parameter_value "TX_OR_RX_N"] @@ -366,7 +359,7 @@ proc jesd204_compose {} { return } - add_instance sys_clock clock_source 19.3 + add_instance sys_clock clock_source set_instance_parameter_value sys_clock {clockFrequency} [expr $sysclk_frequency*1000000] set_instance_parameter_value sys_clock {resetSynchronousEdges} {deassert} add_interface sys_clk clock sink @@ -374,7 +367,7 @@ proc jesd204_compose {} { add_interface sys_resetn reset sink set_interface_property sys_resetn EXPORT_OF sys_clock.clk_in_reset - add_instance ref_clock altera_clock_bridge $version + add_instance ref_clock altera_clock_bridge set_instance_parameter_value ref_clock {EXPLICIT_CLOCK_RATE} [expr $refclk_frequency*1000000] set_instance_parameter_value ref_clock {NUM_CLOCK_OUTPUTS} 2 add_interface ref_clk clock sink @@ -385,11 +378,11 @@ proc jesd204_compose {} { ## link clock configuration (also known as device clock, which will be used ## by the upper layers for the data path, it can come from the PCS or external) - add_instance link_clock altera_clock_bridge $version + add_instance link_clock altera_clock_bridge set_instance_parameter_value link_clock {EXPLICIT_CLOCK_RATE} [expr $linkclk_frequency*1000000] set_instance_parameter_value link_clock {NUM_CLOCK_OUTPUTS} 2 - add_instance link_reset altera_reset_bridge $version + add_instance link_reset altera_reset_bridge set_instance_parameter_value link_reset {NUM_RESET_OUTPUTS} 2 if {$dual_clk_mode} { @@ -416,7 +409,7 @@ proc jesd204_compose {} { if {$device_family == "Arria 10"} { - add_instance link_pll altera_xcvr_fpll_a10 $version + add_instance link_pll altera_xcvr_fpll_a10 set_instance_parameter_value link_pll {gui_fpll_mode} {0} set_instance_parameter_value link_pll {gui_reference_clock_frequency} $refclk_frequency set_instance_parameter_value link_pll {gui_number_of_output_clocks} 2 @@ -428,7 +421,7 @@ proc jesd204_compose {} { set outclk_name "outclk0" - add_instance link_pll_reset_control altera_xcvr_reset_control $version + add_instance link_pll_reset_control altera_xcvr_reset_control set_instance_parameter_value link_pll_reset_control {SYNCHRONIZE_RESET} {0} set_instance_parameter_value link_pll_reset_control {SYS_CLK_IN_MHZ} $sysclk_frequency set_instance_parameter_value link_pll_reset_control {TX_PLL_ENABLE} {1} @@ -443,7 +436,7 @@ proc jesd204_compose {} { } elseif {$device_family == "Stratix 10"} { send_message info "Instantiate a fpll_s10_htile for link_pll." - add_instance link_pll altera_xcvr_fpll_s10_htile 19.1.1 + add_instance link_pll altera_xcvr_fpll_s10_htile ## Primary Use is Core mode set_instance_parameter_value link_pll {set_primary_use} 0 ## Basic Mode @@ -479,7 +472,7 @@ proc jesd204_compose {} { add_connection sys_clock.clk_reset link_pll.reconfig_reset0 add_connection sys_clock.clk link_pll.reconfig_clk0 - add_instance axi_xcvr axi_adxcvr 1.0 + add_instance axi_xcvr axi_adxcvr set_instance_parameter_value axi_xcvr {ID} $id set_instance_parameter_value axi_xcvr {TX_OR_RX_N} $tx_or_rx_n set_instance_parameter_value axi_xcvr {NUM_OF_LANES} $num_of_lanes @@ -500,7 +493,7 @@ proc jesd204_compose {} { create_phy_reset_control $tx_or_rx_n $num_of_lanes $sysclk_frequency - add_instance phy jesd204_phy 1.0 + add_instance phy jesd204_phy set_instance_parameter_value phy ID $id set_instance_parameter_value phy DEVICE $device_family set_instance_parameter_value phy SOFT_PCS $soft_pcs @@ -519,7 +512,7 @@ proc jesd204_compose {} { ## connect the required device clock if {$ext_device_clk_en} { - add_instance ext_device_clock altera_clock_bridge $version + add_instance ext_device_clock altera_clock_bridge set_instance_parameter_value ext_device_clock {EXPLICIT_CLOCK_RATE} [expr $deviceclk_frequency*1000000] set_instance_parameter_value ext_device_clock {NUM_CLOCK_OUTPUTS} 2 add_interface device_clk clock sink @@ -556,13 +549,13 @@ proc jesd204_compose {} { add_connection ref_clock.out_clk phy.ref_clk } - add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} 1.0 + add_instance axi_jesd204_${tx_rx} axi_jesd204_${tx_rx} set_instance_parameter_value axi_jesd204_${tx_rx} {NUM_LANES} $num_of_lanes add_connection sys_clock.clk axi_jesd204_${tx_rx}.s_axi_clock add_connection sys_clock.clk_reset axi_jesd204_${tx_rx}.s_axi_reset - add_instance jesd204_${tx_rx} jesd204_${tx_rx} 1.0 + add_instance jesd204_${tx_rx} jesd204_${tx_rx} set_instance_parameter_value jesd204_${tx_rx} {NUM_LANES} $num_of_lanes set_instance_parameter_value jesd204_${tx_rx} {ASYNC_CLK} $dual_clk_mode set_instance_parameter_value jesd204_${tx_rx} {TPL_DATA_PATH_WIDTH} $tpl_data_path_width diff --git a/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl b/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl index 2e2117e4d..b15b99acd 100644 --- a/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl +++ b/library/intel/avl_adxcfg/avl_adxcfg_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 set_module_property NAME avl_adxcfg set_module_property DESCRIPTION "Avalon ADXCFG Core" diff --git a/library/intel/avl_adxcvr/avl_adxcvr_hw.tcl b/library/intel/avl_adxcvr/avl_adxcvr_hw.tcl index 9360ddade..58f3e2255 100644 --- a/library/intel/avl_adxcvr/avl_adxcvr_hw.tcl +++ b/library/intel/avl_adxcvr/avl_adxcvr_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl b/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl index 64b8495ae..30006ef6c 100644 --- a/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl +++ b/library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/intel/avl_adxphy/avl_adxphy_hw.tcl b/library/intel/avl_adxphy/avl_adxphy_hw.tcl index e8f6facfd..f0e44d2d4 100644 --- a/library/intel/avl_adxphy/avl_adxphy_hw.tcl +++ b/library/intel/avl_adxphy/avl_adxphy_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl b/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl index fec89b90d..d08423d4f 100644 --- a/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl +++ b/library/intel/avl_dacfifo/avl_dacfifo_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl b/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl index 6ed19fcbf..930752b0d 100644 --- a/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl +++ b/library/intel/axi_adxcvr/axi_adxcvr_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 package require quartus::device source ../../scripts/adi_env.tcl diff --git a/library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl b/library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl index acd5babb5..9d3ec3cd2 100644 --- a/library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl +++ b/library/intel/common/intel_mem_asym/intel_mem_asym_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl @@ -29,7 +29,7 @@ proc p_intel_mem_asym {} { set m_size [expr ((2**$m_addr_width_b)*$m_data_width_b)] } - add_instance intel_mem ram_2port 1.0 + add_instance intel_mem ram_2port set_instance_parameter_value intel_mem {GUI_MODE} 0 set_instance_parameter_value intel_mem {GUI_MEM_IN_BITS} 1 set_instance_parameter_value intel_mem {GUI_MEMSIZE_BITS} $m_size diff --git a/library/intel/common/intel_serdes/intel_serdes_hw.tcl b/library/intel/common/intel_serdes/intel_serdes_hw.tcl index 7a1d9791c..3e66a5a32 100644 --- a/library/intel/common/intel_serdes/intel_serdes_hw.tcl +++ b/library/intel/common/intel_serdes/intel_serdes_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl index 9b569351f..3dbcd835a 100644 --- a/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl +++ b/library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/intel/jesd204_phy/jesd204_phy_hw.tcl b/library/intel/jesd204_phy/jesd204_phy_hw.tcl index 2ba6f3023..dc01cd703 100644 --- a/library/intel/jesd204_phy/jesd204_phy_hw.tcl +++ b/library/intel/jesd204_phy/jesd204_phy_hw.tcl @@ -42,13 +42,11 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl -set version 19.2 - # # Instantiates the Arria 10 native PHY and configures it for JESD204 operation. # The datapath width is configured for 4 octets per beat. @@ -76,8 +74,6 @@ ad_ip_parameter BONDING_CLOCKS_EN BOOLEAN false false proc jesd204_phy_composition_callback {} { - global version - set device [get_parameter_value "DEVICE"] set soft_pcs [get_parameter_value "SOFT_PCS"] set tx [get_parameter_value "TX_OR_RX_N"] @@ -99,7 +95,7 @@ proc jesd204_phy_composition_callback {} { set device_type 0 } - add_instance link_clock clock_source 19.3 + add_instance link_clock clock_source set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000] add_interface link_clk clock sink set_interface_property link_clk EXPORT_OF link_clock.clk_in @@ -108,14 +104,14 @@ proc jesd204_phy_composition_callback {} { ## Arria10 if {$device_type == 1} { - add_instance native_phy altera_xcvr_native_a10 19.1 + add_instance native_phy altera_xcvr_native_a10 set_instance_parameter_value native_phy {enh_txfifo_mode} "Phase compensation" set_instance_parameter_value native_phy {enh_rxfifo_mode} "Phase compensation" set_instance_property native_phy SUPPRESS_ALL_WARNINGS true set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true ## Stratix 10 } elseif {$device_type == 2} { - add_instance native_phy altera_xcvr_native_s10_htile $version + add_instance native_phy altera_xcvr_native_s10_htile set_instance_parameter_value native_phy {tx_fifo_mode} "Phase compensation" set_instance_parameter_value native_phy {rx_fifo_mode} "Phase compensation" ## Unsupported device @@ -178,7 +174,7 @@ proc jesd204_phy_composition_callback {} { set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1 set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0 - add_instance phy_glue jesd204_phy_glue 1.0 + add_instance phy_glue jesd204_phy_glue set_instance_parameter_value phy_glue DEVICE $device set_instance_parameter_value phy_glue TX_OR_RX_N $tx set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs @@ -279,7 +275,7 @@ proc jesd204_phy_composition_callback {} { if {$tx} { if {$soft_pcs} { - add_instance soft_pcs_${i} jesd204_soft_pcs_tx 1.0 + add_instance soft_pcs_${i} jesd204_soft_pcs_tx set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \ [expr ($lane_invert >> $i) & 1] add_connection link_clock.clk soft_pcs_${i}.clock @@ -292,7 +288,7 @@ proc jesd204_phy_composition_callback {} { } } else { if {$soft_pcs} { - add_instance soft_pcs_${i} jesd204_soft_pcs_rx 1.0 + add_instance soft_pcs_${i} jesd204_soft_pcs_rx set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \ [expr ($lane_invert >> $i) & 1] diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl index f1717225d..ee586d6f5 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl @@ -21,7 +21,7 @@ # *************************************************************************** # *************************************************************************** -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl index e9729046c..f29797ca8 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl @@ -21,7 +21,7 @@ # *************************************************************************** # *************************************************************************** -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl index 709aae53e..4aff8fbcf 100755 --- a/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl +++ b/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl index 0ba2faf44..64d1dee97 100644 --- a/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl +++ b/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl index 936408100..38d642522 100755 --- a/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl +++ b/library/jesd204/jesd204_rx/jesd204_rx_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl index bbaf8dd91..44b94f091 100644 --- a/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl +++ b/library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl index da4e63d98..24c10c44b 100644 --- a/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl +++ b/library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl index 1f180a21f..f059e9e8c 100644 --- a/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl +++ b/library/jesd204/jesd204_tx/jesd204_tx_hw.tcl @@ -42,7 +42,7 @@ # is copyright © 2016-2017, Analog Devices, Inc.” # -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl index 1eceaef7b..c4f39d68f 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl index eddbda455..02ff6b9c5 100644 --- a/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl +++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl index 13f69b838..1709f24c7 100644 --- a/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl +++ b/library/spi_engine/spi_engine_interconnect/spi_engine_interconnect_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl b/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl index 6320df72c..ef8f09af1 100644 --- a/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl +++ b/library/spi_engine/spi_engine_offload/spi_engine_offload_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/sysid_rom/sysid_rom_hw.tcl b/library/sysid_rom/sysid_rom_hw.tcl index 6631b5a31..26882b0d3 100644 --- a/library/sysid_rom/sysid_rom_hw.tcl +++ b/library/sysid_rom/sysid_rom_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/util_adcfifo/util_adcfifo_hw.tcl b/library/util_adcfifo/util_adcfifo_hw.tcl index d4a0cc697..fcbdfa946 100644 --- a/library/util_adcfifo/util_adcfifo_hw.tcl +++ b/library/util_adcfifo/util_adcfifo_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/util_bsplit/util_bsplit_hw.tcl b/library/util_bsplit/util_bsplit_hw.tcl index 33dfbb4ba..1d0815541 100644 --- a/library/util_bsplit/util_bsplit_hw.tcl +++ b/library/util_bsplit/util_bsplit_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/util_dacfifo/util_dacfifo_hw.tcl b/library/util_dacfifo/util_dacfifo_hw.tcl index e183804d0..edb2b2e97 100644 --- a/library/util_dacfifo/util_dacfifo_hw.tcl +++ b/library/util_dacfifo/util_dacfifo_hw.tcl @@ -1,5 +1,5 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/util_pack/util_cpack2/util_cpack2_hw.tcl b/library/util_pack/util_cpack2/util_cpack2_hw.tcl index d9ad009fc..132bda14f 100644 --- a/library/util_pack/util_cpack2/util_cpack2_hw.tcl +++ b/library/util_pack/util_cpack2/util_cpack2_hw.tcl @@ -21,7 +21,7 @@ # *************************************************************************** # *************************************************************************** -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/util_pack/util_upack2/util_upack2_hw.tcl b/library/util_pack/util_upack2/util_upack2_hw.tcl index a8535a262..364042d90 100644 --- a/library/util_pack/util_upack2/util_upack2_hw.tcl +++ b/library/util_pack/util_upack2/util_upack2_hw.tcl @@ -21,7 +21,7 @@ # *************************************************************************** # *************************************************************************** -package require qsys +package require qsys 14.0 source ../../scripts/adi_env.tcl source ../../scripts/adi_ip_intel.tcl diff --git a/library/util_rfifo/util_rfifo_hw.tcl b/library/util_rfifo/util_rfifo_hw.tcl index c238bf957..b2350ff37 100644 --- a/library/util_rfifo/util_rfifo_hw.tcl +++ b/library/util_rfifo/util_rfifo_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/library/util_wfifo/util_wfifo_hw.tcl b/library/util_wfifo/util_wfifo_hw.tcl index 913fdfc7f..877a0fd38 100644 --- a/library/util_wfifo/util_wfifo_hw.tcl +++ b/library/util_wfifo/util_wfifo_hw.tcl @@ -1,6 +1,6 @@ -package require qsys +package require qsys 14.0 source ../scripts/adi_env.tcl source ../scripts/adi_ip_intel.tcl diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl index e6e3de6ef..c05286df8 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl @@ -63,10 +63,10 @@ set dac_fifo_address_width [expr int(ceil(log(($dac_fifo_samples_per_converter*$ # JESD204B clock bridges -add_instance tx_device_clk altera_clock_bridge 19.1 +add_instance tx_device_clk altera_clock_bridge set_instance_parameter_value tx_device_clk {EXPLICIT_CLOCK_RATE} {250000000} -add_instance rx_device_clk altera_clock_bridge 19.1 +add_instance rx_device_clk altera_clock_bridge set_instance_parameter_value rx_device_clk {EXPLICIT_CLOCK_RATE} {250000000} # diff --git a/projects/common/intel/dacfifo_qsys.tcl b/projects/common/intel/dacfifo_qsys.tcl index e54dc96e9..742189b37 100644 --- a/projects/common/intel/dacfifo_qsys.tcl +++ b/projects/common/intel/dacfifo_qsys.tcl @@ -5,7 +5,7 @@ proc ad_dacfifo_create {dac_fifo_name dac_data_width dac_dma_data_width dac_fifo return -code error [format "ERROR: util_dacfifo dac/dma widths must be the same!"] } - add_instance $dac_fifo_name util_dacfifo 1.0 + add_instance $dac_fifo_name util_dacfifo set_instance_parameter_value $dac_fifo_name {ADDRESS_WIDTH} $dac_fifo_address_width set_instance_parameter_value $dac_fifo_name {DATA_WIDTH} $dac_data_width diff --git a/projects/scripts/adi_project_intel.tcl b/projects/scripts/adi_project_intel.tcl index 61df074c9..e689a8613 100644 --- a/projects/scripts/adi_project_intel.tcl +++ b/projects/scripts/adi_project_intel.tcl @@ -2,7 +2,7 @@ ## Initialize global variable set family "none" set device "none" -set version "19.3.0" +set version "20.1.0" ## Define the ADI_IGNORE_VERSION_CHECK environment variable to skip version check if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {