jesd204: axi_jesd204_{rx,tx}: Add external link domain reset

Currently the reset for the link clock domain is generated internally in
the axi_jesd204_{rx,tx} peripheral. The reset is controlled by through the
register map.

Add an additional external reset for link clock domain. The link clock
domain is kept in reset if either the internal reset or the external reset
is asserted.

This for example allows the fabric to keep the domain in reset if the clock
is not yet stable.

The status of the external reset can be queried from the register map.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

library/jesd204/axi_jesd204_common/jesd204_up_common.v

@@ -60,6 +60,7 @@ module jesd204_up_common # (
   output up_reset_synchronizer,
 
   input core_clk,
+  input core_reset_ext,
   output core_reset,
 
   input [11:0] up_raddr,
@@ -102,6 +103,15 @@ assign core_reset = core_reset_vector[0];
 reg [1:0] up_reset_synchronizer_vector = 2'b11;
 assign up_reset_synchronizer = up_reset_synchronizer_vector[0];
 
+/*
+ * Synchronize the external core reset to the register map domain so the status
+ * can be shown in the register map. This is useful for debugging.
+ */
+reg [1:0] up_core_reset_ext_synchronizer_vector = 2'b11;
+wire up_core_reset_ext;
+
+assign up_core_reset_ext = up_core_reset_ext_synchronizer_vector[0];
+
 /* Transfer two cycles before the core comes out of reset */
 wire core_cfg_transfer_en;
 assign core_cfg_transfer_en = core_reset_vector[2] ^ core_reset_vector[1];
@@ -118,19 +128,29 @@ always @(posedge up_clk or negedge ext_resetn) begin
   end
 end
 
-always @(posedge core_clk or posedge up_reset_core) begin
+wire core_reset_all = up_reset_core | core_reset_ext;
-  if (up_reset_core == 1'b1) begin
+
+always @(posedge core_clk or posedge core_reset_all) begin
+  if (core_reset_all == 1'b1) begin
     core_reset_vector <= 5'b11111;
   end else begin
     core_reset_vector <= {1'b0,core_reset_vector[4:1]};
   end
 end
 
-always @(posedge up_clk or posedge up_reset_core) begin
+always @(posedge up_clk or posedge core_reset) begin
-  if (up_reset_core == 1'b1) begin
+  if (core_reset == 1'b1) begin
     up_reset_synchronizer_vector <= 2'b11;
   end else begin
-    up_reset_synchronizer_vector <= {core_reset,up_reset_synchronizer_vector[1]};
+    up_reset_synchronizer_vector <= {1'b0,up_reset_synchronizer_vector[1]};
+  end
+end
+
+always @(posedge up_clk or posedge core_reset_ext) begin
+  if (core_reset_ext == 1'b1) begin
+    up_core_reset_ext_synchronizer_vector <= 2'b11;
+  end else begin
+    up_core_reset_ext_synchronizer_vector <= {1'b0,up_core_reset_ext_synchronizer_vector[1]};
   end
 end
 
@@ -199,7 +219,7 @@ always @(*) begin
 
   /* JESD common control */
   12'h030: up_rdata <= up_reset_core;
-  12'h031: up_rdata <= up_reset_synchronizer; /* core ready */
+  12'h031: up_rdata <= {up_core_reset_ext, up_reset_synchronizer}; /* core ready */
   12'h032: up_rdata <= {11'h00, clk_mon_count}; /* Make it 16.16 */
   /* 0x32-0x34 reserver for future use */
 

library/jesd204/axi_jesd204_rx/axi_jesd204_rx.v

@@ -72,6 +72,7 @@ module axi_jesd204_rx #(
   output irq,
 
   input core_clk,
+  input core_reset_ext,
   output core_reset,
 
   output [NUM_LANES-1:0] core_cfg_lanes_disable,
@@ -175,6 +176,7 @@ jesd204_up_common #(
   .up_reset_synchronizer(up_reset_synchronizer),
 
   .core_clk(core_clk),
+  .core_reset_ext(core_reset_ext),
   .core_reset(core_reset),
 
   .up_raddr(up_raddr),

library/jesd204/axi_jesd204_rx/axi_jesd204_rx_constr.xdc

@@ -53,7 +53,8 @@ set_property ASYNC_REG TRUE \
 set_property ASYNC_REG TRUE \
   [get_cells -hier {up_reset_vector_reg*}] \
   [get_cells -hier {core_reset_vector_reg*}] \
-  [get_cells -hier {up_reset_synchronizer_vector_reg*}]
+  [get_cells -hier {up_reset_synchronizer_vector_reg*}] \
+  [get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}]
 
 set_false_path \
   -from [get_pins {i_up_rx/i_cdc_status/in_toggle_d1_reg/C}] \
@@ -105,7 +106,10 @@ set_false_path \
 
 set_false_path \
   -from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \
-  -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[1]/D}]
+  -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}]
+
+set_false_path \
+  -to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
 
 set_max_delay -datapath_only \
   -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \

library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.tcl

@@ -117,4 +117,6 @@ adi_add_bus "rx_status" "slave" \
 adi_add_bus_clock "core_clk" "rx_status:rx_event:rx_ilas_config:rx_cfg" \
   "core_reset" "master"
 
+set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
+
 ipx::save_core [ipx::current_core]

library/jesd204/axi_jesd204_tx/axi_jesd204_tx.v

@@ -73,6 +73,7 @@ module axi_jesd204_tx #(
   output irq,
 
   input core_clk,
+  input core_reset_ext,
   output core_reset,
 
   output [NUM_LANES-1:0] core_cfg_lanes_disable,
@@ -183,6 +184,7 @@ jesd204_up_common #(
   .up_reset_synchronizer(),
 
   .core_clk(core_clk),
+  .core_reset_ext(core_reset_ext),
   .core_reset(core_reset),
 
   .up_raddr(up_raddr),

library/jesd204/axi_jesd204_tx/axi_jesd204_tx_constr.xdc

@@ -53,7 +53,8 @@ set_property ASYNC_REG TRUE \
 set_property ASYNC_REG TRUE \
   [get_cells -hier {up_reset_vector_reg*}] \
   [get_cells -hier {core_reset_vector_reg*}] \
-  [get_cells -hier {up_reset_synchronizer_vector_reg*}]
+  [get_cells -hier {up_reset_synchronizer_vector_reg*}] \
+  [get_cells -hier {up_core_reset_ext_synchronizer_vector_reg*}]
 
 set_false_path \
   -from [get_pins {i_up_tx/i_cdc_status/out_toggle_d1_reg/C}] \
@@ -91,7 +92,10 @@ set_false_path \
 
 set_false_path \
   -from [get_pins {i_up_common/core_reset_vector_reg[0]/C}] \
-  -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[1]/D}]
+  -to [get_pins {i_up_common/up_reset_synchronizer_vector_reg[*]/PRE}]
+
+set_false_path \
+  -to [get_pins {i_up_common/up_core_reset_ext_synchronizer_vector_reg[*]/PRE}]
 
 set_max_delay -datapath_only \
   -from [get_pins {i_up_common/up_cfg_*_reg*/C}] \

library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.tcl

@@ -122,4 +122,6 @@ adi_add_bus "tx_ctrl" "master" \
 adi_add_bus_clock "core_clk" "tx_status:tx_event:tx_ilas_config:tx_cfg:tx_ctrl" \
   "core_reset" "master"
 
+set_property DRIVER_VALUE "0" [ipx::get_ports "core_reset_ext"]
+
 ipx::save_core [ipx::current_core]

library/jesd204/tb/axi_jesd204_rx_regmap_tb.v

@@ -333,6 +333,7 @@ module axi_jesd204_rx_tb;
     .s_axi_rdata(s_axi_rdata),
 
     .core_clk(core_clk),
+    .core_reset_ext(1'b0),
 
     .core_ilas_config_valid({NUM_LANES{core_ilas_config_valid}}),
     .core_ilas_config_addr({NUM_LANES{core_ilas_config_addr}}),

library/jesd204/tb/axi_jesd204_tx_regmap_tb.v

@@ -340,6 +340,7 @@ module axi_jesd204_tx_tb;
     .s_axi_rdata(s_axi_rdata),
 
     .core_clk(core_clk),
+    .core_reset_ext(1'b0),
 
     .core_ilas_config_rd(1'b1),
     .core_ilas_config_addr(2'b00),