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Merge branch 'devel' of github.com:analogdevicesinc/hdl into devel

main
Rejeesh Kutty 2014-06-25 15:26:21 -04:00
parent 10a7804e14 92e525d573
commit 4afe6c24e9
9 changed files with 169 additions and 250 deletions
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159
library/axi_ad9250/axi_ad9250.v
View File

@ -50,9 +50,12 @@ module axi_ad9250 (
// dma interface
adc_clk,
adc_dwr,
adc_ddata,
adc_dsync,
adc_valid_a,
adc_enable_a,
adc_data_a,
adc_valid_b,
adc_enable_b,
adc_data_b,
adc_dovf,
adc_dunf,
@ -76,19 +79,14 @@ module axi_ad9250 (
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
parameter C_S_AXI_MIN_SIZE = 32'hffff;
parameter C_BASEADDR = 32'hffffffff;
parameter C_HIGHADDR = 32'h00000000;
parameter C_BASEADDR = 32'h00000000;
parameter C_HIGHADDR = 32'hffffffff;
// jesd interface
// rx_clk is (line-rate/40)
@ -99,9 +97,12 @@ module axi_ad9250 (
// dma interface
output adc_clk;
output adc_dwr;
output [63:0] adc_ddata;
output adc_dsync;
output adc_valid_a;
output adc_enable_a;
output [31:0] adc_data_a;
output adc_valid_b;
output adc_enable_b;
output [31:0] adc_data_b;
input adc_dovf;
input adc_dunf;
@ -127,20 +128,11 @@ module axi_ad9250 (
output [31:0] s_axi_rdata;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [55:0] adc_mon_data;
// internal registers
reg adc_data_cnt = 'd0;
reg adc_dsync = 'd0;
reg adc_dwr = 'd0;
reg [63:0] adc_ddata = 'd0;
reg up_adc_status_pn_err = 'd0;
reg up_adc_status_pn_oos = 'd0;
reg up_adc_status_or = 'd0;
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
@ -157,22 +149,11 @@ module axi_ad9250 (
wire adc_or_a_s;
wire adc_or_b_s;
wire adc_status_s;
wire adc_enable_a_s;
wire [31:0] adc_channel_data_a_s;
wire adc_enable_b_s;
wire [31:0] adc_channel_data_b_s;
wire up_adc_pn_err_a_s;
wire up_adc_pn_oos_a_s;
wire up_adc_or_a_s;
wire [31:0] up_adc_channel_rdata_a_s;
wire up_adc_channel_ack_a_s;
wire up_adc_pn_err_b_s;
wire up_adc_pn_oos_b_s;
wire up_adc_or_b_s;
wire [31:0] up_adc_channel_rdata_b_s;
wire up_adc_channel_ack_b_s;
wire [31:0] up_adc_common_rdata_s;
wire up_adc_common_ack_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire [31:0] up_rdata_s[0:2];
wire up_ack_s[0:2];
wire up_sel_s;
wire up_wr_s;
wire [13:0] up_addr_s;
@ -183,59 +164,29 @@ module axi_ad9250 (
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// monitor signals
assign adc_mon_valid = 1'b1;
assign adc_mon_data[ 27: 0] = adc_data_a_s;
assign adc_mon_data[ 55: 28] = adc_data_b_s;
// adc channels - dma interface
always @(posedge adc_clk) begin
adc_data_cnt <= ~adc_data_cnt;
case ({adc_enable_b_s, adc_enable_a_s})
2'b11: begin // both I and Q
adc_dsync <= 1'b1;
adc_dwr <= 1'b1;
adc_ddata <= {adc_channel_data_b_s[31:16], adc_channel_data_a_s[31:16],
adc_channel_data_b_s[15: 0], adc_channel_data_a_s[15: 0]};
end
2'b10: begin // Q only
adc_dsync <= 1'b1;
adc_dwr <= adc_data_cnt;
adc_ddata <= {adc_channel_data_b_s, adc_ddata[63:32]};
end
2'b01: begin // I only
adc_dsync <= 1'b1;
adc_dwr <= adc_data_cnt;
adc_ddata <= {adc_channel_data_a_s, adc_ddata[63:32]};
end
default: begin // no channels
adc_dsync <= 1'b1;
adc_dwr <= 1'b1;
adc_ddata <= {4{16'hdead}};
end
endcase
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_adc_status_pn_err <= 'd0;
up_adc_status_pn_oos <= 'd0;
up_adc_status_or <= 'd0;
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_adc_status_pn_err <= up_adc_pn_err_a_s | up_adc_pn_err_b_s;
up_adc_status_pn_oos <= up_adc_pn_oos_a_s | up_adc_pn_oos_b_s;
up_adc_status_or <= up_adc_or_a_s | up_adc_or_b_s;
up_rdata <= up_adc_common_rdata_s | up_adc_channel_rdata_a_s | up_adc_channel_rdata_b_s;
up_ack <= up_adc_common_ack_s | up_adc_channel_ack_a_s | up_adc_channel_ack_b_s;
up_status_pn_err <= | up_status_pn_err_s;
up_status_pn_oos <= | up_status_pn_oos_s;
up_status_or <= | up_status_or_s;
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
up_ack <= up_ack_s[0] | up_ack_s[1] | up_ack_s[2];
end
end
// adc valid
assign adc_valid_a = 1'b1;
assign adc_valid_b = 1'b1;
// main (device interface)
axi_ad9250_if i_if (
@ -256,19 +207,19 @@ module axi_ad9250 (
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dfmt_data (adc_channel_data_a_s),
.adc_enable (adc_enable_a_s),
.up_adc_pn_err (up_adc_pn_err_a_s),
.up_adc_pn_oos (up_adc_pn_oos_a_s),
.up_adc_or (up_adc_or_a_s),
.adc_dfmt_data (adc_data_a),
.adc_enable (adc_enable_a),
.up_adc_pn_err (up_status_pn_err_s[0]),
.up_adc_pn_oos (up_status_pn_oos_s[0]),
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_a_s),
.up_ack (up_adc_channel_ack_a_s));
.up_rdata (up_rdata_s[0]),
.up_ack (up_ack_s[0]));
// channel
@ -277,19 +228,19 @@ module axi_ad9250 (
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dfmt_data (adc_channel_data_b_s),
.adc_enable (adc_enable_b_s),
.up_adc_pn_err (up_adc_pn_err_b_s),
.up_adc_pn_oos (up_adc_pn_oos_b_s),
.up_adc_or (up_adc_or_b_s),
.adc_dfmt_data (adc_data_b),
.adc_enable (adc_enable_b),
.up_adc_pn_err (up_status_pn_err_s[1]),
.up_adc_pn_oos (up_status_pn_oos_s[1]),
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel_s),
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_channel_rdata_b_s),
.up_ack (up_adc_channel_ack_b_s));
.up_rdata (up_rdata_s[1]),
.up_ack (up_ack_s[1]));
// common processor control
@ -301,12 +252,12 @@ module axi_ad9250 (
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status (adc_status_s),
.adc_status_pn_err (up_adc_status_pn_err),
.adc_status_pn_oos (up_adc_status_pn_oos),
.adc_status_or (up_adc_status_or),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.delay_clk (1'b0),
.delay_rst (),
.delay_sel (),
@ -333,8 +284,8 @@ module axi_ad9250 (
.up_wr (up_wr_s),
.up_addr (up_addr_s),
.up_wdata (up_wdata_s),
.up_rdata (up_adc_common_rdata_s),
.up_ack (up_adc_common_ack_s));
.up_rdata (up_rdata_s[2]),
.up_ack (up_ack_s[2]));
// up bus interface

43
library/axi_ad9250/axi_ad9250_alt.v
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@ -50,9 +50,12 @@ module axi_ad9250_alt (
// dma interface
adc_clk,
adc_dwr,
adc_ddata,
adc_dsync,
adc_valid_a,
adc_enable_a,
adc_data_a,
adc_valid_b,
adc_enable_b,
adc_data_b,
adc_dovf,
adc_dunf,
@ -94,12 +97,7 @@ module axi_ad9250_alt (
s_axi_rdata,
s_axi_rid,
s_axi_rlast,
s_axi_rready,
// debug signals
adc_mon_valid,
adc_mon_data);
s_axi_rready);
parameter PCORE_ID = 0;
parameter PCORE_AXI_ID_WIDTH = 3;
@ -114,9 +112,12 @@ module axi_ad9250_alt (
// dma interface
output adc_clk;
output adc_dwr;
output [63:0] adc_ddata;
output adc_dsync;
output adc_valid_a;
output adc_enable_a;
output [31:0] adc_data_a;
output adc_valid_b;
output adc_enable_b;
output [31:0] adc_data_b;
input adc_dovf;
input adc_dunf;
@ -160,11 +161,6 @@ module axi_ad9250_alt (
output s_axi_rlast;
input s_axi_rready;
// debug signals
output adc_mon_valid;
output [119:0] adc_mon_data;
// defaults
assign s_axi_bid = 'd0;
@ -184,9 +180,12 @@ module axi_ad9250_alt (
.rx_clk (rx_clk),
.rx_data (rx_data),
.adc_clk (adc_clk),
.adc_dwr (adc_dwr),
.adc_ddata (adc_ddata),
.adc_dsync (adc_dsync),
.adc_valid_a (adc_valid_a),
.adc_enable_a (adc_enable_a),
.adc_data_a (adc_data_a),
.adc_valid_b (adc_valid_b),
.adc_enable_b (adc_enable_b),
.adc_data_b (adc_data_b),
.adc_dovf (adc_dovf),
.adc_dunf (adc_dunf),
.s_axi_aclk (s_axi_aclk),
@ -207,9 +206,7 @@ module axi_ad9250_alt (
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rresp (s_axi_rresp),
.s_axi_rdata (s_axi_rdata),
.s_axi_rready (s_axi_rready),
.adc_mon_valid (adc_mon_valid),
.adc_mon_data (adc_mon_data));
.s_axi_rready (s_axi_rready));
endmodule

8
library/axi_ad9250/axi_ad9250_channel.v
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@ -103,7 +103,7 @@ module axi_ad9250_channel (
wire adc_pn_oos_s;
wire adc_pn_err_s;
wire adc_pn_type_s;
wire [ 3:0] adc_pnseq_sel_s;
wire adc_dfmt_enable_s;
wire adc_dfmt_type_s;
wire adc_dfmt_se_s;
@ -115,7 +115,7 @@ module axi_ad9250_channel (
.adc_data (adc_data),
.adc_pn_oos (adc_pn_oos_s),
.adc_pn_err (adc_pn_err_s),
.adc_pn_type (adc_pn_type_s));
.adc_pnseq_sel (adc_pnseq_sel_s));
genvar n;
generate
@ -136,17 +136,17 @@ module axi_ad9250_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable),
.adc_pn_sel (),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (adc_dfmt_se_s),
.adc_dfmt_type (adc_dfmt_type_s),
.adc_dfmt_enable (adc_dfmt_enable_s),
.adc_pn_type (adc_pn_type_s),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (adc_pnseq_sel_s),
.adc_data_sel (),
.adc_pn_err (adc_pn_err_s),
.adc_pn_oos (adc_pn_oos_s),
.adc_or (adc_or),

21
library/axi_ad9250/axi_ad9250_hw.tcl
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@ -13,6 +13,7 @@ set_module_property DISPLAY_NAME axi_ad9250
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL axi_ad9250_alt
add_fileset_file ad_rst.v VERILOG PATH $ad_hdl_dir/library/common/altera/ad_rst.v
add_fileset_file ad_pnmon.v VERILOG PATH $ad_hdl_dir/library/common/ad_pnmon.v
add_fileset_file ad_datafmt.v VERILOG PATH $ad_hdl_dir/library/common/ad_datafmt.v
add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
add_fileset_file up_xfer_cntrl.v VERILOG PATH $ad_hdl_dir/library/common/up_xfer_cntrl.v
@ -116,16 +117,12 @@ add_interface_port adc_clock adc_clk clk Output 1
add_interface adc_dma_if conduit end
set_interface_property adc_dma_if associatedClock adc_clock
add_interface_port adc_dma_if adc_ddata ddata Output 64
add_interface_port adc_dma_if adc_dsync dsync Output 1
add_interface_port adc_dma_if adc_dovf dovf Input 1
add_interface_port adc_dma_if adc_dunf dunf Input 1
add_interface_port adc_dma_if adc_dwr dwr Output 1
# signal tap
add_interface adc_mon_if conduit end
set_interface_property adc_mon_if associatedClock adc_clock
add_interface_port adc_mon_if adc_mon_valid valid Output 1
add_interface_port adc_mon_if adc_mon_data data Output 56
add_interface_port adc_dma_if adc_valid_a adc_valid_a Output 1
add_interface_port adc_dma_if adc_enable_a adc_enable_a Output 1
add_interface_port adc_dma_if adc_data_a adc_data_a Output 32
add_interface_port adc_dma_if adc_valid_b adc_valid_b Output 1
add_interface_port adc_dma_if adc_enable_b adc_enable_b Output 1
add_interface_port adc_dma_if adc_data_b adc_data_b Output 32
add_interface_port adc_dma_if adc_dovf adc_dovf Input 1
add_interface_port adc_dma_if adc_dunf adc_dunf Input 1

2
library/axi_ad9250/axi_ad9250_if.v
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@ -94,14 +94,12 @@ module axi_ad9250_if (
// adc channels
assign adc_data_a = {adc_data_a_s1_s[13:0], adc_data_a_s0_s[13:0]};
assign adc_data_b = {adc_data_b_s1_s[13:0], adc_data_b_s0_s[13:0]};
// data multiplex
assign adc_data_a_s1_s = {rx_data[25:24], rx_data[23:16], rx_data[31:26]};
assign adc_data_a_s0_s = {rx_data[ 9: 8], rx_data[ 7: 0], rx_data[15:10]};
assign adc_data_b_s1_s = {rx_data[57:56], rx_data[55:48], rx_data[63:58]};
assign adc_data_b_s0_s = {rx_data[41:40], rx_data[39:32], rx_data[47:42]};

1
library/axi_ad9250/axi_ad9250_ip.tcl
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@ -6,6 +6,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_ad9250
adi_ip_files axi_ad9250 [list \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_pnmon.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \

79
library/axi_ad9250/axi_ad9250_pnmon.v
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@ -52,9 +52,9 @@ module axi_ad9250_pnmon (
adc_pn_oos,
adc_pn_err,
// processor interface PN9 (0x0), PN23 (0x1)
// processor interface
adc_pn_type);
adc_pnseq_sel);
// adc interface
@ -68,28 +68,16 @@ module axi_ad9250_pnmon (
// processor interface PN9 (0x0), PN23 (0x1)
input adc_pn_type;
input [ 3:0] adc_pnseq_sel;
// internal registers
reg [27:0] adc_pn_data = 'd0;
reg adc_pn_match_d_1 = 'd0;
reg adc_pn_match_d_0 = 'd0;
reg adc_pn_match_z = 'd0;
reg adc_pn_err = 'd0;
reg [ 6:0] adc_pn_oos_count = 'd0;
reg adc_pn_oos = 'd0;
reg [27:0] adc_pn_data_in = 'd0;
reg [27:0] adc_pn_data_pn = 'd0;
// internal signals
wire [27:0] adc_pn_data_in_s;
wire adc_pn_match_d_1_s;
wire adc_pn_match_d_0_s;
wire adc_pn_match_z_s;
wire adc_pn_match_s;
wire [27:0] adc_pn_data_s;
wire adc_pn_update_s;
wire adc_pn_err_s;
wire [27:0] adc_pn_data_pn_s;
// PN23 function
@ -167,55 +155,28 @@ module axi_ad9250_pnmon (
end
endfunction
// pn sequence checking algorithm is commonly used in most applications.
// if oos is asserted (pn is out of sync):
// the next sequence is generated from the incoming data.
// if 16 sequences match consecutively, oos is cleared (de-asserted).
// if oos is de-asserted (pn is in sync)
// the next sequence is generated from the current sequence.
// if 64 sequences mismatch consecutively, oos is set (asserted).
// if oos is de-asserted, any spurious mismatches sets the error register.
// ideally, processor should make sure both oos == 0x0 and err == 0x0.
// pn sequence select
assign adc_pn_data_in_s = {~adc_data[13], adc_data[12:0], ~adc_data[27], adc_data[26:14]};
assign adc_pn_match_d_1_s = (adc_pn_data_in_s[27:14] == adc_pn_data[27:14]) ? 1'b1 : 1'b0;
assign adc_pn_match_d_0_s = (adc_pn_data_in_s[13: 0] == adc_pn_data[13: 0]) ? 1'b1 : 1'b0;
assign adc_pn_match_z_s = (adc_pn_data_in_s == 28'd0) ? 1'b0 : 1'b1;
assign adc_pn_match_s = adc_pn_match_d_1 & adc_pn_match_d_0 & adc_pn_match_z;
assign adc_pn_data_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in_s : adc_pn_data;
assign adc_pn_update_s = ~(adc_pn_oos ^ adc_pn_match_s);
assign adc_pn_err_s = ~(adc_pn_oos | adc_pn_match_s);
// pn running sequence
assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
always @(posedge adc_clk) begin
if (adc_pn_type == 1'b0) begin
adc_pn_data <= pn9(adc_pn_data_s);
adc_pn_data_in <= {~adc_data[13], adc_data[12:0], ~adc_data[27], adc_data[26:14]};
if (adc_pnseq_sel == 4'd0) begin
adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
end else begin
adc_pn_data <= pn23(adc_pn_data_s);
adc_pn_data_pn <= pn23(adc_pn_data_pn_s);
end
end
// pn oos and counters (64 to clear and set).
// pn oos & pn err
always @(posedge adc_clk) begin
adc_pn_match_d_1 <= adc_pn_match_d_1_s;
adc_pn_match_d_0 <= adc_pn_match_d_0_s;
adc_pn_match_z <= adc_pn_match_z_s;
adc_pn_err <= adc_pn_err_s;
if (adc_pn_update_s == 1'b1) begin
if (adc_pn_oos_count >= 16) begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= ~adc_pn_oos;
end else begin
adc_pn_oos_count <= adc_pn_oos_count + 1'b1;
adc_pn_oos <= adc_pn_oos;
end
end else begin
adc_pn_oos_count <= 'd0;
adc_pn_oos <= adc_pn_oos;
end
end
ad_pnmon #(.DATA_WIDTH(28)) i_pnmon (
.adc_clk (adc_clk),
.adc_valid_in (1'b1),
.adc_data_in (adc_pn_data_in),
.adc_data_pn (adc_pn_data_pn),
.adc_pn_oos (adc_pn_oos),
.adc_pn_err (adc_pn_err));
endmodule

20
projects/fmcjesdadc1/a5soc/system_bd.qsys
View File

@ -160,11 +160,11 @@
type = "String";
}
}
element axi_ad9250_0.s_axi
element axi_hdmi_tx.s_axi
{
datum baseAddress
{
value = "65536";
value = "0";
type = "String";
}
}
@ -184,11 +184,11 @@
type = "String";
}
}
element axi_hdmi_tx.s_axi
element axi_ad9250_0.s_axi
{
datum baseAddress
{
value = "0";
value = "65536";
type = "String";
}
}
@ -389,11 +389,7 @@
internal="axi_ad9250_0.adc_dma_if"
type="conduit"
dir="end" />
<interface
name="axi_ad9250_0_adc_mon_if"
internal="axi_ad9250_0.adc_mon_if"
type="conduit"
dir="end" />
<interface name="axi_ad9250_0_adc_mon_if" internal="axi_ad9250_0.adc_mon_if" />
<interface
name="axi_dmac_0_fifo_wr_clock"
internal="axi_dmac_0.fifo_wr_clock"
@ -424,11 +420,7 @@
internal="axi_ad9250_1.adc_dma_if"
type="conduit"
dir="end" />
<interface
name="axi_ad9250_1_adc_mon_if"
internal="axi_ad9250_1.adc_mon_if"
type="conduit"
dir="end" />
<interface name="axi_ad9250_1_adc_mon_if" internal="axi_ad9250_1.adc_mon_if" />
<interface
name="axi_dmac_1_fifo_wr_clock"
internal="axi_dmac_1.fifo_wr_clock"

86
projects/fmcjesdadc1/a5soc/system_top.v
View File

@ -269,6 +269,10 @@ module system_top (
reg rx_sysref_m2 = 'd0;
reg rx_sysref_m3 = 'd0;
reg rx_sysref = 'd0;
reg dma0_wr = 'd0;
reg [ 63:0] dma0_wdata = 'd0;
reg dma1_wr = 'd0;
reg [ 63:0] dma1_wdata = 'd0;
reg [ 63:0] sys_hdmi_pll_reconfig_in = 'd0;
reg [ 63:0] sys_hdmi_pll_reconfig_reconfig_in = 'd0;
@ -286,18 +290,16 @@ module system_top (
wire spi_clk_s;
wire spi_mosi_s;
wire spi_miso_s;
wire [ 63:0] adc0_ddata_s;
wire adc0_dsync_s;
wire adc0_enable_a_s;
wire [ 31:0] adc0_data_a_s;
wire adc0_enable_b_s;
wire [ 31:0] adc0_data_b_s;
wire adc0_dovf_s;
wire adc0_dwr_s;
wire adc0_mon_valid_s;
wire [ 55:0] adc0_mon_data_s;
wire [ 63:0] adc1_ddata_s;
wire adc1_dsync_s;
wire adc1_enable_a_s;
wire [ 31:0] adc1_data_a_s;
wire adc1_enable_b_s;
wire [ 31:0] adc1_data_b_s;
wire adc1_dovf_s;
wire adc1_dwr_s;
wire adc1_mon_valid_s;
wire [ 55:0] adc1_mon_data_s;
wire [ 3:0] rx_ip_sof_s;
wire [127:0] rx_ip_data_s;
wire [127:0] rx_data_s;
@ -325,9 +327,22 @@ module system_top (
rx_sysref <= rx_sysref_m2 & ~rx_sysref_m3;
end
always @(posedge rx_clk) begin
dma0_wr <= adc0_enable_a_s & adc0_enable_b_s;
dma0_wdata <= { adc0_data_b_s[31:16],
adc0_data_a_s[31:16],
adc0_data_b_s[15: 0],
adc0_data_a_s[15: 0]};
dma1_wr <= adc1_enable_a_s & adc1_enable_b_s;
dma1_wdata <= { adc1_data_b_s[31:16],
adc1_data_a_s[31:16],
adc1_data_b_s[15: 0],
adc1_data_a_s[15: 0]};
end
sld_signaltap #(
.sld_advanced_trigger_entity ("basic,1,"),
.sld_data_bits (114),
.sld_data_bits (130),
.sld_data_bit_cntr_bits (8),
.sld_enable_advanced_trigger (0),
.sld_mem_address_bits (10),
@ -345,7 +360,12 @@ module system_top (
.sld_trigger_level_pipeline (1))
i_signaltap (
.acq_clk (rx_clk),
.acq_data_in ({rx_sysref, rx_sync, adc1_mon_data_s, adc0_mon_data_s}),
.acq_data_in ({ rx_sysref,
rx_sync,
adc1_data_b_s,
adc1_data_a_s,
adc0_data_b_s,
adc0_data_a_s}),
.acq_trigger_in ({rx_sysref, rx_sync}));
genvar n;
@ -418,33 +438,35 @@ module system_top (
.axi_ad9250_0_xcvr_clk_clk (rx_clk),
.axi_ad9250_0_xcvr_data_data (rx_data_s[63:0]),
.axi_ad9250_0_adc_clock_clk (adc0_clk),
.axi_ad9250_0_adc_dma_if_ddata (adc0_ddata_s),
.axi_ad9250_0_adc_dma_if_dsync (adc0_dsync_s),
.axi_ad9250_0_adc_dma_if_dovf (adc0_dovf_s),
.axi_ad9250_0_adc_dma_if_dunf (1'b0),
.axi_ad9250_0_adc_dma_if_dwr (adc0_dwr_s),
.axi_ad9250_0_adc_mon_if_valid (adc0_mon_valid_s),
.axi_ad9250_0_adc_mon_if_data (adc0_mon_data_s),
.axi_ad9250_0_adc_dma_if_adc_valid_a (),
.axi_ad9250_0_adc_dma_if_adc_enable_a (adc0_enable_a_s),
.axi_ad9250_0_adc_dma_if_adc_data_a (adc0_data_a_s),
.axi_ad9250_0_adc_dma_if_adc_valid_b (),
.axi_ad9250_0_adc_dma_if_adc_enable_b (adc0_enable_b_s),
.axi_ad9250_0_adc_dma_if_adc_data_b (adc0_data_b_s),
.axi_ad9250_0_adc_dma_if_adc_dovf (adc0_dovf_s),
.axi_ad9250_0_adc_dma_if_adc_dunf (1'b0),
.axi_dmac_0_fifo_wr_clock_clk (adc0_clk),
.axi_dmac_0_fifo_wr_if_ovf (adc0_dovf_s),
.axi_dmac_0_fifo_wr_if_wren (adc0_dwr_s),
.axi_dmac_0_fifo_wr_if_data (adc0_ddata_s),
.axi_dmac_0_fifo_wr_if_sync (adc0_dsync_s),
.axi_dmac_0_fifo_wr_if_wren (dma0_wr),
.axi_dmac_0_fifo_wr_if_data (dma0_wdata),
.axi_dmac_0_fifo_wr_if_sync (1'b1),
.axi_ad9250_1_xcvr_clk_clk (rx_clk),
.axi_ad9250_1_xcvr_data_data (rx_data_s[127:64]),
.axi_ad9250_1_adc_clock_clk (adc1_clk),
.axi_ad9250_1_adc_dma_if_ddata (adc1_ddata_s),
.axi_ad9250_1_adc_dma_if_dsync (adc1_dsync_s),
.axi_ad9250_1_adc_dma_if_dovf (adc1_dovf_s),
.axi_ad9250_1_adc_dma_if_dunf (1'b0),
.axi_ad9250_1_adc_dma_if_dwr (adc1_dwr_s),
.axi_ad9250_1_adc_mon_if_valid (adc1_mon_valid_s),
.axi_ad9250_1_adc_mon_if_data (adc1_mon_data_s),
.axi_ad9250_1_adc_dma_if_adc_valid_a (),
.axi_ad9250_1_adc_dma_if_adc_enable_a (adc1_enable_a_s),
.axi_ad9250_1_adc_dma_if_adc_data_a (adc1_data_a_s),
.axi_ad9250_1_adc_dma_if_adc_valid_b (),
.axi_ad9250_1_adc_dma_if_adc_enable_b (adc1_enable_b_s),
.axi_ad9250_1_adc_dma_if_adc_data_b (adc1_data_b_s),
.axi_ad9250_1_adc_dma_if_adc_dovf (adc1_dovf_s),
.axi_ad9250_1_adc_dma_if_adc_dunf (1'b0),
.axi_dmac_1_fifo_wr_clock_clk (adc1_clk),
.axi_dmac_1_fifo_wr_if_ovf (adc1_dovf_s),
.axi_dmac_1_fifo_wr_if_wren (adc1_dwr_s),
.axi_dmac_1_fifo_wr_if_data (adc1_ddata_s),
.axi_dmac_1_fifo_wr_if_sync (adc1_dsync_s),
.axi_dmac_1_fifo_wr_if_wren (dma1_wr),
.axi_dmac_1_fifo_wr_if_data (dma1_wdata),
.axi_dmac_1_fifo_wr_if_sync (1'b1),
.sys_jesd204b_s1_ref_clk_in_clk_clk (ref_clk),
.sys_jesd204b_s1_rx_clk_out_clk_clk (rx_clk),
.sys_jesd204b_s1_jesd204_rx_link_data (rx_ip_data_s),