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ad9361/tdd: Fix generation of tx_valid_* signals 

In FDD mode the tx_valid_* signals are generated inside the axi_ad9361_tx module, in function of
the selected dac data rate. In TDD mode, these signals are gated by the tdd_enable and tdd_tx_dp_en signals.
In other words, the tx_valid_* signals will be valid just when tdd_enable and tdd_tx_dp_en is active.
main
Istvan Csomortani 2015-06-08 16:21:40 +03:00
parent b3324b3ef9
commit 4b08df9ed6
3 changed files with 9 additions and 11 deletions
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1
library/axi_ad9361/axi_ad9361.v
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@ -392,7 +392,6 @@ module axi_ad9361 (
axi_ad9361_tdd i_tdd( axi_ad9361_tdd i_tdd(
.clk(clk), .clk(clk),
.rst(rst), .rst(rst),
.tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en_s), .tdd_rx_vco_en(tdd_rx_vco_en_s),
.tdd_tx_vco_en(tdd_tx_vco_en_s), .tdd_tx_vco_en(tdd_tx_vco_en_s),
.tdd_rx_rf_en(tdd_rx_rf_en_s), .tdd_rx_rf_en(tdd_rx_rf_en_s),

16
library/axi_ad9361/axi_ad9361_tdd.v
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@ -48,7 +48,6 @@ module axi_ad9361_tdd (
// control signals from the tdd control // control signals from the tdd control
tdd_tx_dp_en,
tdd_rx_vco_en, tdd_rx_vco_en,
tdd_tx_vco_en, tdd_tx_vco_en,
tdd_rx_rf_en, tdd_rx_rf_en,
@ -91,7 +90,6 @@ module axi_ad9361_tdd (
// control signals from the tdd control // control signals from the tdd control
output tdd_tx_dp_en;
output tdd_rx_vco_en; output tdd_rx_vco_en;
output tdd_tx_vco_en; output tdd_tx_vco_en;
output tdd_rx_rf_en; output tdd_rx_rf_en;
@ -159,15 +157,17 @@ module axi_ad9361_tdd (
wire [23:0] tdd_counter_status; wire [23:0] tdd_counter_status;
assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_tx_dp_en, wire tdd_tx_dp_en_s;
assign tdd_dbg = {tdd_counter_status, tdd_enable_s, tdd_tx_dp_en_s,
tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en}; tdd_rx_vco_en, tdd_tx_vco_en, tdd_rx_rf_en, tdd_tx_rf_en};
// tx data flow control // tx data flow control
assign tdd_tx_valid_i0 = tx_valid_i0 & tdd_enable_s; assign tdd_tx_valid_i0 = (tdd_enable_s == 1'b1) ? (tx_valid_i0 & tdd_tx_dp_en_s) : tx_valid_i0;
assign tdd_tx_valid_q0 = tx_valid_q0 & tdd_enable_s; assign tdd_tx_valid_q0 = (tdd_enable_s == 1'b1) ? (tx_valid_q0 & tdd_tx_dp_en_s) : tx_valid_q0;
assign tdd_tx_valid_i1 = tx_valid_i1 & tdd_enable_s; assign tdd_tx_valid_i1 = (tdd_enable_s == 1'b1) ? (tx_valid_i1 & tdd_tx_dp_en_s) : tx_valid_i1;
assign tdd_tx_valid_q1 = tx_valid_q1 & tdd_enable_s; assign tdd_tx_valid_q1 = (tdd_enable_s == 1'b1) ? (tx_valid_q1 & tdd_tx_dp_en_s) : tx_valid_q1;
// instantiations // instantiations
@ -243,7 +243,7 @@ module axi_ad9361_tdd (
.tdd_tx_off_2(tdd_tx_off_2_s), .tdd_tx_off_2(tdd_tx_off_2_s),
.tdd_tx_dp_on_2(tdd_tx_dp_on_2_s), .tdd_tx_dp_on_2(tdd_tx_dp_on_2_s),
.tdd_tx_dp_off_2(tdd_tx_dp_off_2_s), .tdd_tx_dp_off_2(tdd_tx_dp_off_2_s),
.tdd_tx_dp_en(tdd_tx_dp_en), .tdd_tx_dp_en(tdd_tx_dp_en_s),
.tdd_rx_vco_en(tdd_rx_vco_en), .tdd_rx_vco_en(tdd_rx_vco_en),
.tdd_tx_vco_en(tdd_tx_vco_en), .tdd_tx_vco_en(tdd_tx_vco_en),
.tdd_rx_rf_en(tdd_rx_rf_en), .tdd_rx_rf_en(tdd_rx_rf_en),

3
library/common/up_tdd_cntrl.v
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@ -180,7 +180,6 @@ module up_tdd_cntrl (
wire up_wreq_s; wire up_wreq_s;
wire up_rreq_s; wire up_rreq_s;
wire up_cntrl_xfer_done;
wire [ 7:0] up_tdd_status_s; wire [ 7:0] up_tdd_status_s;
@ -352,7 +351,7 @@ module up_tdd_cntrl (
up_tdd_tx_only, up_tdd_tx_only,
up_tdd_burst_count up_tdd_burst_count
}), }),
.up_xfer_done(up_cntrl_xfer_done), .up_xfer_done(),
.d_rst(rst), .d_rst(rst),
.d_clk(clk), .d_clk(clk),
.d_data_cntrl({tdd_enable, .d_data_cntrl({tdd_enable,