util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching

main
Adrian Costina 2017-01-13 13:54:07 +02:00
parent e77428c50e
commit 4b2602437f
3 changed files with 31 additions and 2 deletions

View File

@ -35,7 +35,8 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1 // Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
// IP uses BUFR and BUFGMUX primitives // IP uses BUFR and BUFGMUX_CTRL primitive
// IP provides a glitch free output clock
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
@ -47,9 +48,13 @@ module util_clkdiv (
output clk_out output clk_out
); );
parameter C_SIM_DEVICE = "7SERIES";
wire clk_div_2_s; wire clk_div_2_s;
wire clk_div_4_s; wire clk_div_4_s;
generate if (C_SIM_DEVICE == "7SERIES") begin
BUFR #( BUFR #(
.BUFR_DIVIDE("2"), .BUFR_DIVIDE("2"),
.SIM_DEVICE("7SERIES") .SIM_DEVICE("7SERIES")
@ -68,7 +73,27 @@ module util_clkdiv (
.CLR(0), .CLR(0),
.O(clk_div_4_s)); .O(clk_div_4_s));
BUFGMUX i_div_clk_gbuf ( end else if (C_SIM_DEVICE == "ULTRASCALE") begin
BUFGCE_DIV #(
.BUFGCE_DIVIDE("2")
) clk_divide_2 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_2_s));
BUFGCE_DIV #(
.BUFGCE_DIVIDE("4")
) clk_divide_4 (
.I(clk),
.CE(1),
.CLR(0),
.O(clk_div_4_s));
end endgenerate
BUFGMUX_CTRL i_div_clk_gbuf (
.I0(clk_div_4_s), // 1-bit input: Clock input (S=0) .I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
.I1(clk_div_2_s), // 1-bit input: Clock input (S=1) .I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
.S(clk_sel), .S(clk_sel),

View File

@ -1 +1,2 @@
set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive
set_false_path -to [get_pins i_div_clk_gbuf/S*]

View File

@ -13,4 +13,7 @@ adi_ip_constraints util_clkdiv [list \
set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
set_property value_validation_type list [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]