util_clkdiv: Added Ultrascale support and switch to BUFGMUX_CTRL for glitch free switching
parent
e77428c50e
commit
4b2602437f
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@ -35,7 +35,8 @@
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
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// Divides the input clock to 4 if clk_sel is 0 or 2 if clk_sel is 1
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// IP uses BUFR and BUFGMUX primitives
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// IP uses BUFR and BUFGMUX_CTRL primitive
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// IP provides a glitch free output clock
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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@ -47,9 +48,13 @@ module util_clkdiv (
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output clk_out
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output clk_out
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);
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);
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parameter C_SIM_DEVICE = "7SERIES";
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wire clk_div_2_s;
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wire clk_div_2_s;
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wire clk_div_4_s;
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wire clk_div_4_s;
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generate if (C_SIM_DEVICE == "7SERIES") begin
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BUFR #(
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BUFR #(
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.BUFR_DIVIDE("2"),
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.BUFR_DIVIDE("2"),
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.SIM_DEVICE("7SERIES")
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.SIM_DEVICE("7SERIES")
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@ -68,7 +73,27 @@ module util_clkdiv (
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.CLR(0),
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.CLR(0),
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.O(clk_div_4_s));
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.O(clk_div_4_s));
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BUFGMUX i_div_clk_gbuf (
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end else if (C_SIM_DEVICE == "ULTRASCALE") begin
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BUFGCE_DIV #(
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.BUFGCE_DIVIDE("2")
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) clk_divide_2 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_2_s));
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BUFGCE_DIV #(
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.BUFGCE_DIVIDE("4")
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) clk_divide_4 (
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.I(clk),
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.CE(1),
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.CLR(0),
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.O(clk_div_4_s));
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end endgenerate
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BUFGMUX_CTRL i_div_clk_gbuf (
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.I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
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.I0(clk_div_4_s), // 1-bit input: Clock input (S=0)
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.I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
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.I1(clk_div_2_s), // 1-bit input: Clock input (S=1)
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.S(clk_sel),
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.S(clk_sel),
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@ -1 +1,2 @@
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set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive
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set_clock_groups -group [get_clocks clk_div_4_s] -group [get_clocks clk_div_2_s] -logically_exclusive
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set_false_path -to [get_pins i_div_clk_gbuf/S*]
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@ -13,4 +13,7 @@ adi_ip_constraints util_clkdiv [list \
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set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
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set_property driver_value 0 [ipx::get_ports clk_sel -of_objects [ipx::current_core]]
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set_property value_validation_type list [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
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set_property value_validation_list {7SERIES ULTRASCALE} [ipx::get_user_parameters C_SIM_DEVICE -of_objects [ipx::current_core]]
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ipx::save_core [ipx::current_core]
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ipx::save_core [ipx::current_core]
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