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ad7768-1evb: Add coraz7s support

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Stanca Pop 2019-09-20 18:41:48 +03:00 committed by StancaPop
parent 40d839df5f
commit 4b380fe640
5 changed files with 242 additions and 0 deletions
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23
projects/ad77681evb/coraz7s/Makefile Normal file
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####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################
PROJECT_NAME := ad77681evb_coraz7s
M_DEPS += ../common/ad77681evb_bd.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_ps7.tcl
M_DEPS += ../../common/coraz7s/coraz7s_system_constr.xdc
M_DEPS += ../../common/coraz7s/coraz7s_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
LIB_DEPS += axi_dmac
LIB_DEPS += axi_sysid
LIB_DEPS += spi_engine/axi_spi_engine
LIB_DEPS += spi_engine/spi_engine_execution
LIB_DEPS += spi_engine/spi_engine_interconnect
LIB_DEPS += spi_engine/spi_engine_offload
LIB_DEPS += sysid_rom
LIB_DEPS += util_axis_upscale
include ../../scripts/project-xilinx.mk

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projects/ad77681evb/coraz7s/system_bd.tcl Normal file
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source $ad_hdl_dir/projects/common/coraz7s/coraz7s_system_bd.tcl
#system ID
ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt"
ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
set sys_cstring "sys rom custom string placeholder"
sysid_gen_sys_init_file $sys_cstring
source ../common/ad77681evb_bd.tcl

19
projects/ad77681evb/coraz7s/system_constr.xdc Normal file
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# SPI interface
set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad77681_spi_sclk] ; ## CK_IO13
set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports ad77681_spi_miso] ; ## CK_IO12
set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE PULLTYPE PULLUP} [get_ports ad77681_spi_mosi] ; ## CK_IO11
set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} [get_ports ad77681_spi_cs] ; ## CK_IO10
# reset and GPIO signals
set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports ad77681_reset] ; ## CK_IO3
set_property -dict {PACKAGE_PIN M18 IOSTANDARD LVCMOS33} [get_ports ad77681_fda_dis] ; ## CK_IO9
set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS33} [get_ports ad77681_fda_mode] ; ## CK_IO8
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS33} [get_ports ad77681_dac_buf_en] ; ## CK_IO5
# syncronization and timing
set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad77681_drdy] ; ## CK_IO2
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports ad77681_sync_in] ; ## CK_IO6

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projects/ad77681evb/coraz7s/system_project.tcl Normal file
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source ../../scripts/adi_env.tcl
source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project ad77681evb_coraz7s
adi_project_files ad77681evb_coraz7s [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/projects/common/coraz7s/coraz7s_system_constr.xdc"]
adi_project_run ad77681evb_coraz7s

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projects/ad77681evb/coraz7s/system_top.v Normal file
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// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
inout ddr_ck_n,
inout ddr_ck_p,
inout ddr_cke,
inout ddr_cs_n,
inout [ 3:0] ddr_dm,
inout [31:0] ddr_dq,
inout [ 3:0] ddr_dqs_n,
inout [ 3:0] ddr_dqs_p,
inout ddr_odt,
inout ddr_ras_n,
inout ddr_reset_n,
inout ddr_we_n,
inout fixed_io_ddr_vrn,
inout fixed_io_ddr_vrp,
inout [53:0] fixed_io_mio,
inout fixed_io_ps_clk,
inout fixed_io_ps_porb,
inout fixed_io_ps_srstb,
inout [1:0] btn,
inout [5:0] led,
inout ad77681_reset,
inout ad77681_sync_in,
inout ad77681_fda_dis,
inout ad77681_fda_mode,
inout ad77681_dac_buf_en,
input ad77681_spi_miso,
output ad77681_spi_mosi,
output ad77681_spi_sclk,
output ad77681_spi_cs,
input ad77681_drdy);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
// instantiations
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_buttons (
.dio_t(gpio_t[1:0]),
.dio_i(gpio_o[1:0]),
.dio_o(gpio_i[1:0]),
.dio_p(btn));
ad_iobuf #(
.DATA_WIDTH(6)
) i_iobuf_leds (
.dio_t(gpio_t[7:2]),
.dio_i(gpio_o[7:2]),
.dio_o(gpio_i[7:2]),
.dio_p(led));
assign gpio_i[31:8] = gpio_o[31:8];
ad_iobuf #(
.DATA_WIDTH(5)
) i_iobuf_ad77681_gpio (
.dio_t(gpio_t[36:32]),
.dio_i(gpio_o[36:32]),
.dio_o(gpio_i[36:32]),
.dio_p({
ad77681_fda_dis,
ad77681_fda_mode,
ad77681_dac_buf_en,
ad77681_sync_in,
ad77681_reset}));
assign gpio_i[63:37] = gpio_o[63:37];
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.adc_spi_sdo (ad77681_spi_mosi),
.adc_spi_sdo_t (),
.adc_spi_sdi (ad77681_spi_miso),
.adc_spi_cs (ad77681_spi_cs),
.adc_spi_sclk (ad77681_spi_sclk),
.adc_data_ready (ad77681_drdy),
.spi0_clk_i (1'b0),
.spi0_clk_o (),
.spi0_csn_0_o (),
.spi0_csn_1_o (),
.spi0_csn_2_o (),
.spi0_csn_i (1'b1),
.spi0_sdi_i (1'b0),
.spi0_sdo_i (1'b0),
.spi0_sdo_o (),
.spi1_clk_i (1'b0),
.spi1_clk_o (),
.spi1_csn_0_o (),
.spi1_csn_1_o (),
.spi1_csn_2_o (),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o());
endmodule
// ***************************************************************************
// ***************************************************************************