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cn0540_de10nano: Update system_top, cleanup

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Sergiu Arpadi 2023-02-20 12:32:27 +02:00 committed by sarpadi
parent cf3bd8528d
commit 4b704337d4
2 changed files with 3 additions and 7 deletions
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4
projects/cn0540/de10nano/system_qsys.tcl
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@ -1,6 +1,3 @@
set dac_fifo_address_width 10
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl
@ -17,4 +14,3 @@ set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9}
set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt"
sysid_gen_sys_init_file;

6
projects/cn0540/de10nano/system_top.v
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@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2019 - 2020 (c) Analog Devices, Inc. All rights reserved.
// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
@ -8,7 +8,7 @@
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsabilities that he or she has by using this source/core.
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
@ -281,7 +281,7 @@ module system_top (
.cn0540_spi_sdi_sdi (cn0540_spi_miso),
.cn0540_spi_cs_cs (cn0540_spi_cs),
.cn0540_spi_sclk_clk (cn0540_spi_sclk),
.cn0540_spi_trigger_trigger (cn0540_drdy),
.cn0540_spi_trigger_if_pwm (cn0540_drdy),
.sys_spi_MISO (1'b0),
.sys_spi_MOSI (),
.sys_spi_SCLK (),