From 4b704337d48d1faff6ba716d4ae5defaa9f6746f Mon Sep 17 00:00:00 2001 From: Sergiu Arpadi Date: Mon, 20 Feb 2023 12:32:27 +0200 Subject: [PATCH] cn0540_de10nano: Update system_top, cleanup --- projects/cn0540/de10nano/system_qsys.tcl | 4 ---- projects/cn0540/de10nano/system_top.v | 6 +++--- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/projects/cn0540/de10nano/system_qsys.tcl b/projects/cn0540/de10nano/system_qsys.tcl index a1b3677f6..e4d6b3c2e 100755 --- a/projects/cn0540/de10nano/system_qsys.tcl +++ b/projects/cn0540/de10nano/system_qsys.tcl @@ -1,6 +1,3 @@ - -set dac_fifo_address_width 10 - source $ad_hdl_dir/projects/scripts/adi_pd.tcl source $ad_hdl_dir/projects/common/de10nano/de10nano_system_qsys.tcl @@ -17,4 +14,3 @@ set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" sysid_gen_sys_init_file; - diff --git a/projects/cn0540/de10nano/system_top.v b/projects/cn0540/de10nano/system_top.v index 8d5905b2f..664c9d497 100755 --- a/projects/cn0540/de10nano/system_top.v +++ b/projects/cn0540/de10nano/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2019 - 2020 (c) Analog Devices, Inc. All rights reserved. +// Copyright 2022 - 2023 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -8,7 +8,7 @@ // terms. // // The user should read each of these license terms, and understand the -// freedoms and responsabilities that he or she has by using this source/core. +// freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR @@ -281,7 +281,7 @@ module system_top ( .cn0540_spi_sdi_sdi (cn0540_spi_miso), .cn0540_spi_cs_cs (cn0540_spi_cs), .cn0540_spi_sclk_clk (cn0540_spi_sclk), - .cn0540_spi_trigger_trigger (cn0540_drdy), + .cn0540_spi_trigger_if_pwm (cn0540_drdy), .sys_spi_MISO (1'b0), .sys_spi_MOSI (), .sys_spi_SCLK (),