spi_engine: The width of the counters depend on the current DATA_WIDTH
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14f7027793
commit
4b962e8d72
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@ -50,19 +50,22 @@ localparam MISC_SLEEP = 1'b1;
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localparam REG_CLK_DIV = 1'b0;
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localparam REG_CONFIG = 1'b1;
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localparam BIT_COUNTER_WIDTH = DATA_WIDTH > 16 ? 5 :
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DATA_WIDTH > 8 ? 4 : 3;
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reg idle;
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reg [7:0] clk_div_counter = 'h00;
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reg [7:0] clk_div_counter_next = 'h00;
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reg clk_div_last;
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reg [11:0] counter = 'h00;
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reg [(BIT_COUNTER_WIDTH+8):0] counter = 'h00;
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wire [7:0] sleep_counter = counter[11:4];
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wire [1:0] cs_sleep_counter = counter[5:4];
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wire [2:0] cs_sleep_counter2 = counter[6:4];
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wire [2:0] bit_counter = counter[3:1];
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wire [7:0] transfer_counter = counter[11:4];
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wire [7:0] sleep_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
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wire [1:0] cs_sleep_counter = counter[(BIT_COUNTER_WIDTH+2):(BIT_COUNTER_WIDTH+1)];
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wire [2:0] cs_sleep_counter2 = counter[(BIT_COUNTER_WIDTH+3):(BIT_COUNTER_WIDTH+1)];
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wire [(BIT_COUNTER_WIDTH-1):0] bit_counter = counter[BIT_COUNTER_WIDTH:1];
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wire [7:0] transfer_counter = counter[(BIT_COUNTER_WIDTH+8):(BIT_COUNTER_WIDTH+1)];
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wire ntx_rx = counter[0];
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reg trigger = 1'b0;
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@ -76,7 +79,7 @@ reg last_transfer;
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wire end_of_word;
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assign first_bit = bit_counter == 'h0;
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assign last_bit = bit_counter == 'h7;
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assign last_bit = bit_counter == DATA_WIDTH - 1;
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assign end_of_word = last_bit == 1'b1 && ntx_rx == 1'b1 && clk_div_last == 1'b1;
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reg [15:0] cmd_d1;
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