common: clean up synthesis warnings

Removed unused registers and define registers only when they are in use.

library/common/ad_addsub.v

@@ -59,7 +59,6 @@ module ad_addsub #(
   reg     [A_DATA_WIDTH:0]       out_d = 'b0;
   reg     [A_DATA_WIDTH:0]       out_d2 = 'b0;
   reg     [(A_DATA_WIDTH-1):0]   A_d = 'b0;
-  reg     [(A_DATA_WIDTH-1):0]   A_d2 = 'b0;
   reg     [(A_DATA_WIDTH-1):0]   Amax_d = 'b0;
   reg     [(A_DATA_WIDTH-1):0]   Amax_d2 = 'b0;
 
@@ -71,7 +70,6 @@ module ad_addsub #(
 
   always @(posedge clk) begin
       A_d <= A;
-      A_d2 <= A_d;
       Amax_d <= Amax;
       Amax_d2 <= Amax_d;
   end

library/common/ad_iqcor.v

@@ -64,8 +64,6 @@ module ad_iqcor #(
   // internal registers
 
   reg             p1_valid = 'd0;
-  reg     [15:0]  p1_data_i = 'd0;
-  reg     [15:0]  p1_data_q = 'd0;
   reg     [33:0]  p1_data_p = 'd0;
   reg             valid_int = 'd0;
   reg     [15:0]  data_int = 'd0;
@@ -81,6 +79,8 @@ module ad_iqcor #(
   wire    [15:0]  p1_data_i_s;
   wire    [33:0]  p1_data_p_q_s;
   wire    [15:0]  p1_data_q_s;
+  wire    [15:0]  p1_data_i_int;
+  wire    [15:0]  p1_data_q_int;
 
   // data-path disable
 
@@ -133,12 +133,34 @@ module ad_iqcor #(
     assign p1_data_p_q_s = 34'h0;
     assign p1_data_q_s = 16'h0;
   end
+
+  endgenerate
+  generate
+  if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
+    reg [15:0]  p1_data_q = 'd0;
+
+    always @(posedge clk) begin
+      p1_data_q <= p1_data_q_s;
+    end
+
+    assign p1_data_i_int = 16'h0;
+    assign p1_data_q_int = p1_data_q;
+
+  // sum
+  end else begin
+    reg [15:0]  p1_data_i = 'd0;
+
+    always @(posedge clk) begin
+      p1_data_i <= p1_data_i_s;
+    end
+
+    assign p1_data_i_int = p1_data_i;
+    assign p1_data_q_int = 16'h0;
+  end
   endgenerate
 
   always @(posedge clk) begin
     p1_valid <= p1_valid_s;
-    p1_data_i <= p1_data_i_s;
-    p1_data_q <= p1_data_q_s;
     p1_data_p <= p1_data_p_i_s + p1_data_p_q_s;
   end
   // output registers
@@ -148,9 +170,9 @@ module ad_iqcor #(
     if (iqcor_enable == 1'b1) begin
       data_int <= p1_data_p[29:14];
     end else if (Q_OR_I_N == 1 && SCALE_ONLY == 0) begin
-      data_int <= p1_data_q;
+      data_int <= p1_data_q_int;
     end else begin
-      data_int <= p1_data_i;
+      data_int <= p1_data_i_int;
     end
   end