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ad_ip_jesd204_tpl_adc: Fix latency of valid signal

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Laszlo Nagy 2022-02-01 14:27:05 +00:00 committed by Laszlo Nagy
parent 5edf6c19de
commit 4c7be950d1
1 changed files with 3 additions and 1 deletions
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library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_core.v
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@ -73,15 +73,17 @@ module ad_ip_jesd204_tpl_adc_core #(
wire link_valid_tmp; wire link_valid_tmp;
reg link_valid_d = 1'b0; reg link_valid_d = 1'b0;
reg link_valid_dd = 1'b0;
assign link_ready = 1'b1; assign link_ready = 1'b1;
assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_d : link_valid; assign link_valid_tmp = EN_FRAME_ALIGN ? link_valid_dd : link_valid_d;
assign adc_valid = {NUM_CHANNELS{link_valid_tmp & ~adc_sync_armed}}; assign adc_valid = {NUM_CHANNELS{link_valid_tmp & ~adc_sync_armed}};
assign adc_sync_status = adc_sync_armed; assign adc_sync_status = adc_sync_armed;
assign adc_rst_sync = adc_sync_armed; assign adc_rst_sync = adc_sync_armed;
always @(posedge clk) begin always @(posedge clk) begin
link_valid_d <= link_valid; link_valid_d <= link_valid;
link_valid_dd <= link_valid_d;
end end
// synchronization logic // synchronization logic