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scripts/adi_xilinx_device_info_enc.tcl: Add Versal support

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Laszlo Nagy 2021-08-24 08:31:18 +01:00 committed by Laszlo Nagy
parent 2b242bf06f
commit 4d12c4d99a
1 changed files with 18 additions and 11 deletions
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13
library/scripts/adi_xilinx_device_info_enc.tcl
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@ -61,14 +61,18 @@ set fpga_technology_list { \
{ Unknown 0 } \ { Unknown 0 } \
{ 7series 1 } \ { 7series 1 } \
{ ultrascale 2 } \ { ultrascale 2 } \
{ ultrascale+ 3 }} { ultrascale+ 3 } \
{ versal 4 }}
set fpga_family_list { \ set fpga_family_list { \
{ Unknown 0 } \ { Unknown 0 } \
{ artix 1 } \ { artix 1 } \
{ kintex 2 } \ { kintex 2 } \
{ virtex 3 } \ { virtex 3 } \
{ zynq 4 }} { zynq 4 } \
{ versalprime 5 } \
{ versalaicore 6 } \
}
set speed_grade_list { \ set speed_grade_list { \
{ Unknown 0 } \ { Unknown 0 } \
@ -80,6 +84,7 @@ set speed_grade_list { \
{ -2 20 } \ { -2 20 } \
{ -2L 21 } \ { -2L 21 } \
{ -2LV 22 } \ { -2LV 22 } \
{ -2MP 23 } \
{ -3 30 }} { -3 30 }}
set dev_package_list { \ set dev_package_list { \
@ -102,7 +107,8 @@ set dev_package_list { \
{ ba 16 } \ { ba 16 } \
{ fa 17 } \ { fa 17 } \
{ fs 18 } \ { fs 18 } \
{ fi 19 }} { fi 19 } \
{ vs 20 }}
set xcvr_type_list { \ set xcvr_type_list { \
@ -140,6 +146,7 @@ proc adi_device_spec {cellpath param} {
^xczu {set series_name ultrascale+} ^xczu {set series_name ultrascale+}
^xc.u.p {set series_name ultrascale+} ^xc.u.p {set series_name ultrascale+}
^xc.u {set series_name ultrascale } ^xc.u {set series_name ultrascale }
^xcv[ecmph] {set series_name versal}
default { default {
puts "Undefined fpga technology for \"$part\"!" puts "Undefined fpga technology for \"$part\"!"
exit -1 exit -1