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spi_engine_execution: Merge the SDI lines into one vector 

This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
main
Istvan Csomortani 2020-05-05 14:42:39 +03:00 committed by István Csomortáni
parent 7b3d52436a
commit 4d54c7e2d6
6 changed files with 55 additions and 190 deletions
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1
library/spi_engine/interfaces/spi_master.xml
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@ -10,4 +10,5 @@
<spirit:isAddressable>false</spirit:isAddressable> <spirit:isAddressable>false</spirit:isAddressable>
<spirit:maxMasters>1</spirit:maxMasters> <spirit:maxMasters>1</spirit:maxMasters>
<spirit:maxSlaves>1</spirit:maxSlaves> <spirit:maxSlaves>1</spirit:maxSlaves>
<spirit:description>SPI Engine physical interface</spirit:description>
</spirit:busDefinition> </spirit:busDefinition>

123
library/spi_engine/interfaces/spi_master_rtl.xml
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@ -13,10 +13,12 @@
<spirit:ports> <spirit:ports>
<spirit:port> <spirit:port>
<spirit:logicalName>SCLK</spirit:logicalName> <spirit:logicalName>SCLK</spirit:logicalName>
<spirit:description>SPI clock</spirit:description>
<spirit:wire> <spirit:wire>
<spirit:onMaster> <spirit:onMaster>
<spirit:presence>required</spirit:presence> <spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width> <spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster> </spirit:onMaster>
<spirit:onSlave> <spirit:onSlave>
<spirit:presence>required</spirit:presence> <spirit:presence>required</spirit:presence>
@ -27,150 +29,83 @@
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:logicalName>SDI</spirit:logicalName> <spirit:logicalName>SDI</spirit:logicalName>
<spirit:description>Serial data in</spirit:description>
<spirit:wire> <spirit:wire>
<spirit:onMaster> <spirit:onMaster>
<spirit:presence>required</spirit:presence> <spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction> <spirit:direction>in</spirit:direction>
</spirit:onMaster> </spirit:onMaster>
<spirit:onSlave> <spirit:onSlave>
<spirit:width>1</spirit:width> <spirit:presence>optional</spirit:presence>
</spirit:onSlave> <spirit:direction>out</spirit:direction>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_1</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_2</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_3</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_4</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_5</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_6</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave>
</spirit:wire>
</spirit:port>
<spirit:port>
<spirit:logicalName>SDI_7</spirit:logicalName>
<spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction>
</spirit:onMaster>
<spirit:onSlave>
<spirit:width>1</spirit:width>
</spirit:onSlave> </spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:logicalName>SDO</spirit:logicalName> <spirit:logicalName>SDO</spirit:logicalName>
<spirit:description>Serial data out</spirit:description>
<spirit:wire> <spirit:wire>
<spirit:onMaster> <spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width> <spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster> </spirit:onMaster>
<spirit:onSlave> <spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width> <spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction> <spirit:direction>in</spirit:direction>
</spirit:onSlave> </spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:logicalName>SDO_T</spirit:logicalName> <spirit:logicalName>SDO_T</spirit:logicalName>
<spirit:description>Serial data out three state controle line</spirit:description>
<spirit:wire> <spirit:wire>
<spirit:onMaster> <spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width> <spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster> </spirit:onMaster>
<spirit:onSlave> <spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width> <spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction> <spirit:direction>in</spirit:direction>
</spirit:onSlave> </spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:logicalName>THREE_WIRE</spirit:logicalName> <spirit:logicalName>THREE_WIRE</spirit:logicalName>
<spirit:description>Three wire mode</spirit:description>
<spirit:wire> <spirit:wire>
<spirit:onMaster> <spirit:onMaster>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width> <spirit:width>1</spirit:width>
<spirit:direction>out</spirit:direction>
</spirit:onMaster> </spirit:onMaster>
<spirit:onSlave> <spirit:onSlave>
<spirit:presence>optional</spirit:presence>
<spirit:width>1</spirit:width> <spirit:width>1</spirit:width>
<spirit:direction>in</spirit:direction> <spirit:direction>in</spirit:direction>
</spirit:onSlave> </spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
<spirit:port> <spirit:port>
<spirit:logicalName>CS</spirit:logicalName> <spirit:logicalName>CS</spirit:logicalName>
<spirit:description>Chip select</spirit:description>
<spirit:wire> <spirit:wire>
<spirit:onMaster>
<spirit:presence>required</spirit:presence>
<spirit:direction>out</spirit:direction>
</spirit:onMaster>
<spirit:onSlave> <spirit:onSlave>
<spirit:presence>required</spirit:presence>
<spirit:direction>in</spirit:direction> <spirit:direction>in</spirit:direction>
</spirit:onSlave> </spirit:onSlave>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:wire> </spirit:wire>
</spirit:port> </spirit:port>
</spirit:ports> </spirit:ports>

78
library/spi_engine/spi_engine_execution/spi_engine_execution.v
View File

@ -70,14 +70,7 @@ module spi_engine_execution #(
output reg sclk, output reg sclk,
output reg sdo, output reg sdo,
output reg sdo_t, output reg sdo_t,
input sdi, input [NUM_OF_SDI-1:0] sdi,
input sdi_1,
input sdi_2,
input sdi_3,
input sdi_4,
input sdi_5,
input sdi_6,
input sdi_7,
output reg [NUM_OF_CS-1:0] cs, output reg [NUM_OF_CS-1:0] cs,
output reg three_wire output reg three_wire
); );
@ -146,16 +139,7 @@ reg [7:0] clk_div = DEFAULT_CLK_DIV;
wire sdo_enabled = cmd_d1[8]; wire sdo_enabled = cmd_d1[8];
wire sdi_enabled = cmd_d1[9]; wire sdi_enabled = cmd_d1[9];
// supporting max 8 SDI channel
reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0; reg [(DATA_WIDTH-1):0] data_sdo_shift = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift_1 = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift_2 = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift_3 = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift_4 = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift_5 = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift_6 = 'h0;
reg [(DATA_WIDTH-1):0] data_sdi_shift_7 = 'h0;
reg [4:0] trigger_rx_d = 5'b0; reg [4:0] trigger_rx_d = 5'b0;
@ -415,48 +399,26 @@ assign trigger_rx_s = (SDI_DELAY == 2'b00) ? trigger_rx_d[1] :
(SDI_DELAY == 2'b10) ? trigger_rx_d[3] : (SDI_DELAY == 2'b10) ? trigger_rx_d[3] :
(SDI_DELAY == 2'b11) ? trigger_rx_d[4] : trigger_rx_d[1]; (SDI_DELAY == 2'b11) ? trigger_rx_d[4] : trigger_rx_d[1];
always @(posedge clk) begin // Load the serial data into SDI shift register(s), then link it to the output
if (inst_d1 == CMD_CHIPSELECT) begin // register of the module
data_sdi_shift <= {DATA_WIDTH{1'b0}}; genvar i;
data_sdi_shift_1 <= {DATA_WIDTH{1'b0}}; generate
data_sdi_shift_2 <= {DATA_WIDTH{1'b0}}; for (i=0; i<NUM_OF_SDI; i=i+1) begin: g_sdi_shift_reg
data_sdi_shift_3 <= {DATA_WIDTH{1'b0}};
data_sdi_shift_4 <= {DATA_WIDTH{1'b0}};
data_sdi_shift_5 <= {DATA_WIDTH{1'b0}};
data_sdi_shift_6 <= {DATA_WIDTH{1'b0}};
data_sdi_shift_7 <= {DATA_WIDTH{1'b0}};
end else if (trigger_rx_s == 1'b1) begin
data_sdi_shift <= {data_sdi_shift[(DATA_WIDTH-2):0], sdi};
data_sdi_shift_1 <= {data_sdi_shift_1[(DATA_WIDTH-2):0], sdi_1};
data_sdi_shift_2 <= {data_sdi_shift_2[(DATA_WIDTH-2):0], sdi_2};
data_sdi_shift_3 <= {data_sdi_shift_3[(DATA_WIDTH-2):0], sdi_3};
data_sdi_shift_4 <= {data_sdi_shift_4[(DATA_WIDTH-2):0], sdi_4};
data_sdi_shift_5 <= {data_sdi_shift_5[(DATA_WIDTH-2):0], sdi_5};
data_sdi_shift_6 <= {data_sdi_shift_6[(DATA_WIDTH-2):0], sdi_6};
data_sdi_shift_7 <= {data_sdi_shift_7[(DATA_WIDTH-2):0], sdi_7};
end
end
assign sdi_data = (NUM_OF_SDI == 1) ? data_sdi_shift : reg [DATA_WIDTH-1:0] data_sdi_shift;
(NUM_OF_SDI == 2) ? {data_sdi_shift_1, data_sdi_shift} :
(NUM_OF_SDI == 3) ? {data_sdi_shift_2, data_sdi_shift_1, always @(posedge clk) begin
data_sdi_shift} : if (inst_d1 == CMD_CHIPSELECT) begin
(NUM_OF_SDI == 4) ? {data_sdi_shift_3, data_sdi_shift_2, data_sdi_shift <= {DATA_WIDTH{1'b0}};
data_sdi_shift_1, data_sdi_shift} : end else if (trigger_rx_s == 1'b1) begin
(NUM_OF_SDI == 5) ? {data_sdi_shift_4, data_sdi_shift_3, data_sdi_shift <= {data_sdi_shift[DATA_WIDTH-2:0], sdi[i]};
data_sdi_shift_2, data_sdi_shift_1, end
data_sdi_shift} : end
(NUM_OF_SDI == 6) ? {data_sdi_shift_5, data_sdi_shift_4,
data_sdi_shift_3, data_sdi_shift_2, assign sdi_data[((i+1)*DATA_WIDTH)-1:i*DATA_WIDTH] = data_sdi_shift;
data_sdi_shift_1, data_sdi_shift} :
(NUM_OF_SDI == 7) ? {data_sdi_shift_6, data_sdi_shift_5, end
data_sdi_shift_4, data_sdi_shift_3, endgenerate
data_sdi_shift_2, data_sdi_shift_1,
data_sdi_shift} :
(NUM_OF_SDI == 8) ? {data_sdi_shift_7, data_sdi_shift_6,
data_sdi_shift_5, data_sdi_shift_4,
data_sdi_shift_3, data_sdi_shift_2,
data_sdi_shift_1, data_sdi_shift} : data_sdi_shift;
assign last_sdi_bit = (sdi_counter == word_length-1); assign last_sdi_bit = (sdi_counter == word_length-1);
always @(posedge clk) begin always @(posedge clk) begin

25
library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl
View File

@ -36,13 +36,6 @@ adi_add_bus "spi" "master" \
{ {
{"sclk" "SCLK"} \ {"sclk" "SCLK"} \
{"sdi" "SDI"} \ {"sdi" "SDI"} \
{"sdi_1" "SDI_1"} \
{"sdi_2" "SDI_2"} \
{"sdi_3" "SDI_3"} \
{"sdi_4" "SDI_4"} \
{"sdi_5" "SDI_5"} \
{"sdi_6" "SDI_6"} \
{"sdi_7" "SDI_7"} \
{"sdo" "SDO"} \ {"sdo" "SDO"} \
{"sdo_t" "SDO_T"} \ {"sdo_t" "SDO_T"} \
{"three_wire" "THREE_WIRE"} \ {"three_wire" "THREE_WIRE"} \
@ -50,22 +43,4 @@ adi_add_bus "spi" "master" \
} }
adi_add_bus_clock "clk" "spi" "resetn" adi_add_bus_clock "clk" "spi" "resetn"
foreach port {"sdi_1" "sdi_2" "sdi_3" "sdi_4" "sdi_5" "sdi_6" "sdi_7"} {
set_property DRIVER_VALUE "0" [ipx::get_ports $port]
}
adi_set_ports_dependency "sdi_1" \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) > 1)"
adi_set_ports_dependency "sdi_2" \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) > 2)"
adi_set_ports_dependency "sdi_3" \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) > 3)"
adi_set_ports_dependency "sdi_4" \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) > 4)"
adi_set_ports_dependency "sdi_5" \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) > 5)"
adi_set_ports_dependency "sdi_6" \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) > 6)"
adi_set_ports_dependency "sdi_7" \
"(spirit:decode(id('MODELPARAM_VALUE.NUM_OF_SDI')) > 7)"
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]

9
projects/ad7134_fmc/zed/system_top.v
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@ -217,14 +217,7 @@ module system_top (
.spi0_sdo_o (ad713x_spi_sdo), .spi0_sdo_o (ad713x_spi_sdo),
.ad713x_di_sdo (), .ad713x_di_sdo (),
.ad713x_di_sdo_t (), .ad713x_di_sdo_t (),
.ad713x_di_sdi (ad713x_din[0]), .ad713x_di_sdi (ad713x_din),
.ad713x_di_sdi_1 (ad713x_din[1]),
.ad713x_di_sdi_2 (ad713x_din[2]),
.ad713x_di_sdi_3 (ad713x_din[3]),
.ad713x_di_sdi_4 (ad713x_din[4]),
.ad713x_di_sdi_5 (ad713x_din[5]),
.ad713x_di_sdi_6 (ad713x_din[6]),
.ad713x_di_sdi_7 (ad713x_din[7]),
.ad713x_di_cs (), .ad713x_di_cs (),
.ad713x_di_sclk (ad713x_dclk), .ad713x_di_sclk (ad713x_dclk),
.ad713x_odr (ad713x_odr), .ad713x_odr (ad713x_odr),

3
projects/ad738x_fmc/zed/system_top.v
View File

@ -174,8 +174,7 @@ module system_top (
.iic_mux_sda_t (iic_mux_sda_t_s), .iic_mux_sda_t (iic_mux_sda_t_s),
.spi_sdo (spi_sdo), .spi_sdo (spi_sdo),
.spi_sdo_t (), .spi_sdo_t (),
.spi_sdi (spi_sdia), .spi_sdi ({spi_sdib, spi_sdia}),
.spi_sdi_1 (spi_sdib),
.spi_cs (spi_cs), .spi_cs (spi_cs),
.spi_sclk (spi_sclk), .spi_sclk (spi_sclk),
.otg_vbusoc (otg_vbusoc), .otg_vbusoc (otg_vbusoc),