daq2: rebase conflicts
Rejeesh Kutty
parent
43cdafe1e2
commit
4eeb50114f
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@ -69,6 +69,12 @@ if {$sys_zynq == 0} {
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set adc_dsync [create_bd_port -dir I adc_dsync]
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set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata]
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if {$sys_zynq == 1} {
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set DDR3 [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR3]
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set sys_clk [create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk]
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}
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# dac peripherals
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set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core]
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@ -106,7 +112,7 @@ if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.C_LANES {4}] $axi_ad9680_jesd
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set axi_ad9680_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9680_dma]
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_SRC {1}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.PCORE_ID {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9680_dma
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@ -116,8 +122,13 @@ if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9680_dma
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set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9680_dma
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if {$sys_zynq == 1} {
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p_plddr3_fifo [current_bd_instance .] axi_ad9680_fifo 128
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}
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if {$sys_zynq == 1} {
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@ -129,6 +140,10 @@ if {$sys_zynq == 1} {
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set axi_daq2_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq2_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {4}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_daq2_gt
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set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_daq2_gt
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if {$sys_zynq == 1} {
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@ -177,13 +192,38 @@ if {$sys_zynq == 1} {
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set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {43}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property LEFT 42 [get_bd_ports GPIO_I]
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set_property LEFT 42 [get_bd_ports GPIO_O]
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set_property LEFT 42 [get_bd_ports GPIO_T]
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set_property LEFT 43 [get_bd_ports GPIO_I]
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set_property LEFT 43 [get_bd_ports GPIO_O]
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set_property LEFT 43 [get_bd_ports GPIO_T]
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}
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# connections (pl ddr3)
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if {$sys_zynq == 1} {
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connect_bd_intf_net -intf_net DDR3 [get_bd_intf_ports DDR3] [get_bd_intf_pins axi_ad9680_fifo/DDR3]
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connect_bd_intf_net -intf_net sys_clk [get_bd_intf_ports sys_clk] [get_bd_intf_pins axi_ad9680_fifo/sys_clk]
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}
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# fmc dma clocks
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if {$sys_zynq == 1} {
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set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset]
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set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk]
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connect_bd_net -net sys_fmc_dma_async_reset \
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[get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \
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[get_bd_pins sys_ps7/FCLK_RESET2_N]
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connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
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}
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# connections (spi and gpio)
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@ -293,18 +333,29 @@ if {$sys_zynq == 0} {
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connect_bd_net -net axi_daq2_gt_rx_ip_sof [get_bd_pins axi_daq2_gt/rx_ip_sof] [get_bd_pins axi_ad9680_jesd/rx_start_of_frame]
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connect_bd_net -net axi_daq2_gt_rx_ip_data [get_bd_pins axi_daq2_gt/rx_ip_data] [get_bd_pins axi_ad9680_jesd/rx_tdata]
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connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins axi_daq2_gt/rx_data] [get_bd_pins axi_ad9680_core/rx_data]
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connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_dma/fifo_wr_clk]
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if {$sys_zynq == 1} {
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connect_bd_net -net axi_daq2_gt_rx_rst [get_bd_pins axi_ad9680_fifo/adc_rst] [get_bd_pins axi_daq2_gt/rx_rst]
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connect_bd_net -net sys_fmc_dma_resetn [get_bd_pins axi_ad9680_fifo/dma_rstn] $sys_fmc_dma_resetn_source
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connect_bd_net -net axi_ad9680_adc_clk [get_bd_pins axi_ad9680_core/adc_clk] [get_bd_pins axi_ad9680_fifo/adc_clk]
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connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_fifo/adc_wovf]
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connect_bd_net -net axi_ad9680_adc_enable_0 [get_bd_pins axi_ad9680_core/adc_enable_0] [get_bd_ports adc_enable_0]
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connect_bd_net -net axi_ad9680_adc_valid_0 [get_bd_pins axi_ad9680_core/adc_valid_0] [get_bd_ports adc_valid_0]
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connect_bd_net -net axi_ad9680_adc_data_0 [get_bd_pins axi_ad9680_core/adc_data_0] [get_bd_ports adc_data_0]
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connect_bd_net -net axi_ad9680_adc_enable_1 [get_bd_pins axi_ad9680_core/adc_enable_1] [get_bd_ports adc_enable_1]
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connect_bd_net -net axi_ad9680_adc_valid_1 [get_bd_pins axi_ad9680_core/adc_valid_1] [get_bd_ports adc_valid_1]
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connect_bd_net -net axi_ad9680_adc_data_1 [get_bd_pins axi_ad9680_core/adc_data_1] [get_bd_ports adc_data_1]
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connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_dma/fifo_wr_en]
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connect_bd_net -net axi_ad9680_adc_dsync [get_bd_ports adc_dsync] [get_bd_pins axi_ad9680_dma/fifo_wr_sync]
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connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_dma/fifo_wr_din]
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connect_bd_net -net axi_ad9680_adc_dovf [get_bd_pins axi_ad9680_core/adc_dovf] [get_bd_pins axi_ad9680_dma/fifo_wr_overflow]
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connect_bd_net -net axi_ad9680_adc_dwr [get_bd_ports adc_dwr] [get_bd_pins axi_ad9680_fifo/adc_wr]
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connect_bd_net -net axi_ad9680_adc_ddata [get_bd_ports adc_ddata] [get_bd_pins axi_ad9680_fifo/adc_wdata]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_ad9680_fifo/dma_clk] [get_bd_pins axi_ad9680_dma/s_axis_aclk]
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connect_bd_net -net axi_ad9680_dma_dvalid [get_bd_pins axi_ad9680_fifo/dma_wvalid] [get_bd_pins axi_ad9680_dma/s_axis_valid]
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connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready]
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connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data]
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connect_bd_net -net axi_ad9680_dma_irq [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13]
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}
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# dac/adc clocks
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@ -396,21 +447,6 @@ if {$sys_zynq == 0} {
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# memory interconnects share the same clock (fclk2)
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if {$sys_zynq == 1} {
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set sys_fmc_dma_sync_reset [create_bd_cell -type ip -vlnv analog.com:user:util_sync_reset:1.0 sys_fmc_dma_sync_reset]
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set sys_fmc_dma_clk_source [get_bd_pins sys_ps7/FCLK_CLK2]
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set sys_fmc_dma_resetn_source [get_bd_pins sys_fmc_dma_sync_reset/sync_resetn]
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connect_bd_net -net sys_fmc_dma_clk [get_bd_pins sys_fmc_dma_sync_reset/clk]
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connect_bd_net -net sys_fmc_dma_async_reset \
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[get_bd_pins sys_fmc_dma_sync_reset/async_resetn] \
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[get_bd_pins sys_ps7/FCLK_RESET2_N]
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connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source
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connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source
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}
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# interconnect (mem/dac)
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if {$sys_zynq == 0} {
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@ -458,11 +494,10 @@ if {$sys_zynq == 0} {
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set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_rx_mon]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE0_WIDTH {334}] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE1_WIDTH {6}] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE2_WIDTH {128}] $ila_jesd_rx_mon
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set_property -dict [list CONFIG.C_PROBE3_WIDTH {128}] $ila_jesd_rx_mon
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connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins axi_daq2_gt/rx_mon_data]
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connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins axi_daq2_gt/rx_mon_trigger]
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@ -470,7 +505,6 @@ if {$sys_zynq == 0} {
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connect_bd_net -net axi_daq2_gt_rx_mon_data [get_bd_pins ila_jesd_rx_mon/PROBE0]
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connect_bd_net -net axi_daq2_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon/PROBE1]
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connect_bd_net -net axi_daq2_gt_rx_data [get_bd_pins ila_jesd_rx_mon/PROBE2]
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connect_bd_net -net axi_ad9680_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
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set ila_jesd_tx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_jesd_tx_mon]
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set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_tx_mon
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@ -511,5 +545,7 @@ if {$sys_zynq == 0} {
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create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9144_dma/m_src_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm
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create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_ad9680_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm
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create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_daq2_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm
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create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces axi_ad9680_fifo/axi_fifo2s/axi] [get_bd_addr_segs axi_ad9680_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr
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}
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