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Merge branch 'master' into devel

main
Rejeesh Kutty 2014-06-25 13:07:12 -04:00
parent 985ace533e e38813fa9f
commit 4f5d163fcc
9 changed files with 200 additions and 213 deletions
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68
library/axi_fifo2s/axi_fifo2s.v
View File

@ -103,7 +103,8 @@ module axi_fifo2s (
// transfer request
axi_xfer_req);
axi_xfer_req,
axi_xfer_status);
// parameters
@ -111,6 +112,7 @@ module axi_fifo2s (
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
// fifo interface
@ -172,15 +174,58 @@ module axi_fifo2s (
input [DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// transfer request
// transfer request & status
input axi_xfer_req;
output [ 4:0] axi_xfer_status;
// internal registers
reg [ 4:0] axi_xfer_status = 'd0;
reg [ 4:0] axi_status_cnt = 'd0;
reg m_wovf_m = 'd0;
reg m_wovf = 'd0;
// internal signals
wire axi_rd_req_s;
wire [ 31:0] axi_rd_addr_s;
wire axi_rd_status_s;
wire axi_dwovf_s;
wire axi_dwunf_s;
wire axi_werror_s;
wire axi_rerror_s;
// status signals
always @(posedge axi_clk) begin
if (axi_resetn == 1'b0) begin
axi_xfer_status <= 'd0;
axi_status_cnt <= 'd0;
end else begin
axi_xfer_status[4] <= axi_rerror_s;
axi_xfer_status[3] <= axi_werror_s;
axi_xfer_status[2] <= axi_dwunf_s;
axi_xfer_status[1] <= axi_dwovf_s;
axi_xfer_status[0] <= axi_mwovf;
if (axi_xfer_status == 0) begin
if (axi_status_cnt[4] == 1'b1) begin
axi_status_cnt <= axi_status_cnt + 1'b1;
end
end else begin
axi_status_cnt <= 5'd10;
end
end
end
always @(posedge m_clk) begin
if (m_rst == 1'b1) begin
m_wovf_m <= 'd0;
m_wovf <= 'd0;
end else begin
m_wovf_m <= axi_status_cnt[4];
m_wovf <= m_wovf_m;
end
end
// instantiations
@ -188,17 +233,16 @@ module axi_fifo2s (
.DATA_WIDTH (DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS))
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
i_wr (
.axi_xfer_req (axi_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.axi_rd_status (axi_rd_status_s),
.m_rst (m_rst),
.m_clk (m_clk),
.m_wr (m_wr),
.m_wdata (m_wdata),
.m_wovf (m_wovf),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_awvalid (axi_awvalid),
@ -223,17 +267,21 @@ module axi_fifo2s (
.axi_bid (axi_bid),
.axi_bresp (axi_bresp),
.axi_buser (axi_buser),
.axi_bready (axi_bready));
.axi_bready (axi_bready),
.axi_dwovf (axi_dwovf_s),
.axi_dwunf (axi_dwunf_s),
.axi_werror (axi_werror_s));
axi_fifo2s_rd #(
.DATA_WIDTH (DATA_WIDTH),
.AXI_SIZE (AXI_SIZE),
.AXI_LENGTH (AXI_LENGTH))
.AXI_LENGTH (AXI_LENGTH),
.AXI_ADDRESS (AXI_ADDRESS),
.AXI_ADDRLIMIT (AXI_ADDRLIMIT))
i_rd (
.axi_xfer_req (axi_xfer_req),
.axi_rd_req (axi_rd_req_s),
.axi_rd_addr (axi_rd_addr_s),
.axi_rd_status (axi_rd_status_s),
.axi_clk (axi_clk),
.axi_resetn (axi_resetn),
.axi_arvalid (axi_arvalid),
@ -255,9 +303,9 @@ module axi_fifo2s (
.axi_rlast (axi_rlast),
.axi_rdata (axi_rdata),
.axi_rready (axi_rready),
.axi_rerror (axi_rerror_s),
.axi_mwr (axi_mwr),
.axi_mwdata (axi_mwdata),
.axi_mwovf (axi_mwovf),
.axi_mwpfull (axi_mwpfull));
endmodule

140
library/axi_fifo2s/axi_fifo2s_rd.v
View File

@ -46,7 +46,6 @@ module axi_fifo2s_rd (
axi_xfer_req,
axi_rd_req,
axi_rd_addr,
axi_rd_status,
// axi interface
@ -72,11 +71,14 @@ module axi_fifo2s_rd (
axi_rdata,
axi_rready,
// axi status
axi_rerror,
// fifo interface
axi_mwr,
axi_mwdata,
axi_mwovf,
axi_mwpfull);
// parameters
@ -84,6 +86,9 @@ module axi_fifo2s_rd (
parameter DATA_WIDTH = 32;
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_AWINCR = (AXI_LENGTH * DATA_WIDTH)/8;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
@ -92,7 +97,6 @@ module axi_fifo2s_rd (
input axi_xfer_req;
input axi_rd_req;
input [ 31:0] axi_rd_addr;
output axi_rd_status;
// axi interface
@ -118,26 +122,22 @@ module axi_fifo2s_rd (
input [DATA_WIDTH-1:0] axi_rdata;
output axi_rready;
// axi status
output axi_rerror;
// fifo interface
output axi_mwr;
output [DATA_WIDTH-1:0] axi_mwdata;
input axi_mwovf;
input axi_mwpfull;
// internal registers
reg [ 5:0] axi_waddr = 'd0;
reg [ 5:0] axi_raddr = 'd0;
reg axi_rd = 'd0;
reg axi_rd_d = 'd0;
reg [ 31:0] axi_rdata_d = 'd0;
reg [ 5:0] axi_addr_diff = 'd0;
reg axi_almost_full = 'd0;
reg axi_unf = 'd0;
reg axi_almost_empty = 'd0;
reg axi_ovf = 'd0;
reg axi_arerror = 'd0;
reg axi_rd_active = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg axi_arvalid = 'd0;
reg [ 31:0] axi_araddr = 'd0;
reg axi_mwr = 'd0;
@ -145,82 +145,33 @@ module axi_fifo2s_rd (
reg axi_rready = 'd0;
reg axi_rerror = 'd0;
reg axi_reset = 'd0;
reg axi_rd_status = 'd0;
// internal signals
wire axi_wr_s;
wire [ 31:0] axi_wdata_s;
wire axi_arready_s;
wire axi_fifo_ready_s;
wire axi_rd_s;
wire [ 6:0] axi_addr_diff_s;
wire [ 31:0] axi_rdata_s;
wire axi_ready_s;
// queue requests
// read is way too slow- buffer mode
assign axi_wr_s = axi_rd_req;
assign axi_wdata_s = axi_rd_addr;
assign axi_ready_s = (~axi_arvalid | axi_arready) & ~axi_mwpfull;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_waddr <= 'd0;
end else begin
if (axi_wr_s == 1'b1) begin
axi_waddr <= axi_waddr + 1'b1;
end
end
end
// read queue
assign axi_arready_s = ~axi_arvalid | axi_arready;
assign axi_fifo_ready_s = ~axi_xfer_req | ~axi_mwpfull;
assign axi_rd_s = (axi_waddr == axi_raddr) ? 1'b0 : (axi_arready_s & axi_fifo_ready_s);
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_raddr <= 'd0;
axi_rd <= 'd0;
axi_rd_d <= 'd0;
axi_rdata_d <= 'd0;
axi_rd_active <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
end else begin
if (axi_rd_s == 1'b1) begin
axi_raddr <= axi_raddr + 1'b1;
if (axi_rd_active == 1'b1) begin
axi_rd <= 1'b0;
if (axi_rlast == 1'b1) begin
axi_rd_active <= 1'b0;
end
axi_rd <= axi_rd_s;
axi_rd_d <= axi_rd;
axi_rdata_d <= axi_rdata_s;
end
end
// overflow (no underflow possible)
assign axi_addr_diff_s = {1'b1, axi_waddr} - axi_raddr;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_addr_diff <= 'd0;
axi_almost_full <= 'd0;
axi_unf <= 'd0;
axi_almost_empty <= 'd0;
axi_ovf <= 'd0;
end else begin
axi_addr_diff <= axi_addr_diff_s[5:0];
if (axi_addr_diff > BUF_THRESHOLD_HI) begin
axi_almost_full <= 1'b1;
axi_unf <= axi_almost_empty;
end else begin
axi_almost_full <= 1'b0;
axi_unf <= 1'b0;
end
if (axi_addr_diff < BUF_THRESHOLD_LO) begin
axi_almost_empty <= 1'b1;
axi_ovf <= axi_almost_full;
end else begin
axi_almost_empty <= 1'b0;
axi_ovf <= 1'b0;
end else if ((axi_ready_s == 1'b1) && (axi_araddr < axi_rd_addr)) begin
axi_rd <= 1'b1;
axi_rd_active <= 1'b1;
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], axi_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
end
end
@ -238,22 +189,22 @@ module axi_fifo2s_rd (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_arerror <= 'd0;
axi_arvalid <= 'd0;
axi_araddr <= 'd0;
end else begin
axi_arerror <= axi_rd_d & axi_arvalid;
if (axi_arvalid == 1'b1) begin
if (axi_arready == 1'b1) begin
axi_arvalid <= 1'b0;
end
end else begin
if (axi_rd_d == 1'b1) begin
if (axi_rd == 1'b1) begin
axi_arvalid <= 1'b1;
end
end
if ((axi_rd_d == 1'b1) && (axi_arvalid == 1'b0)) begin
axi_araddr <= axi_rdata_d;
if (axi_xfer_init == 1'b1) begin
axi_araddr <= AXI_ADDRESS;
end else if ((axi_arvalid == 1'b1) && (axi_arready == 1'b1)) begin
axi_araddr <= axi_araddr + AXI_AWINCR;
end
end
end
@ -268,7 +219,7 @@ module axi_fifo2s_rd (
end else begin
axi_mwr <= axi_rvalid & axi_rready;
axi_mwdata <= axi_rdata;
axi_rready <= axi_fifo_ready_s;
axi_rready <= 1'b1;
end
end
@ -290,27 +241,6 @@ module axi_fifo2s_rd (
end
end
// combined status
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_rd_status <= 'd0;
end else begin
axi_rd_status <= axi_mwovf | axi_ovf | axi_unf | axi_arerror | axi_rerror;
end
end
// buffer
ad_mem #(.DATA_WIDTH(32), .ADDR_WIDTH(6)) i_mem (
.clka (axi_clk),
.wea (axi_wr_s),
.addra (axi_waddr),
.dina (axi_wdata_s),
.clkb (axi_clk),
.addrb (axi_raddr),
.doutb (axi_rdata_s));
endmodule
// ***************************************************************************

115
library/axi_fifo2s/axi_fifo2s_wr.v
View File

@ -46,7 +46,6 @@ module axi_fifo2s_wr (
axi_xfer_req,
axi_rd_req,
axi_rd_addr,
axi_rd_status,
// fifo interface
@ -54,7 +53,6 @@ module axi_fifo2s_wr (
m_clk,
m_wr,
m_wdata,
m_wovf,
// axi interface
@ -82,7 +80,13 @@ module axi_fifo2s_wr (
axi_bid,
axi_bresp,
axi_buser,
axi_bready);
axi_bready,
// axi status
axi_dwovf,
axi_dwunf,
axi_werror);
// parameters
@ -90,6 +94,7 @@ module axi_fifo2s_wr (
parameter AXI_SIZE = 2;
parameter AXI_LENGTH = 16;
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRLIMIT = 32'h00000000;
localparam AXI_AWINCR = (AXI_LENGTH * DATA_WIDTH)/8;
localparam BUF_THRESHOLD_LO = 6'd3;
localparam BUF_THRESHOLD_HI = 6'd60;
@ -99,7 +104,6 @@ module axi_fifo2s_wr (
input axi_xfer_req;
output axi_rd_req;
output [ 31:0] axi_rd_addr;
input axi_rd_status;
// fifo interface
@ -107,7 +111,6 @@ module axi_fifo2s_wr (
input m_clk;
input m_wr;
input [DATA_WIDTH-1:0] m_wdata;
output m_wovf;
// axi interface
@ -137,15 +140,24 @@ module axi_fifo2s_wr (
input [ 3:0] axi_buser;
output axi_bready;
// axi status
output axi_dwovf;
output axi_dwunf;
output axi_werror;
// internal registers
reg [ 2:0] m_xfer_req_m = 'd0;
reg m_xfer_init = 'd0;
reg m_xfer_limit = 'd0;
reg m_xfer_enable = 'd0;
reg [ 31:0] m_xfer_addr = 'd0;
reg [ 5:0] m_waddr = 'd0;
reg [ 5:0] m_waddr_g = 'd0;
reg m_rel_enable = 'd0;
reg m_rel_toggle = 'd0;
reg [ 5:0] m_rel_waddr = 'd0;
reg [ 2:0] m_status_m = 'd0;
reg m_wovf = 'd0;
reg [ 2:0] axi_rel_toggle_m = 'd0;
reg [ 5:0] axi_rel_waddr = 'd0;
reg [ 5:0] axi_waddr_m1 = 'd0;
@ -153,11 +165,11 @@ module axi_fifo2s_wr (
reg [ 5:0] axi_waddr = 'd0;
reg [ 5:0] axi_addr_diff = 'd0;
reg axi_almost_full = 'd0;
reg axi_unf = 'd0;
reg axi_dwunf = 'd0;
reg axi_almost_empty = 'd0;
reg axi_ovf = 'd0;
reg [ 2:0] axi_xfer_enable_m = 'd0;
reg axi_xfer_enable = 'd0;
reg axi_dwovf = 'd0;
reg [ 2:0] axi_xfer_req_m = 'd0;
reg axi_xfer_init = 'd0;
reg [ 5:0] axi_raddr = 'd0;
reg axi_rd = 'd0;
reg axi_rlast = 'd0;
@ -166,13 +178,10 @@ module axi_fifo2s_wr (
reg [DATA_WIDTH-1:0] axi_rdata_d = 'd0;
reg axi_rd_req = 'd0;
reg [ 31:0] axi_rd_addr = 'd0;
reg axi_awerror = 'd0;
reg axi_awvalid = 'd0;
reg [ 31:0] axi_awaddr = 'd0;
reg axi_werror = 'd0;
reg axi_reset = 'd0;
reg [ 4:0] axi_status_cnt = 'd0;
reg axi_status = 'd0;
// internal signals
@ -182,7 +191,6 @@ module axi_fifo2s_wr (
wire axi_rd_s;
wire axi_req_s;
wire axi_rlast_s;
wire axi_status_s;
wire [DATA_WIDTH-1:0] axi_rdata_s;
// binary to grey conversion
@ -223,16 +231,33 @@ module axi_fifo2s_wr (
if (m_rst == 1'b1) begin
m_waddr <= 'd0;
m_waddr_g <= 'd0;
m_xfer_req_m <= 'd0;
m_xfer_init <= 'd0;
m_xfer_limit <= 'd0;
m_xfer_enable <= 'd0;
m_xfer_addr <= 'd0;
m_rel_enable <= 'd0;
m_rel_toggle <= 'd0;
m_rel_waddr <= 'd0;
m_status_m <= 'd0;
m_wovf <= 'd0;
end else begin
if (m_wr == 1'b1) begin
if ((m_wr == 1'b1) && (m_xfer_enable == 1'b1)) begin
m_waddr <= m_waddr + 1'b1;
end
m_waddr_g <= b2g(m_waddr);
m_xfer_req_m <= {m_xfer_req_m[1:0], axi_xfer_req};
m_xfer_init <= m_xfer_req_m[1] & ~m_xfer_req_m[2];
if (m_xfer_init == 1'b1) begin
m_xfer_limit <= 1'd1;
end else if (m_xfer_addr >= AXI_ADDRLIMIT) begin
m_xfer_limit <= 1'd0;
end
if (m_xfer_init == 1'b1) begin
m_xfer_enable <= 1'b1;
m_xfer_addr <= AXI_ADDRESS;
end else if ((m_waddr[1:0] == 2'h3) && (m_wr == 1'b1)) begin
m_xfer_enable <= m_xfer_req_m[2] & m_xfer_limit;
m_xfer_addr <= m_xfer_addr + AXI_AWINCR;
end
if (m_waddr[1:0] == 2'h3) begin
m_rel_enable <= m_wr;
end else begin
@ -242,8 +267,6 @@ module axi_fifo2s_wr (
m_rel_toggle <= ~m_rel_toggle;
m_rel_waddr <= m_waddr;
end
m_status_m <= {m_status_m[1:0], axi_status};
m_wovf <= m_status_m[2];
end
end
@ -277,24 +300,24 @@ module axi_fifo2s_wr (
if (axi_resetn == 1'b0) begin
axi_addr_diff <= 'd0;
axi_almost_full <= 'd0;
axi_unf <= 'd0;
axi_dwunf <= 'd0;
axi_almost_empty <= 'd0;
axi_ovf <= 'd0;
axi_dwovf <= 'd0;
end else begin
axi_addr_diff <= axi_addr_diff_s[5:0];
if (axi_addr_diff > BUF_THRESHOLD_HI) begin
axi_almost_full <= 1'b1;
axi_unf <= axi_almost_empty;
axi_dwunf <= axi_almost_empty;
end else begin
axi_almost_full <= 1'b0;
axi_unf <= 1'b0;
axi_dwunf <= 1'b0;
end
if (axi_addr_diff < BUF_THRESHOLD_LO) begin
axi_almost_empty <= 1'b1;
axi_ovf <= axi_almost_full;
axi_dwovf <= axi_almost_full;
end else begin
axi_almost_empty <= 1'b0;
axi_ovf <= 1'b0;
axi_dwovf <= 1'b0;
end
end
end
@ -303,20 +326,18 @@ module axi_fifo2s_wr (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_xfer_enable_m <= 'd0;
axi_xfer_enable <= 'd0;
axi_xfer_req_m <= 'd0;
axi_xfer_init <= 'd0;
end else begin
axi_xfer_enable_m <= {axi_xfer_enable_m[1:0], axi_xfer_req};
if (axi_rel_toggle_s == 1'b1) begin
axi_xfer_enable <= axi_xfer_enable_m[2];
end
axi_xfer_req_m <= {axi_xfer_req_m[1:0], axi_xfer_req};
axi_xfer_init <= axi_xfer_req_m[1] & ~axi_xfer_req_m[2];
end
end
// read is initiated if xfer enabled
assign axi_wready_s = ~axi_wvalid | axi_wready;
assign axi_rd_s = (axi_rel_waddr == axi_raddr) ? 1'b0 : (axi_wready_s & axi_xfer_enable);
assign axi_rd_s = (axi_rel_waddr == axi_raddr) ? 1'b0 : axi_wready_s;
assign axi_req_s = (axi_raddr[1:0] == 2'h0) ? axi_rd_s : 1'b0;
assign axi_rlast_s = (axi_raddr[1:0] == 2'h3) ? axi_rd_s : 1'b0;
@ -329,9 +350,7 @@ module axi_fifo2s_wr (
axi_rlast_d <= 'd0;
axi_rdata_d <= 'd0;
end else begin
if (axi_xfer_enable == 1'b0) begin
axi_raddr <= axi_rel_waddr;
end else if (axi_rd_s == 1'b1) begin
if (axi_rd_s == 1'b1) begin
axi_raddr <= axi_raddr + 1'b1;
end
axi_rd <= axi_rd_s;
@ -350,7 +369,7 @@ module axi_fifo2s_wr (
axi_rd_addr <= 'd0;
end else begin
axi_rd_req <= axi_rlast_s;
if (axi_xfer_enable == 1'b0) begin
if (axi_xfer_init == 1'b1) begin
axi_rd_addr <= AXI_ADDRESS;
end else if (axi_rd_req == 1'b1) begin
axi_rd_addr <= axi_rd_addr + AXI_AWINCR;
@ -372,11 +391,9 @@ module axi_fifo2s_wr (
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_awerror <= 'd0;
axi_awvalid <= 'd0;
axi_awaddr <= 'd0;
end else begin
axi_awerror <= axi_req_s & axi_awvalid;
if (axi_awvalid == 1'b1) begin
if (axi_awready == 1'b1) begin
axi_awvalid <= 1'b0;
@ -386,7 +403,7 @@ module axi_fifo2s_wr (
axi_awvalid <= 1'b1;
end
end
if (axi_xfer_enable == 1'b0) begin
if (axi_xfer_init == 1'b1) begin
axi_awaddr <= AXI_ADDRESS;
end else if ((axi_awvalid == 1'b1) && (axi_awready == 1'b1)) begin
axi_awaddr <= axi_awaddr + AXI_AWINCR;
@ -421,24 +438,6 @@ module axi_fifo2s_wr (
end
end
// combined status
assign axi_status_s = axi_ovf | axi_unf | axi_awerror | axi_werror | axi_rd_status;
always @(posedge axi_clk or negedge axi_resetn) begin
if (axi_resetn == 1'b0) begin
axi_status_cnt <= 'd0;
axi_status <= 'd0;
end else begin
if (axi_status_s == 1'b1) begin
axi_status_cnt <= 5'h1f;
end else if (axi_status_cnt[4] == 1'b1) begin
axi_status_cnt <= axi_status_cnt + 1'b1;
end
axi_status <= axi_status_cnt[4];
end
end
// interface handler
ad_axis_inf_rx #(.DATA_WIDTH(DATA_WIDTH)) i_axis_inf (

2
library/util_rfifo/util_rfifo.v
View File

@ -126,7 +126,7 @@ module util_rfifo (
// read is non-destructive
assign fifo_rd = m_rd;
assign m_runf_s = s_runf | fifo_runf | fifo_rempty;
assign m_runf_s = s_runf | fifo_runf;
always @(posedge m_clk) begin
m_runf_m1 <= m_runf_s;

2
library/util_wfifo/util_wfifo.v
View File

@ -110,7 +110,7 @@ module util_wfifo (
// write is pass through
assign fifo_wr = m_wr;
assign m_wovf_s = s_wovf | fifo_wfull | fifo_wovf;
assign m_wovf_s = s_wovf | fifo_wovf;
genvar m;
generate

6
projects/ad9625_fmc/zc706/system_bd.tcl
View File

@ -28,6 +28,7 @@ connect_bd_net -net axi_ad9625_adc_dwr [get_bd_pins axi_ad9625_core/adc_dwr
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins axi_ad9625_core/adc_ddata] [get_bd_pins plddr3_fifo/adc_wdata]
connect_bd_net -net axi_ad9625_adc_dovf [get_bd_pins axi_ad9625_core/adc_dovf] [get_bd_pins plddr3_fifo/adc_wovf]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins axi_ad9625_core/adc_enable] [get_bd_pins plddr3_fifo/axi_xfer_req]
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins plddr3_fifo/dma_clk] [get_bd_pins axi_ad9625_dma/fifo_wr_clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins plddr3_fifo/dma_wr] [get_bd_pins axi_ad9625_dma/fifo_wr_en]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins plddr3_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/fifo_wr_din]
@ -37,15 +38,18 @@ connect_bd_net -net axi_ad9625_adc_dsync [get_bd_pins axi_ad9625_core/adc_dsy
connect_bd_net -net axi_ad9625_adc_ddata [get_bd_pins ila_jesd_rx_mon/PROBE3]
set ila_dma_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_dma_mon]
set_property -dict [list CONFIG.C_NUM_OF_PROBES {3}] $ila_dma_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {64}] $ila_dma_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {5}] $ila_dma_mon
connect_bd_net -net axi_ad9625_dma_clk [get_bd_pins ila_dma_mon/clk]
connect_bd_net -net axi_ad9625_dma_dwr [get_bd_pins ila_dma_mon/probe0]
connect_bd_net -net axi_ad9625_adc_enable [get_bd_pins ila_dma_mon/probe1]
connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins ila_dma_mon/probe2]
connect_bd_net -net axi_xfer_status [get_bd_pins ila_dma_mon/probe3] [get_bd_pins plddr3_fifo/axi_xfer_status]
create_bd_addr_seg -range 0x40000000 -offset 0x80000000 [get_bd_addr_spaces plddr3_fifo/axi_fifo2s/axi] [get_bd_addr_segs plddr3_fifo/axi_ddr_cntrl/memmap/memaddr] SEG_axi_ddr_cntrl_memaddr

4
projects/common/zc706/zc706_system_mig.prj
View File

@ -23,8 +23,8 @@
<VccAuxIO>2.0V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>200</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<UIExtraClocks>1</UIExtraClocks>
<MMCMClkOut0> 6.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>

41
projects/common/zc706/zc706_system_plddr3.tcl
View File

@ -18,6 +18,7 @@ proc p_plddr3_fifo {p_name m_name m_width} {
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_clk
create_bd_pin -dir I axi_xfer_req
create_bd_pin -dir O -from 4 -to 0 axi_xfer_status
create_bd_pin -dir I adc_rst
create_bd_pin -dir I -type clk adc_clk
@ -53,10 +54,11 @@ proc p_plddr3_fifo {p_name m_name m_width} {
set_property -dict [list CONFIG.Output_Data_Width {64}] $rfifo_mem
set_property -dict [list CONFIG.Overflow_Flag {true}] $rfifo_mem
set_property -dict [list CONFIG.Programmable_Full_Type {Single_Programmable_Full_Threshold_Constant}] $rfifo_mem
set_property -dict [list CONFIG.Full_Threshold_Assert_Value {1000}] $rfifo_mem
set_property -dict [list CONFIG.Full_Threshold_Assert_Value {800}] $rfifo_mem
set axi_fifo2s [create_bd_cell -type ip -vlnv analog.com:user:axi_fifo2s:1.0 axi_fifo2s]
set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_fifo2s
set_property -dict [list CONFIG.AXI_ADDRLIMIT {0xa0000000}] $axi_fifo2s
set_property -dict [list CONFIG.AXI_LENGTH {4}] $axi_fifo2s
set_property -dict [list CONFIG.AXI_SIZE {6}] $axi_fifo2s
set_property -dict [list CONFIG.DATA_WIDTH {512}] $axi_fifo2s
@ -76,35 +78,39 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net adc_clk [get_bd_pins adc_clk]
connect_bd_net -net adc_clk [get_bd_pins wfifo_ctl/m_clk]
connect_bd_net -net adc_clk [get_bd_pins wfifo_mem/wr_clk]
connect_bd_net -net adc_wr [get_bd_pins adc_wr] [get_bd_pins wfifo_ctl/m_wr]
connect_bd_net -net adc_wdata [get_bd_pins adc_wdata] [get_bd_pins wfifo_ctl/m_wdata]
connect_bd_net -net adc_wovf [get_bd_pins adc_wovf] [get_bd_pins wfifo_ctl/m_wovf]
connect_bd_net -net axi_xfer_req [get_bd_pins axi_xfer_req] [get_bd_pins axi_fifo2s/axi_xfer_req]
connect_bd_net -net axi_clk [get_bd_pins axi_ddr_cntrl/ui_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/axi_clk]
connect_bd_net -net axi_clk [get_bd_pins axi_fifo2s/m_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_ctl/s_clk]
connect_bd_net -net axi_clk [get_bd_pins wfifo_mem/rd_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_ctl/m_clk]
connect_bd_net -net axi_clk [get_bd_pins rfifo_mem/wr_clk]
connect_bd_net -net dma_rstn [get_bd_pins dma_rstn]
connect_bd_net -net dma_rstn [get_bd_pins axi_ddr_cntrl/aresetn]
connect_bd_net -net dma_rstn [get_bd_pins axi_fifo2s/axi_resetn]
connect_bd_net -net dma_rstn [get_bd_pins rfifo_ctl/rstn]
connect_bd_net -net dma_rstn [get_bd_pins wfifo_ctl/rstn]
connect_bd_net -net dma_clk [get_bd_pins axi_ddr_cntrl/ui_clk]
connect_bd_net -net dma_clk [get_bd_pins axi_fifo2s/axi_clk]
connect_bd_net -net dma_clk [get_bd_pins axi_fifo2s/m_clk]
connect_bd_net -net dma_clk [get_bd_pins wfifo_ctl/s_clk]
connect_bd_net -net dma_clk [get_bd_pins wfifo_mem/rd_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/m_clk]
connect_bd_net -net dma_clk [get_bd_pins axi_ddr_cntrl/ui_addn_clk_0]
connect_bd_net -net dma_clk [get_bd_pins rfifo_ctl/s_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_mem/rd_clk]
connect_bd_net -net dma_clk [get_bd_pins rfifo_mem/wr_clk]
connect_bd_net -net dma_clk [get_bd_pins dma_clk]
connect_bd_net -net dma_wr [get_bd_pins dma_wr] [get_bd_pins rfifo_ctl/s_wr]
connect_bd_net -net dma_wdata [get_bd_pins dma_wdata] [get_bd_pins rfifo_ctl/s_wdata]
connect_bd_net -net dma_wovf [get_bd_pins dma_wovf] [get_bd_pins rfifo_ctl/s_wovf]
connect_bd_net -net adc_wr [get_bd_pins adc_wr] [get_bd_pins wfifo_ctl/m_wr]
connect_bd_net -net adc_wdata [get_bd_pins adc_wdata] [get_bd_pins wfifo_ctl/m_wdata]
connect_bd_net -net adc_wovf [get_bd_pins adc_wovf] [get_bd_pins wfifo_ctl/m_wovf]
connect_bd_net -net axi_xfer_req [get_bd_pins axi_xfer_req] [get_bd_pins axi_fifo2s/axi_xfer_req]
connect_bd_net -net axi_xfer_status [get_bd_pins axi_xfer_status] [get_bd_pins axi_fifo2s/axi_xfer_status]
connect_bd_net -net wfifo_ctl_fifo_rst [get_bd_pins wfifo_ctl/fifo_rst] [get_bd_pins wfifo_mem/rst]
connect_bd_net -net wfifo_ctl_fifo_wr [get_bd_pins wfifo_ctl/fifo_wr] [get_bd_pins wfifo_mem/wr_en]
connect_bd_net -net wfifo_ctl_fifo_wdata [get_bd_pins wfifo_ctl/fifo_wdata] [get_bd_pins wfifo_mem/din]
connect_bd_net -net wfifo_ctl_fifo_wfull [get_bd_pins wfifo_ctl/fifo_wfull] [get_bd_pins wfifo_mem/full]
connect_bd_net -net wfifo_ctl_fifo_wovf [get_bd_pins wfifo_ctl/fifo_wovf] [get_bd_pins wfifo_mem/overflow]
connect_bd_net -net dma_wr [get_bd_pins dma_wr] [get_bd_pins rfifo_ctl/s_wr]
connect_bd_net -net dma_wdata [get_bd_pins dma_wdata] [get_bd_pins rfifo_ctl/s_wdata]
connect_bd_net -net dma_wovf [get_bd_pins dma_wovf] [get_bd_pins rfifo_ctl/s_wovf]
connect_bd_net -net rfifo_ctl_fifo_rd [get_bd_pins rfifo_ctl/fifo_rd] [get_bd_pins rfifo_mem/rd_en]
connect_bd_net -net rfifo_ctl_fifo_rdata [get_bd_pins rfifo_ctl/fifo_rdata] [get_bd_pins rfifo_mem/dout]
connect_bd_net -net rfifo_ctl_fifo_rempty [get_bd_pins rfifo_ctl/fifo_rempty] [get_bd_pins rfifo_mem/empty]
connect_bd_net -net wfifo_ctl_fifo_rd [get_bd_pins wfifo_ctl/fifo_rd] [get_bd_pins wfifo_mem/rd_en]
connect_bd_net -net wfifo_ctl_fifo_rdata [get_bd_pins wfifo_ctl/fifo_rdata] [get_bd_pins wfifo_mem/dout]
connect_bd_net -net wfifo_ctl_fifo_rempty [get_bd_pins wfifo_ctl/fifo_rempty] [get_bd_pins wfifo_mem/empty]
@ -113,9 +119,6 @@ proc p_plddr3_fifo {p_name m_name m_width} {
connect_bd_net -net rfifo_ctl_fifo_wdata [get_bd_pins rfifo_ctl/fifo_wdata] [get_bd_pins rfifo_mem/din]
connect_bd_net -net rfifo_ctl_fifo_wfull [get_bd_pins rfifo_ctl/fifo_wfull] [get_bd_pins rfifo_mem/full]
connect_bd_net -net rfifo_ctl_fifo_wovf [get_bd_pins rfifo_ctl/fifo_wovf] [get_bd_pins rfifo_mem/overflow]
connect_bd_net -net rfifo_ctl_fifo_rd [get_bd_pins rfifo_ctl/fifo_rd] [get_bd_pins rfifo_mem/rd_en]
connect_bd_net -net rfifo_ctl_fifo_rdata [get_bd_pins rfifo_ctl/fifo_rdata] [get_bd_pins rfifo_mem/dout]
connect_bd_net -net rfifo_ctl_fifo_rempty [get_bd_pins rfifo_ctl/fifo_rempty] [get_bd_pins rfifo_mem/empty]
connect_bd_net -net axi_fifo2s_swr [get_bd_pins axi_fifo2s/m_wr] [get_bd_pins wfifo_ctl/s_wr]
connect_bd_net -net axi_fifo2s_swdata [get_bd_pins axi_fifo2s/m_wdata] [get_bd_pins wfifo_ctl/s_wdata]
connect_bd_net -net axi_fifo2s_swovf [get_bd_pins axi_fifo2s/m_wovf] [get_bd_pins wfifo_ctl/s_wovf]

3
projects/scripts/adi_project.tcl
View File

@ -96,6 +96,9 @@ proc adi_project_create {project_name} {
create_bd_design "system"
source system_bd.tcl
save_bd_design
validate_bd_design
generate_target {synthesis implementation} [get_files $project_system_dir/system.bd]
make_wrapper -files [get_files $project_system_dir/system.bd] -top
import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v