adv7511_mitx045: Update latest frame work.
parent
fcb163062f
commit
4f69ae19c5
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@ -1,9 +1,3 @@
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source $ad_hdl_dir/projects/common/mitx045/mitx045_system_bd.tcl
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
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set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
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set_property LEFT 31 [get_bd_ports GPIO_I]
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set_property LEFT 31 [get_bd_ports GPIO_O]
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set_property LEFT 31 [get_bd_ports GPIO_T]
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@ -1,13 +1,13 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project_create adv7511_mitx045
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adi_project_files adv7511_mitx045 [list \
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"system_top.v" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" \
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"$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc" ]
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"$ad_hdl_dir/projects/common/mitx045/mitx045_system_constr.xdc"]
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adi_project_run adv7511_mitx045
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@ -41,28 +41,28 @@
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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ddr_addr,
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ddr_ba,
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ddr_cas_n,
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ddr_ck_n,
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ddr_ck_p,
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ddr_cke,
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ddr_cs_n,
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ddr_dm,
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ddr_dq,
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ddr_dqs_n,
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ddr_dqs_p,
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ddr_odt,
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ddr_ras_n,
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ddr_reset_n,
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ddr_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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fixed_io_ddr_vrn,
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fixed_io_ddr_vrp,
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fixed_io_mio,
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fixed_io_ps_clk,
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fixed_io_ps_porb,
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fixed_io_ps_srstb,
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gpio_bd,
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@ -83,28 +83,28 @@ module system_top (
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iic_scl,
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iic_sda);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout [14:0] ddr_addr;
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inout [ 2:0] ddr_ba;
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inout ddr_cas_n;
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inout ddr_ck_n;
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inout ddr_ck_p;
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inout ddr_cke;
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inout ddr_cs_n;
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inout [ 3:0] ddr_dm;
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inout [31:0] ddr_dq;
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inout [ 3:0] ddr_dqs_n;
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inout [ 3:0] ddr_dqs_p;
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inout ddr_odt;
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inout ddr_ras_n;
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inout ddr_reset_n;
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inout ddr_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout fixed_io_ddr_vrn;
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inout fixed_io_ddr_vrp;
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inout [53:0] fixed_io_mio;
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inout fixed_io_ps_clk;
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inout fixed_io_ps_porb;
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inout fixed_io_ps_srstb;
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inout [11:0] gpio_bd;
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@ -127,13 +127,11 @@ module system_top (
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// internal signals
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wire [31:0] gpio_i;
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wire [31:0] gpio_o;
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wire [31:0] gpio_t;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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wire [19:0] gpio_wire;
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wire [15:0] ps_intrs;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(32)) i_iobuf (
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@ -144,30 +142,30 @@ module system_top (
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gpio_bd}));
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.DDR_addr (ddr_addr),
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.DDR_ba (ddr_ba),
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.DDR_cas_n (ddr_cas_n),
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.DDR_ck_n (ddr_ck_n),
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.DDR_ck_p (ddr_ck_p),
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.DDR_cke (ddr_cke),
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.DDR_cs_n (ddr_cs_n),
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.DDR_dm (ddr_dm),
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.DDR_dq (ddr_dq),
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.DDR_dqs_n (ddr_dqs_n),
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.DDR_dqs_p (ddr_dqs_p),
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.DDR_odt (ddr_odt),
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.DDR_ras_n (ddr_ras_n),
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.DDR_reset_n (ddr_reset_n),
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.DDR_we_n (ddr_we_n),
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.FIXED_IO_ddr_vrn (fixed_io_ddr_vrn),
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.FIXED_IO_ddr_vrp (fixed_io_ddr_vrp),
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.FIXED_IO_mio (fixed_io_mio),
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.FIXED_IO_ps_clk (fixed_io_ps_clk),
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.FIXED_IO_ps_porb (fixed_io_ps_porb),
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.FIXED_IO_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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@ -180,20 +178,20 @@ module system_top (
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.i2s_sdata_out (i2s_sdata_out),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.ps_intr_0 (ps_intrs[0]),
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.ps_intr_1 (ps_intrs[1]),
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.ps_intr_2 (ps_intrs[2]),
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.ps_intr_3 (ps_intrs[3]),
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.ps_intr_4 (ps_intrs[4]),
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.ps_intr_5 (ps_intrs[5]),
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.ps_intr_6 (ps_intrs[6]),
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.ps_intr_7 (ps_intrs[7]),
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.ps_intr_8 (ps_intrs[8]),
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.ps_intr_9 (ps_intrs[9]),
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.ps_intr_10 (ps_intrs[10]),
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.ps_intr_11 (ps_intrs[11]),
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.ps_intr_12 (ps_intrs[12]),
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.ps_intr_13 (ps_intrs[13]),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_10 (1'b0),
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.ps_intr_11 (1'b0),
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.ps_intr_12 (1'b0),
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.ps_intr_13 (1'b0),
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.spdif (spdif));
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endmodule
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@ -1,36 +1,76 @@
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# create board design
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# interface ports
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set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN]
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_main
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set GPIO_I [create_bd_port -dir I -from 31 -to 0 GPIO_I]
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set GPIO_O [create_bd_port -dir O -from 31 -to 0 GPIO_O]
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set GPIO_T [create_bd_port -dir O -from 31 -to 0 GPIO_T]
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create_bd_port -dir I -from 63 -to 0 gpio_i
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create_bd_port -dir O -from 63 -to 0 gpio_o
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create_bd_port -dir O -from 63 -to 0 gpio_t
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# spi interface
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create_bd_port -dir O spi0_csn_2_o
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create_bd_port -dir O spi0_csn_1_o
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create_bd_port -dir O spi0_csn_0_o
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create_bd_port -dir I spi0_csn_i
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create_bd_port -dir I spi0_clk_i
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create_bd_port -dir O spi0_clk_o
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create_bd_port -dir I spi0_sdo_i
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create_bd_port -dir O spi0_sdo_o
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create_bd_port -dir I spi0_sdi_i
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create_bd_port -dir O spi1_csn_2_o
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create_bd_port -dir O spi1_csn_1_o
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create_bd_port -dir O spi1_csn_0_o
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create_bd_port -dir I spi1_csn_i
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create_bd_port -dir I spi1_clk_i
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create_bd_port -dir O spi1_clk_o
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create_bd_port -dir I spi1_sdo_i
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create_bd_port -dir O spi1_sdo_o
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create_bd_port -dir I spi1_sdi_i
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# hdmi interface
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set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk]
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set hdmi_hsync [create_bd_port -dir O hdmi_hsync]
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set hdmi_vsync [create_bd_port -dir O hdmi_vsync]
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set hdmi_data_e [create_bd_port -dir O hdmi_data_e]
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set hdmi_data [create_bd_port -dir O -from 15 -to 0 hdmi_data]
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create_bd_port -dir O hdmi_out_clk
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create_bd_port -dir O hdmi_hsync
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create_bd_port -dir O hdmi_vsync
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create_bd_port -dir O hdmi_data_e
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create_bd_port -dir O -from 15 -to 0 hdmi_data
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# spdif audio
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set spdif [create_bd_port -dir O spdif]
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create_bd_port -dir O spdif
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# i2s
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set i2s_mclk [create_bd_port -dir O -type clk i2s_mclk]
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set i2s_bclk [create_bd_port -dir O i2s_bclk]
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set i2s_lrclk [create_bd_port -dir O i2s_lrclk]
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set i2s_sdata_out [create_bd_port -dir O i2s_sdata_out]
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set i2s_sdata_in [create_bd_port -dir I i2s_sdata_in]
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create_bd_port -dir O -type clk i2s_mclk
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create_bd_port -dir O i2s_bclk
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create_bd_port -dir O i2s_lrclk
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create_bd_port -dir O i2s_sdata_out
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create_bd_port -dir I i2s_sdata_in
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# interrupts
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create_bd_port -dir I -type intr ps_intr_00
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create_bd_port -dir I -type intr ps_intr_01
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create_bd_port -dir I -type intr ps_intr_02
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create_bd_port -dir I -type intr ps_intr_03
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create_bd_port -dir I -type intr ps_intr_04
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create_bd_port -dir I -type intr ps_intr_05
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create_bd_port -dir I -type intr ps_intr_06
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create_bd_port -dir I -type intr ps_intr_07
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create_bd_port -dir I -type intr ps_intr_08
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create_bd_port -dir I -type intr ps_intr_09
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create_bd_port -dir I -type intr ps_intr_10
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create_bd_port -dir I -type intr ps_intr_11
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create_bd_port -dir I -type intr ps_intr_12
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create_bd_port -dir I -type intr ps_intr_13
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# instance: sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7]
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apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "FIXED_IO, DDR" apply_board_preset "1" Master "Disable" Slave "Disable" } $sys_ps7
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set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 sys_ps7]
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apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {make_external "fixed_io, ddr" apply_board_preset "1" Master "Disable" Slave "Disable" } $sys_ps7
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set_property -dict [list CONFIG.PCW_TTC0_PERIPHERAL_ENABLE {0}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} ] $sys_ps7
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set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $sys_ps7
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@ -41,22 +81,23 @@ set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {32}] $sys_ps7
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set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {62}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA0 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA1 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_USE_DMA2 {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_IRQ_F2P_MODE {REVERSE}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1}] $sys_ps7
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set_property -dict [list CONFIG.PCW_SPI1_SPI1_IO {EMIO}] $sys_ps7
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set axi_iic_main [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_main]
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_main
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set_property -dict [list CONFIG.USE_BOARD_FLOW {true}] $axi_iic_main
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set_property -dict [list CONFIG.IIC_BOARD_INTERFACE {Custom}] $axi_iic_main
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set sys_concat_intc [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 sys_concat_intc]
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set_property -dict [list CONFIG.NUM_PORTS {16}] $sys_concat_intc
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set axi_cpu_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_cpu_interconnect]
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set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect
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set_property -dict [list CONFIG.STRATEGY {1}] $axi_cpu_interconnect
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set sys_rstgen [create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 sys_rstgen]
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set_property -dict [list CONFIG.C_EXT_RST_WIDTH {1}] $sys_rstgen
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@ -70,9 +111,6 @@ set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma
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set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma
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set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect]
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set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect
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# audio peripherals
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|
||||
set sys_audio_clkgen [create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.1 sys_audio_clkgen]
|
||||
|
@ -91,167 +129,124 @@ set_property -dict [list CONFIG.C_S_AXI_ADDR_WIDTH {16}] $axi_i2s_adi
|
|||
|
||||
# system reset/clock definitions
|
||||
|
||||
set sys_100m_clk_source [get_bd_pins sys_ps7/FCLK_CLK0]
|
||||
set sys_200m_clk_source [get_bd_pins sys_ps7/FCLK_CLK1]
|
||||
|
||||
connect_bd_net -net sys_100m_clk $sys_100m_clk_source
|
||||
connect_bd_net -net sys_200m_clk $sys_200m_clk_source
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_rstgen/slowest_sync_clk]
|
||||
connect_bd_net -net sys_aux_reset [get_bd_pins sys_rstgen/ext_reset_in] [get_bd_pins sys_ps7/FCLK_RESET0_N]
|
||||
|
||||
set sys_100m_resetn_source [get_bd_pins sys_rstgen/peripheral_aresetn]
|
||||
set sys_200m_resetn_source [get_bd_pins sys_rstgen/interconnect_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_200m_resetn $sys_200m_resetn_source
|
||||
ad_connect sys_cpu_clk sys_ps7/FCLK_CLK0
|
||||
ad_connect sys_200m_clk sys_ps7/FCLK_CLK1
|
||||
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
|
||||
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
|
||||
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
|
||||
ad_connect sys_rstgen/ext_reset_in sys_ps7/FCLK_RESET0_N
|
||||
|
||||
# interface connections
|
||||
|
||||
connect_bd_intf_net -intf_net sys_ps7_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins sys_ps7/DDR]
|
||||
connect_bd_net -net sys_ps7_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins sys_ps7/GPIO_I]
|
||||
connect_bd_net -net sys_ps7_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins sys_ps7/GPIO_O]
|
||||
connect_bd_net -net sys_ps7_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins sys_ps7/GPIO_T]
|
||||
connect_bd_intf_net -intf_net sys_ps7_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins sys_ps7/FIXED_IO]
|
||||
connect_bd_intf_net -intf_net axi_iic_main_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_main/iic]
|
||||
ad_connect gpio_i sys_ps7/GPIO_I
|
||||
ad_connect gpio_o sys_ps7/GPIO_O
|
||||
ad_connect gpio_t sys_ps7/GPIO_T
|
||||
ad_connect iic_main axi_iic_main/iic
|
||||
ad_connect sys_200m_clk axi_hdmi_clkgen/clk
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/M_AXI_GP0_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
# spi connection
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_s00_axi [get_bd_intf_pins axi_cpu_interconnect/S00_AXI] [get_bd_intf_pins sys_ps7/M_AXI_GP0]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
ad_connect spi0_csn_2_o sys_ps7/SPI0_SS2_O
|
||||
ad_connect spi0_csn_1_o sys_ps7/SPI0_SS1_O
|
||||
ad_connect spi0_csn_0_o sys_ps7/SPI0_SS_O
|
||||
ad_connect spi0_csn_i sys_ps7/SPI0_SS_I
|
||||
ad_connect spi0_clk_i sys_ps7/SPI0_SCLK_I
|
||||
ad_connect spi0_clk_o sys_ps7/SPI0_SCLK_O
|
||||
ad_connect spi0_sdo_i sys_ps7/SPI0_MOSI_I
|
||||
ad_connect spi0_sdo_o sys_ps7/SPI0_MOSI_O
|
||||
ad_connect spi0_sdi_i sys_ps7/SPI0_MISO_I
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m00_axi [get_bd_intf_pins axi_cpu_interconnect/M00_AXI] [get_bd_intf_pins axi_iic_main/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_iic_main/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_main/s_axi_aresetn]
|
||||
ad_connect spi1_csn_2_o sys_ps7/SPI1_SS2_O
|
||||
ad_connect spi1_csn_1_o sys_ps7/SPI1_SS1_O
|
||||
ad_connect spi1_csn_0_o sys_ps7/SPI1_SS_O
|
||||
ad_connect spi1_csn_i sys_ps7/SPI1_SS_I
|
||||
ad_connect spi1_clk_i sys_ps7/SPI1_SCLK_I
|
||||
ad_connect spi1_clk_o sys_ps7/SPI1_SCLK_O
|
||||
ad_connect spi1_sdo_i sys_ps7/SPI1_MOSI_I
|
||||
ad_connect spi1_sdo_o sys_ps7/SPI1_MOSI_O
|
||||
ad_connect spi1_sdi_i sys_ps7/SPI1_MISO_I
|
||||
|
||||
# hdmi
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins axi_hdmi_clkgen/clk]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m01_axi [get_bd_intf_pins axi_cpu_interconnect/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m02_axi [get_bd_intf_pins axi_cpu_interconnect/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi]
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m03_axi [get_bd_intf_pins axi_cpu_interconnect/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE]
|
||||
|
||||
connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S]
|
||||
connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP0]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M01_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M02_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M03_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/S00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_interconnect/M00_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_clkgen/drp_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/s_axi_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP0_ACLK]
|
||||
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M01_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M02_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M03_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_core/s_axi_aresetn]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_hdmi_dma/axi_resetn]
|
||||
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_16_hsync] [get_bd_ports hdmi_hsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_16_vsync] [get_bd_ports hdmi_vsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_16_data_e] [get_bd_ports hdmi_data_e]
|
||||
connect_bd_net -net axi_hdmi_tx_core_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_16_data] [get_bd_ports hdmi_data]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync]
|
||||
connect_bd_net -net axi_hdmi_tx_core_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret]
|
||||
ad_connect sys_cpu_clk axi_hdmi_clkgen/drp_clk
|
||||
ad_connect sys_cpu_clk axi_hdmi_core/m_axis_mm2s_clk
|
||||
ad_connect sys_cpu_clk axi_hdmi_dma/m_axis_mm2s_aclk
|
||||
ad_connect axi_hdmi_core/hdmi_clk axi_hdmi_clkgen/clk_0
|
||||
ad_connect axi_hdmi_core/hdmi_out_clk hdmi_out_clk
|
||||
ad_connect axi_hdmi_core/hdmi_16_hsync hdmi_hsync
|
||||
ad_connect axi_hdmi_core/hdmi_16_vsync hdmi_vsync
|
||||
ad_connect axi_hdmi_core/hdmi_16_data_e hdmi_data_e
|
||||
ad_connect axi_hdmi_core/hdmi_16_data hdmi_data
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tvalid axi_hdmi_dma/m_axis_mm2s_tvalid
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tdata axi_hdmi_dma/m_axis_mm2s_tdata
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tkeep axi_hdmi_dma/m_axis_mm2s_tkeep
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tlast axi_hdmi_dma/m_axis_mm2s_tlast
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_tready axi_hdmi_dma/m_axis_mm2s_tready
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_dma/mm2s_fsync
|
||||
ad_connect axi_hdmi_core/m_axis_mm2s_fsync axi_hdmi_core/m_axis_mm2s_fsync_ret
|
||||
|
||||
# spdif audio
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m04_axi [get_bd_intf_pins axi_cpu_interconnect/M04_AXI] [get_bd_intf_pins axi_spdif_tx_core/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M04_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M04_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/S_AXI_ARESETN]
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_spdif_tx_core/DMA_REQ_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA0_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_spdif_tx_core/DMA_REQ_RSTN]
|
||||
connect_bd_intf_net -intf_net axi_spdif_dma_req_tx [get_bd_intf_pins sys_ps7/DMA0_REQ] [get_bd_intf_pins axi_spdif_tx_core/DMA_REQ]
|
||||
connect_bd_intf_net -intf_net axi_spdif_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA0_ACK] [get_bd_intf_pins axi_spdif_tx_core/DMA_ACK]
|
||||
|
||||
connect_bd_net -net sys_200m_clk [get_bd_pins sys_audio_clkgen/clk_in1]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins sys_audio_clkgen/resetn] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins sys_audio_clkgen/clk_out1] [get_bd_pins axi_spdif_tx_core/spdif_data_clk]
|
||||
connect_bd_net -net spdif_s [get_bd_ports spdif] [get_bd_pins axi_spdif_tx_core/spdif_tx_o]
|
||||
ad_connect sys_cpu_clk axi_spdif_tx_core/DMA_REQ_ACLK
|
||||
ad_connect sys_cpu_clk sys_ps7/DMA0_ACLK
|
||||
ad_connect sys_cpu_resetn axi_spdif_tx_core/DMA_REQ_RSTN
|
||||
ad_connect sys_ps7/DMA0_REQ axi_spdif_tx_core/DMA_REQ
|
||||
ad_connect sys_ps7/DMA0_ACK axi_spdif_tx_core/DMA_ACK
|
||||
ad_connect sys_200m_clk sys_audio_clkgen/clk_in1
|
||||
ad_connect sys_cpu_resetn sys_audio_clkgen/resetn
|
||||
ad_connect sys_audio_clkgen/clk_out1 axi_spdif_tx_core/spdif_data_clk
|
||||
ad_connect spdif axi_spdif_tx_core/spdif_tx_o
|
||||
|
||||
# i2s audio
|
||||
|
||||
connect_bd_intf_net -intf_net axi_cpu_interconnect_m05_axi [get_bd_intf_pins axi_cpu_interconnect/M05_AXI] [get_bd_intf_pins axi_i2s_adi/s_axi]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M05_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/S_AXI_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_RX_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_i2s_adi/DMA_REQ_TX_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA1_ACLK]
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/DMA2_ACLK]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M05_ARESETN] $sys_100m_resetn_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/S_AXI_ARESETN]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_RX_RSTN]
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_i2s_adi/DMA_REQ_TX_RSTN]
|
||||
ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_RX_ACLK
|
||||
ad_connect sys_cpu_clk axi_i2s_adi/DMA_REQ_TX_ACLK
|
||||
ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_RX_RSTN
|
||||
ad_connect sys_cpu_resetn axi_i2s_adi/DMA_REQ_TX_RSTN
|
||||
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_ports i2s_mclk]
|
||||
connect_bd_net -net sys_audio_clkgen_clk [get_bd_pins axi_i2s_adi/DATA_CLK_I]
|
||||
ad_connect i2s_mclk sys_audio_clkgen/clk_out1
|
||||
ad_connect axi_i2s_adi/DATA_CLK_I sys_audio_clkgen/clk_out1
|
||||
|
||||
connect_bd_net -net i2s_bclk_s [get_bd_ports i2s_bclk] [get_bd_pins axi_i2s_adi/BCLK_O]
|
||||
connect_bd_net -net i2s_lrclk_s [get_bd_ports i2s_lrclk] [get_bd_pins axi_i2s_adi/LRCLK_O]
|
||||
connect_bd_net -net i2s_sdata_out_s [get_bd_ports i2s_sdata_out] [get_bd_pins axi_i2s_adi/SDATA_O]
|
||||
connect_bd_net -net i2s_sdata_in_s [get_bd_ports i2s_sdata_in] [get_bd_pins axi_i2s_adi/SDATA_I]
|
||||
ad_connect i2s_bclk axi_i2s_adi/BCLK_O
|
||||
ad_connect i2s_lrclk axi_i2s_adi/LRCLK_O
|
||||
ad_connect i2s_sdata_out axi_i2s_adi/SDATA_O
|
||||
ad_connect i2s_sdata_in axi_i2s_adi/SDATA_I
|
||||
|
||||
connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_tx [get_bd_intf_pins sys_ps7/DMA1_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_TX]
|
||||
connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_tx [get_bd_intf_pins sys_ps7/DMA1_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_TX]
|
||||
connect_bd_intf_net -intf_net axi_i2s_adi_dma_req_rx [get_bd_intf_pins sys_ps7/DMA2_REQ] [get_bd_intf_pins axi_i2s_adi/DMA_REQ_RX]
|
||||
connect_bd_intf_net -intf_net axi_i2s_adi_dma_ack_rx [get_bd_intf_pins sys_ps7/DMA2_ACK] [get_bd_intf_pins axi_i2s_adi/DMA_ACK_RX]
|
||||
|
||||
# match up interconnects
|
||||
|
||||
connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M06_ACLK] $sys_100m_clk_source
|
||||
connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M06_ARESETN] $sys_100m_resetn_source
|
||||
ad_connect sys_ps7/DMA1_REQ axi_i2s_adi/DMA_REQ_TX
|
||||
ad_connect sys_ps7/DMA1_ACK axi_i2s_adi/DMA_ACK_TX
|
||||
ad_connect sys_ps7/DMA2_REQ axi_i2s_adi/DMA_REQ_RX
|
||||
ad_connect sys_ps7/DMA2_ACK axi_i2s_adi/DMA_ACK_RX
|
||||
ad_connect sys_cpu_clk sys_ps7/DMA1_ACLK
|
||||
ad_connect sys_cpu_clk sys_ps7/DMA2_ACLK
|
||||
|
||||
# interrupts
|
||||
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P]
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/In15] [get_bd_pins axi_hdmi_dma/mm2s_introut]
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2intc_irpt]
|
||||
ad_connect sys_concat_intc/dout sys_ps7/IRQ_F2P
|
||||
ad_connect sys_concat_intc/In15 axi_hdmi_dma/mm2s_introut
|
||||
ad_connect sys_concat_intc/In14 axi_iic_main/iic2intc_irpt
|
||||
ad_connect sys_concat_intc/In13 ps_intr_13
|
||||
ad_connect sys_concat_intc/In12 ps_intr_12
|
||||
ad_connect sys_concat_intc/In11 ps_intr_11
|
||||
ad_connect sys_concat_intc/In10 ps_intr_10
|
||||
ad_connect sys_concat_intc/In9 ps_intr_09
|
||||
ad_connect sys_concat_intc/In8 ps_intr_08
|
||||
ad_connect sys_concat_intc/In7 ps_intr_07
|
||||
ad_connect sys_concat_intc/In6 ps_intr_06
|
||||
ad_connect sys_concat_intc/In5 ps_intr_05
|
||||
ad_connect sys_concat_intc/In4 ps_intr_04
|
||||
ad_connect sys_concat_intc/In3 ps_intr_03
|
||||
ad_connect sys_concat_intc/In2 ps_intr_02
|
||||
ad_connect sys_concat_intc/In1 ps_intr_01
|
||||
ad_connect sys_concat_intc/In0 ps_intr_00
|
||||
|
||||
for {set intc_index 0} {$intc_index < 14} {incr intc_index} {
|
||||
set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}]
|
||||
connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}]
|
||||
}
|
||||
# interconnects
|
||||
|
||||
# address map
|
||||
|
||||
set sys_zynq 1
|
||||
set sys_mem_size 0x40000000
|
||||
set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
|
||||
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x41600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_iic_main/s_axi/Reg] SEG_data_iic_main
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x79000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x43000000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x70e00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x75c00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_spdif_tx_core/S_AXI/reg0] SEG_data_spdif_core
|
||||
create_bd_addr_seg -range 0x00010000 -offset 0x77600000 $sys_addr_cntrl_space [get_bd_addr_segs axi_i2s_adi/S_AXI/reg0] SEG_data_i2s_adi
|
||||
|
||||
create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_sys_ps7_hp0_ddr_lowocm
|
||||
ad_cpu_interconnect 0x41600000 axi_iic_main
|
||||
ad_cpu_interconnect 0x79000000 axi_hdmi_clkgen
|
||||
ad_cpu_interconnect 0x43000000 axi_hdmi_dma
|
||||
ad_cpu_interconnect 0x70e00000 axi_hdmi_core
|
||||
ad_cpu_interconnect 0x75c00000 axi_spdif_tx_core
|
||||
ad_cpu_interconnect 0x77600000 axi_i2s_adi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_hdmi_dma/M_AXI_MM2S
|
||||
|
||||
|
|
Loading…
Reference in New Issue