fmcadc5: Update project
+ Update the JESD IP core for Vivado 2015.2 + Update the framework for JESD interfacemain
Istvan Csomortani
parent
f5b5bbfbca
commit
4f99bdd93f
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@ -9,54 +9,22 @@ create_bd_port -dir I rx_ref_clk_1
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create_bd_port -dir I -from 7 -to 0 rx_data_1_p
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create_bd_port -dir I -from 7 -to 0 rx_data_1_n
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create_bd_port -dir O rx_sync_1
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create_bd_port -dir O rx_sysref
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create_bd_port -dir O adc_clk
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create_bd_port -dir O adc_valid_0
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create_bd_port -dir O adc_enable_0
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create_bd_port -dir O -from 255 -to 0 adc_data_0
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create_bd_port -dir O adc_valid_1
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create_bd_port -dir O adc_enable_1
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create_bd_port -dir O -from 255 -to 0 adc_data_1
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create_bd_port -dir I adc_wr
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create_bd_port -dir I -from 511 -to 0 adc_wdata
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create_bd_port -dir I rx_sysref
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# adc peripherals
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set axi_ad9625_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_0_core]
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set_property -dict [list CONFIG.ID {0}] $axi_ad9625_0_core
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set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9625_0_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
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set axi_ad9625_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_0_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_ad9625_0_gt
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set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_0_gt
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set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_0_gt
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set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_0_gt
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set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_0_gt
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set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_0_gt
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set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_0_gt
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set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_0_gt
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set axi_ad9625_1_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9625:1.0 axi_ad9625_1_core]
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set_property -dict [list CONFIG.ID {1}] $axi_ad9625_1_core
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set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9625_1_jesd]
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set axi_ad9625_0_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_0_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_0_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_0_jesd
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set axi_ad9625_1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.1 axi_ad9625_1_jesd]
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set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9625_1_jesd
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set_property -dict [list CONFIG.C_LANES {8}] $axi_ad9625_1_jesd
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set axi_ad9625_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_ad9625_1_gt]
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set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {8}] $axi_ad9625_1_gt
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set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {1}] $axi_ad9625_1_gt
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set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_ad9625_1_gt
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set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_ad9625_1_gt
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set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {25}] $axi_ad9625_1_gt
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set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {25}] $axi_ad9625_1_gt
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set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_ad9625_1_gt
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set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_ad9625_1_gt
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set axi_ad9625_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9625_dma]
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set_property -dict [list CONFIG.DMA_TYPE_SRC {1}] $axi_ad9625_dma
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set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9625_dma
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@ -72,175 +40,220 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
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p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 512 18
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# adc common gt
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set axi_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_0_gt]
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set_property -dict [list CONFIG.ID {0}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_0_gt
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set axi_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcadc5_1_gt]
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set_property -dict [list CONFIG.ID {0}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_0 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_0 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_1 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_1 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_2 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_2 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_3 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_3 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_4 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_4 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_5 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_5 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_6 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_6 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.PMA_RSV_7 {0x00018480}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.CPLL_FBDIV_7 {1}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_0 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_0 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_1 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_1 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_2 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_2 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_3 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_3 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_4 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_4 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_5 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_5 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_6 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_6 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CLK25_DIV_7 {25}] $axi_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_CDR_CFG_7 {0x03000023ff20400020}] $axi_fmcadc5_1_gt
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set util_fmcadc5_0_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_0_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_0_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_0_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_0_gt
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set util_fmcadc5_1_gt [create_bd_cell -type ip -vlnv analog.com:user:util_jesd_gt:1.0 util_fmcadc5_1_gt]
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set_property -dict [list CONFIG.NUM_OF_LANES {8}] $util_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_ENABLE {1}] $util_fmcadc5_1_gt
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set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc5_1_gt
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set_property -dict [list CONFIG.TX_ENABLE {0}] $util_fmcadc5_1_gt
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set axi_fmcadc5_cpack [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 axi_fmcadc5_cpack]
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set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {256}] $axi_fmcadc5_cpack
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set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $axi_fmcadc5_cpack
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# connections (gt)
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ad_connect axi_ad9625_0_gt/ref_clk_c rx_ref_clk_0
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ad_connect axi_ad9625_0_gt/rx_data_p rx_data_0_p
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ad_connect axi_ad9625_0_gt/rx_data_n rx_data_0_n
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ad_connect axi_ad9625_0_gt/rx_sync rx_sync_0
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ad_connect axi_ad9625_0_gt/rx_sysref rx_sysref
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ad_connect axi_ad9625_1_gt/ref_clk_c rx_ref_clk_1
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ad_connect axi_ad9625_1_gt/rx_data_p rx_data_1_p
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ad_connect axi_ad9625_1_gt/rx_data_n rx_data_1_n
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ad_connect axi_ad9625_1_gt/rx_sync rx_sync_1
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ad_connect util_fmcadc5_0_gt/qpll_ref_clk rx_ref_clk_0
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ad_connect util_fmcadc5_1_gt/qpll_ref_clk rx_ref_clk_1
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ad_connect axi_fmcadc5_0_gt/gt_qpll_0 util_fmcadc5_0_gt/gt_qpll_0
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ad_connect axi_fmcadc5_0_gt/gt_qpll_1 util_fmcadc5_0_gt/gt_qpll_1
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ad_connect axi_fmcadc5_0_gt/gt_pll_0 util_fmcadc5_0_gt/gt_pll_0
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ad_connect axi_fmcadc5_0_gt/gt_pll_1 util_fmcadc5_0_gt/gt_pll_1
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ad_connect axi_fmcadc5_0_gt/gt_pll_2 util_fmcadc5_0_gt/gt_pll_2
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ad_connect axi_fmcadc5_0_gt/gt_pll_3 util_fmcadc5_0_gt/gt_pll_3
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ad_connect axi_fmcadc5_0_gt/gt_pll_4 util_fmcadc5_0_gt/gt_pll_4
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ad_connect axi_fmcadc5_0_gt/gt_pll_5 util_fmcadc5_0_gt/gt_pll_5
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ad_connect axi_fmcadc5_0_gt/gt_pll_6 util_fmcadc5_0_gt/gt_pll_6
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ad_connect axi_fmcadc5_0_gt/gt_pll_7 util_fmcadc5_0_gt/gt_pll_7
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ad_connect axi_fmcadc5_1_gt/gt_qpll_0 util_fmcadc5_1_gt/gt_qpll_0
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ad_connect axi_fmcadc5_1_gt/gt_qpll_1 util_fmcadc5_1_gt/gt_qpll_1
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ad_connect axi_fmcadc5_1_gt/gt_pll_0 util_fmcadc5_1_gt/gt_pll_0
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ad_connect axi_fmcadc5_1_gt/gt_pll_1 util_fmcadc5_1_gt/gt_pll_1
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ad_connect axi_fmcadc5_1_gt/gt_pll_2 util_fmcadc5_1_gt/gt_pll_2
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ad_connect axi_fmcadc5_1_gt/gt_pll_3 util_fmcadc5_1_gt/gt_pll_3
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ad_connect axi_fmcadc5_1_gt/gt_pll_4 util_fmcadc5_1_gt/gt_pll_4
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ad_connect axi_fmcadc5_1_gt/gt_pll_5 util_fmcadc5_1_gt/gt_pll_5
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ad_connect axi_fmcadc5_1_gt/gt_pll_6 util_fmcadc5_1_gt/gt_pll_6
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ad_connect axi_fmcadc5_1_gt/gt_pll_7 util_fmcadc5_1_gt/gt_pll_7
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ad_connect axi_fmcadc5_0_gt/gt_rx_0 util_fmcadc5_0_gt/gt_rx_0
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ad_connect axi_fmcadc5_0_gt/gt_rx_1 util_fmcadc5_0_gt/gt_rx_1
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ad_connect axi_fmcadc5_0_gt/gt_rx_2 util_fmcadc5_0_gt/gt_rx_2
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ad_connect axi_fmcadc5_0_gt/gt_rx_3 util_fmcadc5_0_gt/gt_rx_3
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ad_connect axi_fmcadc5_0_gt/gt_rx_4 util_fmcadc5_0_gt/gt_rx_4
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ad_connect axi_fmcadc5_0_gt/gt_rx_5 util_fmcadc5_0_gt/gt_rx_5
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ad_connect axi_fmcadc5_0_gt/gt_rx_6 util_fmcadc5_0_gt/gt_rx_6
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ad_connect axi_fmcadc5_0_gt/gt_rx_7 util_fmcadc5_0_gt/gt_rx_7
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ad_connect axi_fmcadc5_1_gt/gt_rx_0 util_fmcadc5_1_gt/gt_rx_0
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ad_connect axi_fmcadc5_1_gt/gt_rx_1 util_fmcadc5_1_gt/gt_rx_1
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ad_connect axi_fmcadc5_1_gt/gt_rx_2 util_fmcadc5_1_gt/gt_rx_2
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ad_connect axi_fmcadc5_1_gt/gt_rx_3 util_fmcadc5_1_gt/gt_rx_3
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ad_connect axi_fmcadc5_1_gt/gt_rx_4 util_fmcadc5_1_gt/gt_rx_4
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ad_connect axi_fmcadc5_1_gt/gt_rx_5 util_fmcadc5_1_gt/gt_rx_5
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ad_connect axi_fmcadc5_1_gt/gt_rx_6 util_fmcadc5_1_gt/gt_rx_6
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_7 util_fmcadc5_1_gt/gt_rx_7
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_0 axi_ad9625_0_jesd/gt0_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_1 axi_ad9625_0_jesd/gt1_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_2 axi_ad9625_0_jesd/gt2_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_3 axi_ad9625_0_jesd/gt3_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_4 axi_ad9625_0_jesd/gt4_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_5 axi_ad9625_0_jesd/gt5_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_6 axi_ad9625_0_jesd/gt6_rx
|
||||
ad_connect axi_fmcadc5_0_gt/gt_rx_ip_7 axi_ad9625_0_jesd/gt7_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_0 axi_ad9625_1_jesd/gt0_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_1 axi_ad9625_1_jesd/gt1_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_2 axi_ad9625_1_jesd/gt2_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_3 axi_ad9625_1_jesd/gt3_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_4 axi_ad9625_1_jesd/gt4_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_5 axi_ad9625_1_jesd/gt5_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_6 axi_ad9625_1_jesd/gt6_rx
|
||||
ad_connect axi_fmcadc5_1_gt/gt_rx_ip_7 axi_ad9625_1_jesd/gt7_rx
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_0 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_1 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_2 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_3 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_4 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_5 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_6 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_0_gt/rx_gt_comma_align_enb_7 axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_0 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_1 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_2 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_3 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_4 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_5 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_6 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_fmcadc5_1_gt/rx_gt_comma_align_enb_7 axi_ad9625_1_jesd/rxencommaalign_out
|
||||
|
||||
# connections (adc)
|
||||
|
||||
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_rst axi_ad9625_fifo/adc_rst
|
||||
ad_connect axi_ad9625_0_gt/rx_rst axi_ad9625_0_jesd/rx_reset
|
||||
ad_connect axi_ad9625_0_gt/rx_rst axi_ad9625_1_jesd/rx_reset
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g adc_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g axi_ad9625_fifo/adc_clk
|
||||
ad_connect axi_ad9625_0_gt/tx_clk_g axi_ad9625_0_gt/tx_clk
|
||||
ad_connect axi_ad9625_0_gt/tx_clk_g axi_ad9625_1_gt/tx_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g axi_ad9625_0_gt/rx_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g axi_ad9625_1_gt/rx_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g axi_ad9625_0_core/rx_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g axi_ad9625_1_core/rx_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g axi_ad9625_0_jesd/rx_core_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_clk_g axi_ad9625_1_jesd/rx_core_clk
|
||||
ad_connect axi_ad9625_0_gt/rx_sysref axi_ad9625_0_jesd/rx_sysref
|
||||
ad_connect axi_ad9625_0_gt/rx_sysref axi_ad9625_1_jesd/rx_sysref
|
||||
ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_0_core/adc_raddr_in
|
||||
ad_connect axi_ad9625_0_core/adc_raddr_out axi_ad9625_1_core/adc_raddr_in
|
||||
ad_connect util_fmcadc5_0_gt/rx_sysref rx_sysref
|
||||
ad_connect util_fmcadc5_0_gt/rx_p rx_data_0_p
|
||||
ad_connect util_fmcadc5_0_gt/rx_n rx_data_0_n
|
||||
ad_connect util_fmcadc5_0_gt/rx_sync rx_sync_0
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk util_fmcadc5_0_gt/rx_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_jesd/rx_core_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_rst axi_ad9625_0_jesd/rx_reset
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_rst_done axi_ad9625_0_jesd/rx_reset_done
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sysref axi_ad9625_0_jesd/rx_sysref
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sync axi_ad9625_0_jesd/rx_sync
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_sof axi_ad9625_0_jesd/rx_start_of_frame
|
||||
ad_connect util_fmcadc5_0_gt/rx_ip_data axi_ad9625_0_jesd/rx_tdata
|
||||
ad_connect util_fmcadc5_1_gt/rx_sysref rx_sysref
|
||||
ad_connect util_fmcadc5_1_gt/rx_p rx_data_1_p
|
||||
ad_connect util_fmcadc5_1_gt/rx_n rx_data_1_n
|
||||
ad_connect util_fmcadc5_1_gt/rx_sync rx_sync_1
|
||||
ad_connect util_fmcadc5_1_gt/rx_out_clk util_fmcadc5_1_gt/rx_clk
|
||||
ad_connect util_fmcadc5_1_gt/rx_out_clk axi_ad9625_1_jesd/rx_core_clk
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_rst axi_ad9625_1_jesd/rx_reset
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_rst_done axi_ad9625_1_jesd/rx_reset_done
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_sysref axi_ad9625_1_jesd/rx_sysref
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_sync axi_ad9625_1_jesd/rx_sync
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_sof axi_ad9625_1_jesd/rx_start_of_frame
|
||||
ad_connect util_fmcadc5_1_gt/rx_ip_data axi_ad9625_1_jesd/rx_tdata
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_charisk
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_0_gt_charisk]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_charisk]
|
||||
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/data axi_ad9625_0_gt/rx_gt_charisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_0 axi_ad9625_0_jesd/gt0_rxcharisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_1 axi_ad9625_0_jesd/gt1_rxcharisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_2 axi_ad9625_0_jesd/gt2_rxcharisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_3 axi_ad9625_0_jesd/gt3_rxcharisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_4 axi_ad9625_0_jesd/gt4_rxcharisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_5 axi_ad9625_0_jesd/gt5_rxcharisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_6 axi_ad9625_0_jesd/gt6_rxcharisk
|
||||
ad_connect util_bsplit_rx_0_gt_charisk/split_data_7 axi_ad9625_0_jesd/gt7_rxcharisk
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_disperr
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_0_gt_disperr]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_disperr]
|
||||
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/data axi_ad9625_0_gt/rx_gt_disperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_0 axi_ad9625_0_jesd/gt0_rxdisperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_1 axi_ad9625_0_jesd/gt1_rxdisperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_2 axi_ad9625_0_jesd/gt2_rxdisperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_3 axi_ad9625_0_jesd/gt3_rxdisperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_4 axi_ad9625_0_jesd/gt4_rxdisperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_5 axi_ad9625_0_jesd/gt5_rxdisperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_6 axi_ad9625_0_jesd/gt6_rxdisperr
|
||||
ad_connect util_bsplit_rx_0_gt_disperr/split_data_7 axi_ad9625_0_jesd/gt7_rxdisperr
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_notintable
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_0_gt_notintable]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_notintable]
|
||||
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/data axi_ad9625_0_gt/rx_gt_notintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_0 axi_ad9625_0_jesd/gt0_rxnotintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_1 axi_ad9625_0_jesd/gt1_rxnotintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_2 axi_ad9625_0_jesd/gt2_rxnotintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_3 axi_ad9625_0_jesd/gt3_rxnotintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_4 axi_ad9625_0_jesd/gt4_rxnotintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_5 axi_ad9625_0_jesd/gt5_rxnotintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_6 axi_ad9625_0_jesd/gt6_rxnotintable
|
||||
ad_connect util_bsplit_rx_0_gt_notintable/split_data_7 axi_ad9625_0_jesd/gt7_rxnotintable
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_0_gt_data
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_0_gt_data]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_0_gt_data]
|
||||
|
||||
ad_connect util_bsplit_rx_0_gt_data/data axi_ad9625_0_gt/rx_gt_data
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_0 axi_ad9625_0_jesd/gt0_rxdata
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_1 axi_ad9625_0_jesd/gt1_rxdata
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_2 axi_ad9625_0_jesd/gt2_rxdata
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_3 axi_ad9625_0_jesd/gt3_rxdata
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_4 axi_ad9625_0_jesd/gt4_rxdata
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_5 axi_ad9625_0_jesd/gt5_rxdata
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_6 axi_ad9625_0_jesd/gt6_rxdata
|
||||
ad_connect util_bsplit_rx_0_gt_data/split_data_7 axi_ad9625_0_jesd/gt7_rxdata
|
||||
|
||||
ad_connect axi_ad9625_0_gt/rx_rst_done axi_ad9625_0_jesd/rx_reset_done
|
||||
ad_connect axi_ad9625_0_gt/rx_ip_comma_align axi_ad9625_0_jesd/rxencommaalign_out
|
||||
ad_connect axi_ad9625_0_gt/rx_ip_sync axi_ad9625_0_jesd/rx_sync
|
||||
ad_connect axi_ad9625_0_gt/rx_ip_sof axi_ad9625_0_jesd/rx_start_of_frame
|
||||
ad_connect axi_ad9625_0_gt/rx_ip_data axi_ad9625_0_jesd/rx_tdata
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_charisk
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_1_gt_charisk]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_charisk]
|
||||
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/data axi_ad9625_1_gt/rx_gt_charisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_0 axi_ad9625_1_jesd/gt0_rxcharisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_1 axi_ad9625_1_jesd/gt1_rxcharisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_2 axi_ad9625_1_jesd/gt2_rxcharisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_3 axi_ad9625_1_jesd/gt3_rxcharisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_4 axi_ad9625_1_jesd/gt4_rxcharisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_5 axi_ad9625_1_jesd/gt5_rxcharisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_6 axi_ad9625_1_jesd/gt6_rxcharisk
|
||||
ad_connect util_bsplit_rx_1_gt_charisk/split_data_7 axi_ad9625_1_jesd/gt7_rxcharisk
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_disperr
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_1_gt_disperr]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_disperr]
|
||||
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/data axi_ad9625_1_gt/rx_gt_disperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_0 axi_ad9625_1_jesd/gt0_rxdisperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_1 axi_ad9625_1_jesd/gt1_rxdisperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_2 axi_ad9625_1_jesd/gt2_rxdisperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_3 axi_ad9625_1_jesd/gt3_rxdisperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_4 axi_ad9625_1_jesd/gt4_rxdisperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_5 axi_ad9625_1_jesd/gt5_rxdisperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_6 axi_ad9625_1_jesd/gt6_rxdisperr
|
||||
ad_connect util_bsplit_rx_1_gt_disperr/split_data_7 axi_ad9625_1_jesd/gt7_rxdisperr
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_notintable
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_1_gt_notintable]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_notintable]
|
||||
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/data axi_ad9625_1_gt/rx_gt_notintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_0 axi_ad9625_1_jesd/gt0_rxnotintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_1 axi_ad9625_1_jesd/gt1_rxnotintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_2 axi_ad9625_1_jesd/gt2_rxnotintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_3 axi_ad9625_1_jesd/gt3_rxnotintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_4 axi_ad9625_1_jesd/gt4_rxnotintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_5 axi_ad9625_1_jesd/gt5_rxnotintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_6 axi_ad9625_1_jesd/gt6_rxnotintable
|
||||
ad_connect util_bsplit_rx_1_gt_notintable/split_data_7 axi_ad9625_1_jesd/gt7_rxnotintable
|
||||
|
||||
create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_1_gt_data
|
||||
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_1_gt_data]
|
||||
set_property -dict [list CONFIG.NUM_OF_CHANNELS {8}] [get_bd_cells util_bsplit_rx_1_gt_data]
|
||||
|
||||
ad_connect util_bsplit_rx_1_gt_data/data axi_ad9625_1_gt/rx_gt_data
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_0 axi_ad9625_1_jesd/gt0_rxdata
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_1 axi_ad9625_1_jesd/gt1_rxdata
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_2 axi_ad9625_1_jesd/gt2_rxdata
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_3 axi_ad9625_1_jesd/gt3_rxdata
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_4 axi_ad9625_1_jesd/gt4_rxdata
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_5 axi_ad9625_1_jesd/gt5_rxdata
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_6 axi_ad9625_1_jesd/gt6_rxdata
|
||||
ad_connect util_bsplit_rx_1_gt_data/split_data_7 axi_ad9625_1_jesd/gt7_rxdata
|
||||
|
||||
ad_connect axi_ad9625_1_gt/rx_rst_done axi_ad9625_1_jesd/rx_reset_done
|
||||
ad_connect axi_ad9625_1_gt/rx_ip_comma_align axi_ad9625_1_jesd/rxencommaalign_out
|
||||
ad_connect axi_ad9625_1_gt/rx_ip_sync axi_ad9625_1_jesd/rx_sync
|
||||
ad_connect axi_ad9625_1_gt/rx_ip_sof axi_ad9625_1_jesd/rx_start_of_frame
|
||||
ad_connect axi_ad9625_1_gt/rx_ip_data axi_ad9625_1_jesd/rx_tdata
|
||||
|
||||
ad_connect axi_ad9625_0_gt/rx_data axi_ad9625_0_core/rx_data
|
||||
ad_connect axi_ad9625_1_gt/rx_data axi_ad9625_1_core/rx_data
|
||||
ad_connect axi_ad9625_0_core/adc_valid adc_valid_0
|
||||
ad_connect axi_ad9625_0_core/adc_enable adc_enable_0
|
||||
ad_connect axi_ad9625_0_core/adc_data adc_data_0
|
||||
ad_connect axi_ad9625_1_core/adc_valid adc_valid_1
|
||||
ad_connect axi_ad9625_1_core/adc_enable adc_enable_1
|
||||
ad_connect axi_ad9625_1_core/adc_data adc_data_1
|
||||
ad_connect adc_wr axi_ad9625_fifo/adc_wr
|
||||
ad_connect adc_wdata axi_ad9625_fifo/adc_wdata
|
||||
ad_connect util_fmcadc5_0_gt/rx_out_clk axi_ad9625_0_core/rx_clk
|
||||
ad_connect util_fmcadc5_1_gt/rx_out_clk axi_ad9625_1_core/rx_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_data axi_ad9625_0_core/rx_data
|
||||
ad_connect util_fmcadc5_1_gt/rx_data axi_ad9625_1_core/rx_data
|
||||
ad_connect axi_ad9625_0_core/adc_clk axi_fmcadc5_cpack/adc_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_rst axi_fmcadc5_cpack/adc_rst
|
||||
ad_connect axi_ad9625_0_core/adc_enable axi_fmcadc5_cpack/adc_enable_0
|
||||
ad_connect axi_ad9625_0_core/adc_valid axi_fmcadc5_cpack/adc_valid_0
|
||||
ad_connect axi_ad9625_0_core/adc_data axi_fmcadc5_cpack/adc_data_0
|
||||
ad_connect axi_ad9625_1_core/adc_enable axi_fmcadc5_cpack/adc_enable_1
|
||||
ad_connect axi_ad9625_1_core/adc_valid axi_fmcadc5_cpack/adc_valid_1
|
||||
ad_connect axi_ad9625_1_core/adc_data axi_fmcadc5_cpack/adc_data_1
|
||||
ad_connect axi_ad9625_0_core/adc_clk axi_ad9625_fifo/adc_clk
|
||||
ad_connect util_fmcadc5_0_gt/rx_rst axi_ad9625_fifo/adc_rst
|
||||
ad_connect axi_fmcadc5_cpack/adc_valid axi_ad9625_fifo/adc_wr
|
||||
ad_connect axi_fmcadc5_cpack/adc_data axi_ad9625_fifo/adc_wdata
|
||||
ad_connect axi_ad9625_0_core/adc_dovf axi_ad9625_fifo/adc_wovf
|
||||
ad_connect axi_ad9625_fifo/dma_clk axi_ad9625_dma/s_axis_aclk
|
||||
ad_connect sys_cpu_clk axi_ad9625_dma/s_axis_aclk
|
||||
ad_connect sys_cpu_clk axi_ad9625_fifo/dma_clk
|
||||
ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
|
||||
ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
|
||||
ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
|
||||
|
|
@ -248,8 +261,8 @@ ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
|
|||
|
||||
# interconnect (cpu)
|
||||
|
||||
ad_cpu_interconnect 0x44a60000 axi_ad9625_0_gt
|
||||
ad_cpu_interconnect 0x44b60000 axi_ad9625_1_gt
|
||||
ad_cpu_interconnect 0x44a60000 axi_fmcadc5_0_gt
|
||||
ad_cpu_interconnect 0x44b60000 axi_fmcadc5_1_gt
|
||||
ad_cpu_interconnect 0x44a10000 axi_ad9625_0_core
|
||||
ad_cpu_interconnect 0x44b10000 axi_ad9625_1_core
|
||||
ad_cpu_interconnect 0x44a91000 axi_ad9625_0_jesd
|
||||
|
|
@ -258,12 +271,12 @@ ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
|
|||
|
||||
# interconnect (gt/adc)
|
||||
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_0_gt/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_1_gt/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_0_gt/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_fmcadc5_1_gt/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_ad9625_dma/m_dest_axi
|
||||
ad_connect sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-13 mb-13 axi_ad9625_dma/irq
|
||||
ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
|
||||
|
||||
|
|
|
|||
|
|
@ -246,51 +246,6 @@ module system_top (
|
|||
wire rx_sysref;
|
||||
wire rx_sync_0;
|
||||
wire rx_sync_1;
|
||||
wire adc_clk;
|
||||
wire adc_valid_0;
|
||||
wire adc_enable_0;
|
||||
wire [255:0] adc_data_0;
|
||||
wire adc_valid_1;
|
||||
wire adc_enable_1;
|
||||
wire [255:0] adc_data_1;
|
||||
|
||||
// interleaving
|
||||
|
||||
always @(posedge adc_clk) begin
|
||||
adc_wr <= adc_enable_0 & adc_enable_1;
|
||||
adc_wdata[((16*31)+15):(16*31)] <= adc_data_1[((16*15)+15):(16*15)];
|
||||
adc_wdata[((16*30)+15):(16*30)] <= adc_data_0[((16*15)+15):(16*15)];
|
||||
adc_wdata[((16*29)+15):(16*29)] <= adc_data_1[((16*14)+15):(16*14)];
|
||||
adc_wdata[((16*28)+15):(16*28)] <= adc_data_0[((16*14)+15):(16*14)];
|
||||
adc_wdata[((16*27)+15):(16*27)] <= adc_data_1[((16*13)+15):(16*13)];
|
||||
adc_wdata[((16*26)+15):(16*26)] <= adc_data_0[((16*13)+15):(16*13)];
|
||||
adc_wdata[((16*25)+15):(16*25)] <= adc_data_1[((16*12)+15):(16*12)];
|
||||
adc_wdata[((16*24)+15):(16*24)] <= adc_data_0[((16*12)+15):(16*12)];
|
||||
adc_wdata[((16*23)+15):(16*23)] <= adc_data_1[((16*11)+15):(16*11)];
|
||||
adc_wdata[((16*22)+15):(16*22)] <= adc_data_0[((16*11)+15):(16*11)];
|
||||
adc_wdata[((16*21)+15):(16*21)] <= adc_data_1[((16*10)+15):(16*10)];
|
||||
adc_wdata[((16*20)+15):(16*20)] <= adc_data_0[((16*10)+15):(16*10)];
|
||||
adc_wdata[((16*19)+15):(16*19)] <= adc_data_1[((16* 9)+15):(16* 9)];
|
||||
adc_wdata[((16*18)+15):(16*18)] <= adc_data_0[((16* 9)+15):(16* 9)];
|
||||
adc_wdata[((16*17)+15):(16*17)] <= adc_data_1[((16* 8)+15):(16* 8)];
|
||||
adc_wdata[((16*16)+15):(16*16)] <= adc_data_0[((16* 8)+15):(16* 8)];
|
||||
adc_wdata[((16*15)+15):(16*15)] <= adc_data_1[((16* 7)+15):(16* 7)];
|
||||
adc_wdata[((16*14)+15):(16*14)] <= adc_data_0[((16* 7)+15):(16* 7)];
|
||||
adc_wdata[((16*13)+15):(16*13)] <= adc_data_1[((16* 6)+15):(16* 6)];
|
||||
adc_wdata[((16*12)+15):(16*12)] <= adc_data_0[((16* 6)+15):(16* 6)];
|
||||
adc_wdata[((16*11)+15):(16*11)] <= adc_data_1[((16* 5)+15):(16* 5)];
|
||||
adc_wdata[((16*10)+15):(16*10)] <= adc_data_0[((16* 5)+15):(16* 5)];
|
||||
adc_wdata[((16* 9)+15):(16* 9)] <= adc_data_1[((16* 4)+15):(16* 4)];
|
||||
adc_wdata[((16* 8)+15):(16* 8)] <= adc_data_0[((16* 4)+15):(16* 4)];
|
||||
adc_wdata[((16* 7)+15):(16* 7)] <= adc_data_1[((16* 3)+15):(16* 3)];
|
||||
adc_wdata[((16* 6)+15):(16* 6)] <= adc_data_0[((16* 3)+15):(16* 3)];
|
||||
adc_wdata[((16* 5)+15):(16* 5)] <= adc_data_1[((16* 2)+15):(16* 2)];
|
||||
adc_wdata[((16* 4)+15):(16* 4)] <= adc_data_0[((16* 2)+15):(16* 2)];
|
||||
adc_wdata[((16* 3)+15):(16* 3)] <= adc_data_1[((16* 1)+15):(16* 1)];
|
||||
adc_wdata[((16* 2)+15):(16* 2)] <= adc_data_0[((16* 1)+15):(16* 1)];
|
||||
adc_wdata[((16* 1)+15):(16* 1)] <= adc_data_1[((16* 0)+15):(16* 0)];
|
||||
adc_wdata[((16* 0)+15):(16* 0)] <= adc_data_0[((16* 0)+15):(16* 0)];
|
||||
end
|
||||
|
||||
// spi
|
||||
|
||||
|
|
@ -378,15 +333,6 @@ module system_top (
|
|||
.dio_p (gpio_bd));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.adc_clk (adc_clk),
|
||||
.adc_data_0 (adc_data_0),
|
||||
.adc_data_1 (adc_data_1),
|
||||
.adc_enable_0 (adc_enable_0),
|
||||
.adc_enable_1 (adc_enable_1),
|
||||
.adc_valid_0 (adc_valid_0),
|
||||
.adc_valid_1 (adc_valid_1),
|
||||
.adc_wdata (adc_wdata),
|
||||
.adc_wr (adc_wr),
|
||||
.ddr3_addr (ddr3_addr),
|
||||
.ddr3_ba (ddr3_ba),
|
||||
.ddr3_cas_n (ddr3_cas_n),
|
||||
|
|
@ -420,7 +366,7 @@ module system_top (
|
|||
.mb_intr_06 (1'b0),
|
||||
.mb_intr_07 (1'b0),
|
||||
.mb_intr_08 (1'b0),
|
||||
.mb_intr_12 (1'b0),
|
||||
.mb_intr_13 (1'b0),
|
||||
.mb_intr_14 (1'b0),
|
||||
.mb_intr_15 (1'b0),
|
||||
.mdio_mdc (mdio_mdc),
|
||||
|
|
|
|||
Loading…
Reference in New Issue