diff --git a/projects/ad6676evb/vc707/system_constr.xdc b/projects/ad6676evb/vc707/system_constr.xdc index 2598be3e3..0da921f4b 100644 --- a/projects/ad6676evb/vc707/system_constr.xdc +++ b/projects/ad6676evb/vc707/system_constr.xdc @@ -33,8 +33,3 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_agc4] create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] - diff --git a/projects/ad6676evb/zc706/system_constr.xdc b/projects/ad6676evb/zc706/system_constr.xdc index 09ac1b25a..7a7d74f54 100644 --- a/projects/ad6676evb/zc706/system_constr.xdc +++ b/projects/ad6676evb/zc706/system_constr.xdc @@ -32,9 +32,3 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_agc4 create_clock -name rx_ref_clk -period 5.00 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 10.00 [get_pins i_system_wrapper/system_i/util_ad6676_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] - -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad6676_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - -set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}] -set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] - diff --git a/projects/adrv9371x/kcu105/system_constr.xdc b/projects/adrv9371x/kcu105/system_constr.xdc index 90d5c12a4..aec9af03f 100644 --- a/projects/adrv9371x/kcu105/system_constr.xdc +++ b/projects/adrv9371x/kcu105/system_constr.xdc @@ -87,6 +87,3 @@ set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ * set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ *util_ad9371_xcvr/inst/i_xch_2/i_gthe3_channel}] set_property LOC GTHE3_CHANNEL_X0Y19 [get_cells -hierarchical -filter {NAME =~ *util_ad9371_xcvr/inst/i_xch_3/i_gthe3_channel}] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] diff --git a/projects/adrv9371x/zc706/system_constr.xdc b/projects/adrv9371x/zc706/system_constr.xdc index fa75a515d..570b1f9b9 100644 --- a/projects/adrv9371x/zc706/system_constr.xdc +++ b/projects/adrv9371x/zc706/system_constr.xdc @@ -74,7 +74,3 @@ create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/syste create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - diff --git a/projects/adrv9371x/zcu102/system_constr.xdc b/projects/adrv9371x/zcu102/system_constr.xdc index 7eba6f5b3..370f8e969 100644 --- a/projects/adrv9371x/zcu102/system_constr.xdc +++ b/projects/adrv9371x/zcu102/system_constr.xdc @@ -58,14 +58,11 @@ set_property LOC GTHE4_CHANNEL_X1Y8 [get_cells -hierarchical -filter {NAME =~ * create_clock -name tx_ref_clk -period 8.00 [get_ports ref_clk0_p] create_clock -name rx_ref_clk -period 8.00 [get_ports ref_clk1_p] + create_clock -name tx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK] create_clock -name rx_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK] create_clock -name rx_os_div_clk -period 8.00 [get_pins i_system_wrapper/system_i/util_ad9371_xcvr/inst/i_xch_2/i_gthe4_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9371_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - # pin assignments below are for reference only and are ignored by the tool! # set_property -dict {PACKAGE_PIN G8 } [get_ports ref_clk0_p] ; ## D04 FMC_HPC0_GBTCLK0_M2C_C_P diff --git a/projects/adrv9379/zc706/system_constr.xdc b/projects/adrv9379/zc706/system_constr.xdc index b1afbfafa..657b07f19 100644 --- a/projects/adrv9379/zc706/system_constr.xdc +++ b/projects/adrv9379/zc706/system_constr.xdc @@ -77,8 +77,3 @@ create_clock -name rx_ref_clk -period 4.00 [get_ports ref_clk1_p] create_clock -name tx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] create_clock -name rx_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] create_clock -name rx_os_div_clk -period 4.00 [get_pins i_system_wrapper/system_i/util_ad9379_xcvr/inst/i_xch_2/i_gtxe2_channel/RXOUTCLK] - -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_rx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_tx_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9379_rx_os_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - diff --git a/projects/daq2/kcu105/system_constr.xdc b/projects/daq2/kcu105/system_constr.xdc index c4125d861..ad505988d 100644 --- a/projects/daq2/kcu105/system_constr.xdc +++ b/projects/daq2/kcu105/system_constr.xdc @@ -67,6 +67,3 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ * set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_2/i_gthe3_channel}] set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq2_xcvr/inst/i_xch_3/i_gthe3_channel}] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9144_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - diff --git a/projects/daq3/kcu105/system_constr.xdc b/projects/daq3/kcu105/system_constr.xdc index 899f59fbd..d927d5d29 100644 --- a/projects/daq3/kcu105/system_constr.xdc +++ b/projects/daq3/kcu105/system_constr.xdc @@ -67,6 +67,3 @@ set_property LOC GTHE3_CHANNEL_X0Y16 [get_cells -hierarchical -filter {NAME =~ * set_property LOC GTHE3_CHANNEL_X0Y18 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_2/i_gthe3_channel}] set_property LOC GTHE3_CHANNEL_X0Y17 [get_cells -hierarchical -filter {NAME =~ *util_daq3_xcvr/inst/i_xch_3/i_gthe3_channel}] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] - diff --git a/projects/daq3/zc706/system_constr.xdc b/projects/daq3/zc706/system_constr.xdc index 1cfd829a1..69323f5c7 100644 --- a/projects/daq3/zc706/system_constr.xdc +++ b/projects/daq3/zc706/system_constr.xdc @@ -57,6 +57,6 @@ create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] +#set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] +#set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] diff --git a/projects/daq3/zcu102/system_constr.xdc b/projects/daq3/zcu102/system_constr.xdc index d6637581d..dce20ac94 100644 --- a/projects/daq3/zcu102/system_constr.xdc +++ b/projects/daq3/zcu102/system_constr.xdc @@ -48,9 +48,6 @@ create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/TXOUTCLK] create_clock -name rx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_daq3_xcvr/inst/i_xch_0/i_gthe4_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9680_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9152_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] - # pin assignments below are for reference only and are ignored by the tool! # set_property -dict {PACKAGE_PIN L8 } [get_ports rx_ref_clk_p] ; ## B20 FMC_HPC0_GBTCLK1_M2C_C_P diff --git a/projects/fmcadc2/vc707/system_constr.xdc b/projects/fmcadc2/vc707/system_constr.xdc index 2de57cd6f..260dda3d9 100644 --- a/projects/fmcadc2/vc707/system_constr.xdc +++ b/projects/fmcadc2/vc707/system_constr.xdc @@ -40,7 +40,6 @@ set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] set_property IOB false [get_cells -hierarchical -filter {name =~ *SCK_O_NE_4_FDRE_INST}] set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}] diff --git a/projects/fmcadc2/zc706/system_constr.xdc b/projects/fmcadc2/zc706/system_constr.xdc index 60680277e..36c3ec8dd 100644 --- a/projects/fmcadc2/zc706/system_constr.xdc +++ b/projects/fmcadc2/zc706/system_constr.xdc @@ -40,8 +40,6 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS25} [get_ports adc_fd] create_clock -name rx_ref_clk -period 1.60 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}] set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcadc5/vc707/system_constr.xdc b/projects/fmcadc5/vc707/system_constr.xdc index 79083f710..9a8064baf 100644 --- a/projects/fmcadc5/vc707/system_constr.xdc +++ b/projects/fmcadc5/vc707/system_constr.xdc @@ -86,7 +86,4 @@ create_clock -name rx_ref_clk_0 -period 1.60 [get_ports rx_ref_clk_0_p] create_clock -name rx_ref_clk_1 -period 1.60 [get_ports rx_ref_clk_1_p] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcadc5_0_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_0_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] set_property IOB false [get_cells -hierarchical -filter {name =~ *SCK_O_NE_4_FDRE_INST}] - - diff --git a/projects/fmcjesdadc1/kc705/system_constr.xdc b/projects/fmcjesdadc1/kc705/system_constr.xdc index 733b158bd..d0f477aaf 100644 --- a/projects/fmcjesdadc1/kc705/system_constr.xdc +++ b/projects/fmcjesdadc1/kc705/system_constr.xdc @@ -23,8 +23,6 @@ set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports spi_sdio create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}] set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcjesdadc1/vc707/system_constr.xdc b/projects/fmcjesdadc1/vc707/system_constr.xdc index 03e82eaef..3766e2727 100644 --- a/projects/fmcjesdadc1/vc707/system_constr.xdc +++ b/projects/fmcjesdadc1/vc707/system_constr.xdc @@ -23,8 +23,6 @@ set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS18} [get_ports spi_sdio create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}] set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcjesdadc1/zc706/system_constr.xdc b/projects/fmcjesdadc1/zc706/system_constr.xdc index d5ae14ff2..1c8345f10 100644 --- a/projects/fmcjesdadc1/zc706/system_constr.xdc +++ b/projects/fmcjesdadc1/zc706/system_constr.xdc @@ -23,8 +23,6 @@ set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]] - set_property ASYNC_REG TRUE [get_cells -hier -filter {name =~ *sysref_en_m*}] set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m1* && IS_SEQUENTIAL}] diff --git a/projects/fmcomms11/zc706/system_constr.xdc b/projects/fmcomms11/zc706/system_constr.xdc index 8d004dcfc..178bd8698 100644 --- a/projects/fmcomms11/zc706/system_constr.xdc +++ b/projects/fmcomms11/zc706/system_constr.xdc @@ -64,7 +64,3 @@ set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVCMOS25} [get_ports ad9162_i create_clock -name rx_ref_clk -period 6.40 [get_ports trx_ref_clk_p] create_clock -name tx_div_clk -period 3.20 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/TXOUTCLK] create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcomms11_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK] - -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9162_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] -set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]*] -