adrv9371x- altera updates
Rejeesh Kutty
parent
f752f0c9d7
commit
50552ce7d6
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@ -41,140 +41,72 @@ module system_top (
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// clock and resets
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sys_clk,
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sys_resetn,
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input sys_clk,
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input sys_resetn,
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// ddr3
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ddr3_clk_p,
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ddr3_clk_n,
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ddr3_a,
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ddr3_ba,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_odt,
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ddr3_reset_n,
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ddr3_we_n,
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ddr3_ras_n,
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ddr3_cas_n,
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ddr3_dqs_p,
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ddr3_dqs_n,
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ddr3_dq,
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ddr3_dm,
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ddr3_rzq,
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ddr3_ref_clk,
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output ddr3_clk_p,
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output ddr3_clk_n,
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output [ 14:0] ddr3_a,
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output [ 2:0] ddr3_ba,
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_odt,
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output ddr3_reset_n,
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output ddr3_we_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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inout [ 7:0] ddr3_dqs_p,
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inout [ 7:0] ddr3_dqs_n,
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inout [ 63:0] ddr3_dq,
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output [ 7:0] ddr3_dm,
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input ddr3_rzq,
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input ddr3_ref_clk,
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// ethernet
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eth_ref_clk,
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eth_rxd,
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eth_txd,
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eth_mdc,
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eth_mdio,
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eth_resetn,
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eth_intn,
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input eth_ref_clk,
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input eth_rxd,
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output eth_txd,
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output eth_mdc,
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inout eth_mdio,
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output eth_resetn,
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input eth_intn,
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// board gpio
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gpio_bd_i,
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gpio_bd_o,
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input [ 10:0] gpio_bd_i,
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output [ 15:0] gpio_bd_o,
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// lane interface
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ref_clk0,
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ref_clk1,
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rx_data,
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tx_data,
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rx_sync,
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rx_os_sync,
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tx_sync,
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sysref,
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input ref_clk0,
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input ref_clk1,
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input [ 3:0] rx_data,
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output [ 3:0] tx_data,
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output rx_sync,
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output rx_os_sync,
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input tx_sync,
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input sysref,
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ad9528_reset_b,
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ad9528_sysref_req,
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ad9371_tx1_enable,
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ad9371_tx2_enable,
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ad9371_rx1_enable,
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ad9371_rx2_enable,
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ad9371_test,
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ad9371_reset_b,
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ad9371_gpint,
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ad9371_gpio,
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output ad9528_reset_b,
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output ad9528_sysref_req,
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output ad9371_tx1_enable,
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output ad9371_tx2_enable,
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output ad9371_rx1_enable,
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output ad9371_rx2_enable,
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output ad9371_test,
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output ad9371_reset_b,
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input ad9371_gpint,
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spi_csn_ad9528,
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spi_csn_ad9371,
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spi_clk,
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spi_mosi,
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spi_miso);
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inout [ 18:0] ad9371_gpio,
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// clock and resets
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input sys_clk;
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input sys_resetn;
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// ddr3
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output ddr3_clk_p;
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output ddr3_clk_n;
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output [ 14:0] ddr3_a;
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output [ 2:0] ddr3_ba;
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output ddr3_cke;
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output ddr3_cs_n;
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output ddr3_odt;
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output ddr3_reset_n;
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output ddr3_we_n;
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output ddr3_ras_n;
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output ddr3_cas_n;
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inout [ 7:0] ddr3_dqs_p;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 63:0] ddr3_dq;
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output [ 7:0] ddr3_dm;
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input ddr3_rzq;
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input ddr3_ref_clk;
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// ethernet
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input eth_ref_clk;
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input eth_rxd;
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output eth_txd;
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output eth_mdc;
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inout eth_mdio;
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output eth_resetn;
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input eth_intn;
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// board gpio
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input [ 10:0] gpio_bd_i;
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output [ 15:0] gpio_bd_o;
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// lane interface
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input ref_clk0;
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input ref_clk1;
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input [ 3:0] rx_data;
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output [ 3:0] tx_data;
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output rx_sync;
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output rx_os_sync;
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input tx_sync;
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input sysref;
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output ad9528_reset_b;
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output ad9528_sysref_req;
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output ad9371_tx1_enable;
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output ad9371_tx2_enable;
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output ad9371_rx1_enable;
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output ad9371_rx2_enable;
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output ad9371_test;
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output ad9371_reset_b;
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input ad9371_gpint;
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inout [ 18:0] ad9371_gpio;
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output spi_csn_ad9528;
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output spi_csn_ad9371;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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output spi_csn_ad9528,
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output spi_csn_ad9371,
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output spi_clk,
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output spi_mosi,
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input spi_miso);
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// internal signals
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@ -186,6 +118,8 @@ module system_top (
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wire [ 63:0] gpio_o;
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wire [ 7:0] spi_csn_s;
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// assignments
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assign spi_csn_ad9371 = spi_csn_s[0];
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assign spi_csn_ad9528 = spi_csn_s[1];
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@ -219,6 +153,17 @@ module system_top (
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assign gpio_bd_o = gpio_o[15:0];
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system_bd i_system_bd (
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.avl_ad9371_gpio_export(ad9371_gpio),
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.rx_data_0_rx_serial_data (rx_data[0]),
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.rx_data_1_rx_serial_data (rx_data[1]),
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.rx_data_2_rx_serial_data (rx_data[2]),
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.rx_data_3_rx_serial_data (rx_data[3]),
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.rx_os_ref_clk_clk (ref_clk1),
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.rx_os_sync_export (rx_os_sync),
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.rx_os_sysref_export (sysref),
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.rx_ref_clk_clk (ref_clk1),
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.rx_sync_export (rx_sync),
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.rx_sysref_export (sysref),
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.sys_clk_clk (sys_clk),
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.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
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.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
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@ -254,18 +199,13 @@ module system_top (
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.sys_spi_MOSI (spi_mosi),
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.sys_spi_SCLK (spi_clk),
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.sys_spi_SS_n (spi_csn_s),
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.ad9371_gpio_export(ad9371_gpio),
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.xcvr_ref_clk_clk(ref_clk1),
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.rx_data_rx_serial_data (rx_data[1:0]),
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.rx_os_data_rx_serial_data (rx_data[3:2]),
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.rx_os_sync_rx_sync (rx_os_sync),
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.rx_os_sysref_rx_ext_sysref_in (sysref),
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.rx_sync_rx_sync (rx_sync),
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.rx_sysref_rx_ext_sysref_in (sysref),
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.tx_data_tx_serial_data ({tx_data[0],tx_data[3],tx_data[2],tx_data[1]}),
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.tx_sync_tx_sync (tx_sync),
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.tx_sysref_tx_ext_sysref_in (sysref)
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);
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.tx_data_0_tx_serial_data (tx_data[0]),
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.tx_data_1_tx_serial_data (tx_data[1]),
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.tx_data_2_tx_serial_data (tx_data[2]),
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.tx_data_3_tx_serial_data (tx_data[3]),
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.tx_ref_clk_clk (ref_clk1),
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.tx_sync_export (tx_sync),
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.tx_sysref_export (sysref));
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endmodule
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@ -25,7 +25,6 @@ set_instance_parameter_value sys_int_mem {dataWidth} {32}
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set_instance_parameter_value sys_int_mem {dualPort} {0}
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set_instance_parameter_value sys_int_mem {initMemContent} {0}
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set_instance_parameter_value sys_int_mem {memorySize} {163840.0}
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add_connection sys_clk.clk sys_int_mem.clk1
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add_connection sys_clk.clk_reset sys_int_mem.reset1
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@ -36,7 +35,6 @@ set_instance_parameter_value sys_tlb_mem {dataWidth} {32}
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set_instance_parameter_value sys_tlb_mem {dualPort} {1}
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set_instance_parameter_value sys_tlb_mem {initMemContent} {1}
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set_instance_parameter_value sys_tlb_mem {memorySize} {163840.0}
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add_connection sys_clk.clk sys_tlb_mem.clk1
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add_connection sys_clk.clk_reset sys_tlb_mem.reset1
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add_connection sys_clk.clk sys_tlb_mem.clk2
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@ -72,12 +70,10 @@ set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRCD_NS} {10.285}
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set_instance_parameter_value sys_ddr3_cntrl {MEM_DDR3_TRP_NS} {10.285}
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set_instance_parameter_value sys_ddr3_cntrl {BOARD_DDR3_USER_RCLK_SLEW_RATE} {4.0}
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set_instance_parameter_value sys_ddr3_cntrl {SHORT_QSYS_INTERFACE_NAMES} {1}
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add_connection sys_clk.clk_reset sys_ddr3_cntrl.global_reset_n
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add_interface sys_ddr3_cntrl_mem conduit end
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add_interface sys_ddr3_cntrl_oct conduit end
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add_interface sys_ddr3_cntrl_pll_ref_clk clock sink
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set_interface_property sys_ddr3_cntrl_mem EXPORT_OF sys_ddr3_cntrl.mem
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set_interface_property sys_ddr3_cntrl_oct EXPORT_OF sys_ddr3_cntrl.oct
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set_interface_property sys_ddr3_cntrl_pll_ref_clk EXPORT_OF sys_ddr3_cntrl.pll_ref_clk
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@ -103,19 +99,47 @@ set_instance_parameter_value sys_cpu {setting_dc_ecc_present} {0}
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set_instance_parameter_value sys_cpu {setting_itcm_ecc_present} {0}
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set_instance_parameter_value sys_cpu {setting_dtcm_ecc_present} {0}
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set_instance_parameter_value sys_cpu {mmu_enabled} $mmu_enabled
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add_connection sys_clk.clk sys_cpu.clk
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add_connection sys_clk.clk_reset sys_cpu.reset
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add_connection sys_cpu.debug_reset_request sys_cpu.reset
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add_connection sys_cpu.instruction_master sys_cpu.debug_mem_slave
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add_connection sys_cpu.data_master sys_cpu.debug_mem_slave
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add_connection sys_cpu.instruction_master sys_int_mem.s1
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add_connection sys_cpu.data_master sys_int_mem.s1
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add_connection sys_cpu.tightly_coupled_instruction_master_0 sys_tlb_mem.s2
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add_connection sys_cpu.tightly_coupled_data_master_0 sys_tlb_mem.s1
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add_connection sys_cpu.instruction_master sys_ddr3_cntrl.ctrl_amm_0
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add_connection sys_cpu.data_master sys_ddr3_cntrl.ctrl_amm_0
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set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0}
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set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0}
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set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
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set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000}
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set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000}
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set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000}
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# cpu/hps handling
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proc ad_cpu_interrupt {m_irq m_port} {
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add_connection sys_cpu.irq ${m_port}
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set_connection_parameter_value sys_cpu.irq/${m_port} irqNumber ${m_irq}
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}
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proc ad_cpu_interconnect {m_base m_port} {
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add_connection sys_cpu.data_master ${m_port}
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set_connection_parameter_value sys_cpu.data_master/${m_port} baseAddress [expr ($m_base + 0x10000000)]
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}
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proc ad_dma_interconnect {m_port} {
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add_connection ${m_port} sys_ddr3_cntrl.ctrl_amm_0
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set_connection_parameter_value ${m_port}/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x0}
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}
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# common dma interfaces
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add_instance sys_dma_clk clock_source 16.0
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add_connection sys_ddr3_cntrl.emif_usr_clk sys_dma_clk.clk_in
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add_connection sys_ddr3_cntrl.emif_usr_reset_n sys_dma_clk.clk_in_reset
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# ethernet
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@ -172,18 +196,8 @@ add_connection sys_clk.clk sys_ethernet.transmit_clock_connection
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add_connection sys_clk.clk sys_ethernet_dma_rx.clock
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add_connection sys_clk.clk sys_ethernet_dma_tx.clock
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add_connection sys_clk.clk sys_ethernet_reset.clk
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add_connection sys_cpu.data_master sys_ethernet.control_port
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add_connection sys_cpu.data_master sys_ethernet_dma_rx.csr
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add_connection sys_cpu.data_master sys_ethernet_dma_rx.response
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add_connection sys_cpu.data_master sys_ethernet_dma_rx.descriptor_slave
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add_connection sys_cpu.data_master sys_ethernet_dma_tx.csr
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add_connection sys_cpu.data_master sys_ethernet_dma_tx.descriptor_slave
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add_connection sys_cpu.irq sys_ethernet_dma_rx.csr_irq
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add_connection sys_cpu.irq sys_ethernet_dma_tx.csr_irq
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add_connection sys_ethernet.receive sys_ethernet_dma_rx.st_sink
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add_connection sys_ethernet_dma_tx.st_source sys_ethernet.transmit
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add_connection sys_ethernet_dma_rx.mm_write sys_ddr3_cntrl.ctrl_amm_0
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add_connection sys_ethernet_dma_tx.mm_read sys_ddr3_cntrl.ctrl_amm_0
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add_interface sys_ethernet_reset reset source
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add_interface sys_ethernet_ref_clk clock sink
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add_interface sys_ethernet_mdio conduit end
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@ -198,40 +212,29 @@ set_interface_property sys_ethernet_sgmii EXPORT_OF sys_ethernet.serial_connecti
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add_instance sys_id altera_avalon_sysid_qsys 16.0
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set_instance_parameter_value sys_id {id} {182193580}
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add_connection sys_clk.clk_reset sys_id.reset
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add_connection sys_clk.clk sys_id.clk
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add_connection sys_cpu.data_master sys_id.control_slave
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# timer-1
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add_instance sys_timer_1 altera_avalon_timer 16.0
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set_instance_parameter_value sys_timer_1 {counterSize} {32}
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add_connection sys_clk.clk_reset sys_timer_1.reset
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add_connection sys_clk.clk sys_timer_1.clk
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add_connection sys_cpu.data_master sys_timer_1.s1
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add_connection sys_cpu.irq sys_timer_1.irq
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# timer-2
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add_instance sys_timer_2 altera_avalon_timer 16.0
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set_instance_parameter_value sys_timer_2 {counterSize} {32}
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add_connection sys_clk.clk_reset sys_timer_2.reset
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add_connection sys_clk.clk sys_timer_2.clk
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add_connection sys_cpu.data_master sys_timer_2.s1
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add_connection sys_cpu.irq sys_timer_2.irq
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# uart
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add_instance sys_uart altera_avalon_jtag_uart 16.0
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set_instance_parameter_value sys_uart {allowMultipleConnections} {0}
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add_connection sys_clk.clk_reset sys_uart.reset
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add_connection sys_clk.clk sys_uart.clk
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add_connection sys_cpu.data_master sys_uart.avalon_jtag_slave
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add_connection sys_cpu.irq sys_uart.irq
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# gpio-bd
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@ -239,13 +242,9 @@ add_instance sys_gpio_bd altera_avalon_pio 16.0
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set_instance_parameter_value sys_gpio_bd {direction} {InOut}
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set_instance_parameter_value sys_gpio_bd {generateIRQ} {1}
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set_instance_parameter_value sys_gpio_bd {width} {32}
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add_connection sys_clk.clk_reset sys_gpio_bd.reset
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add_connection sys_clk.clk sys_gpio_bd.clk
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add_connection sys_cpu.data_master sys_gpio_bd.s1
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add_connection sys_cpu.irq sys_gpio_bd.irq
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add_interface sys_gpio_bd conduit end
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set_interface_property sys_gpio_bd EXPORT_OF sys_gpio_bd.external_connection
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# gpio-in
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@ -254,13 +253,9 @@ add_instance sys_gpio_in altera_avalon_pio 16.0
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set_instance_parameter_value sys_gpio_in {direction} {Input}
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set_instance_parameter_value sys_gpio_in {generateIRQ} {1}
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set_instance_parameter_value sys_gpio_in {width} {32}
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add_connection sys_clk.clk_reset sys_gpio_in.reset
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add_connection sys_clk.clk sys_gpio_in.clk
|
||||
add_connection sys_cpu.data_master sys_gpio_in.s1
|
||||
add_connection sys_cpu.irq sys_gpio_in.irq
|
||||
add_interface sys_gpio_in conduit end
|
||||
|
||||
set_interface_property sys_gpio_in EXPORT_OF sys_gpio_in.external_connection
|
||||
|
||||
# gpio-out
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||||
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@ -269,12 +264,9 @@ add_instance sys_gpio_out altera_avalon_pio 16.0
|
|||
set_instance_parameter_value sys_gpio_out {direction} {Output}
|
||||
set_instance_parameter_value sys_gpio_out {generateIRQ} {0}
|
||||
set_instance_parameter_value sys_gpio_out {width} {32}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_gpio_out.reset
|
||||
add_connection sys_clk.clk sys_gpio_out.clk
|
||||
add_connection sys_cpu.data_master sys_gpio_out.s1
|
||||
add_interface sys_gpio_out conduit end
|
||||
|
||||
set_interface_property sys_gpio_out EXPORT_OF sys_gpio_out.external_connection
|
||||
|
||||
# spi
|
||||
|
|
@ -286,51 +278,44 @@ set_instance_parameter_value sys_spi {dataWidth} {8}
|
|||
set_instance_parameter_value sys_spi {masterSPI} {1}
|
||||
set_instance_parameter_value sys_spi {numberOfSlaves} {8}
|
||||
set_instance_parameter_value sys_spi {targetClockRate} {128000.0}
|
||||
|
||||
add_connection sys_clk.clk_reset sys_spi.reset
|
||||
add_connection sys_clk.clk sys_spi.clk
|
||||
add_connection sys_cpu.data_master sys_spi.spi_control_port
|
||||
add_connection sys_cpu.irq sys_spi.irq
|
||||
add_interface sys_spi conduit end
|
||||
|
||||
set_interface_property sys_spi EXPORT_OF sys_spi.external
|
||||
|
||||
# addresses
|
||||
# base-addresses
|
||||
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_int_mem.s1 baseAddress {0x10140000}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_uart.avalon_jtag_slave baseAddress {0x101814f0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet.control_port baseAddress {0x10181000}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.csr baseAddress {0x101814a0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.response baseAddress {0x101814e0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_rx.descriptor_slave baseAddress {0x10181440}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.csr baseAddress {0x10181480}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_ethernet_dma_tx.descriptor_slave baseAddress {0x10181460}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_spi.spi_control_port baseAddress {0x10181400}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_gpio_out.s1 baseAddress {0x10181500}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_gpio_in.s1 baseAddress {0x101814c0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_gpio_bd.s1 baseAddress {0x101814d0}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_timer_2.s1 baseAddress {0x10181520}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_timer_1.s1 baseAddress {0x10181420}
|
||||
set_connection_parameter_value sys_cpu.data_master/sys_id.control_slave baseAddress {0x101814e8}
|
||||
set_connection_parameter_value sys_cpu.instruction_master/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value sys_cpu.instruction_master/sys_cpu.debug_mem_slave baseAddress {0x10180800}
|
||||
set_connection_parameter_value sys_cpu.instruction_master/sys_int_mem.s1 baseAddress {0x10140000}
|
||||
set_connection_parameter_value sys_cpu.tightly_coupled_instruction_master_0/sys_tlb_mem.s2 baseAddress {0x10200000}
|
||||
set_connection_parameter_value sys_cpu.tightly_coupled_data_master_0/sys_tlb_mem.s1 baseAddress {0x10200000}
|
||||
set_connection_parameter_value sys_ethernet_dma_tx.mm_read/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
set_connection_parameter_value sys_ethernet_dma_rx.mm_write/sys_ddr3_cntrl.ctrl_amm_0 baseAddress {0x00000000}
|
||||
ad_cpu_interconnect 0x00180800 sys_cpu.debug_mem_slave
|
||||
ad_cpu_interconnect 0x00140000 sys_int_mem.s1
|
||||
ad_cpu_interconnect 0x00181000 sys_ethernet.control_port
|
||||
ad_cpu_interconnect 0x001814a0 sys_ethernet_dma_rx.csr
|
||||
ad_cpu_interconnect 0x001814e0 sys_ethernet_dma_rx.response
|
||||
ad_cpu_interconnect 0x00181440 sys_ethernet_dma_rx.descriptor_slave
|
||||
ad_cpu_interconnect 0x00181480 sys_ethernet_dma_tx.csr
|
||||
ad_cpu_interconnect 0x00181460 sys_ethernet_dma_tx.descriptor_slave
|
||||
ad_cpu_interconnect 0x001814e8 sys_id.control_slave
|
||||
ad_cpu_interconnect 0x00181420 sys_timer_1.s1
|
||||
ad_cpu_interconnect 0x00181520 sys_timer_2.s1
|
||||
ad_cpu_interconnect 0x001814f0 sys_uart.avalon_jtag_slave
|
||||
ad_cpu_interconnect 0x001814d0 sys_gpio_bd.s1
|
||||
ad_cpu_interconnect 0x001814c0 sys_gpio_in.s1
|
||||
ad_cpu_interconnect 0x00181500 sys_gpio_out.s1
|
||||
ad_cpu_interconnect 0x00181400 sys_spi.spi_control_port
|
||||
|
||||
set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_rx.csr_irq irqNumber {0}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_ethernet_dma_tx.csr_irq irqNumber {1}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_uart.irq irqNumber {2}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_timer_2.irq irqNumber {3}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_timer_1.irq irqNumber {4}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_gpio_in.irq irqNumber {5}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_gpio_bd.irq irqNumber {6}
|
||||
set_connection_parameter_value sys_cpu.irq/sys_spi.irq irqNumber {7}
|
||||
# dma interconnects
|
||||
|
||||
ad_dma_interconnect sys_ethernet_dma_tx.mm_read
|
||||
ad_dma_interconnect sys_ethernet_dma_rx.mm_write
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt 0 sys_ethernet_dma_rx.csr_irq
|
||||
ad_cpu_interrupt 1 sys_ethernet_dma_tx.csr_irq
|
||||
ad_cpu_interrupt 2 sys_uart.irq
|
||||
ad_cpu_interrupt 3 sys_timer_2.irq
|
||||
ad_cpu_interrupt 4 sys_timer_1.irq
|
||||
ad_cpu_interrupt 5 sys_gpio_in.irq
|
||||
ad_cpu_interrupt 6 sys_gpio_bd.irq
|
||||
ad_cpu_interrupt 7 sys_spi.irq
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -189,6 +189,12 @@ proc ad_dma_interconnect {m_port} {
|
|||
set_connection_parameter_value ${m_port}/sys_hps.f2sdram0_data baseAddress {0x0}
|
||||
}
|
||||
|
||||
# common dma interfaces
|
||||
|
||||
add_instance sys_dma_clk clock_source 16.0
|
||||
add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
|
||||
add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
|
||||
|
||||
# gpio-in
|
||||
|
||||
add_instance sys_gpio_in altera_avalon_pio 16.0
|
||||
|
|
@ -239,9 +245,3 @@ ad_cpu_interconnect 0x00000040 sys_spi.spi_control_port
|
|||
ad_cpu_interrupt 5 sys_gpio_in.irq
|
||||
ad_cpu_interrupt 7 sys_spi.irq
|
||||
|
||||
# common dma interfaces
|
||||
|
||||
add_instance sys_dma_clk clock_source 16.0
|
||||
add_connection sys_hps.h2f_user0_clock sys_dma_clk.clk_in
|
||||
add_connection sys_clk.clk_reset sys_dma_clk.clk_in_reset
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue