From 508a783f391385872f492d6c8f3edb25169af282 Mon Sep 17 00:00:00 2001
From: Lars-Peter Clausen <lars@metafoo.de>
Date: Mon, 10 Apr 2017 10:59:32 +0200
Subject: [PATCH] axi_dac_interpolate: Register output mux signal

The output data mux is used to bypass the filter when it is not used. Which
setting is used for the mux depends on the 3-bit filter_mask signal.
Registering the control logic into a single bit signal reduces the amount
of routing resources required. Since changing the filter_mask settings is
asynchronous to the processing anyway the extra clock cycle delay
introduced by this change does not affect behaviour.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
---
 .../axi_dac_interpolate_filter.v              | 27 ++++++++++---------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v
index f3c250c71..bc79a8111 100644
--- a/library/axi_dac_interpolate/axi_dac_interpolate_filter.v
+++ b/library/axi_dac_interpolate/axi_dac_interpolate_filter.v
@@ -61,6 +61,8 @@ module axi_dac_interpolate_filter (
   reg               cic_change_rate;
   reg     [31:0]    interpolation_counter;
 
+  reg               filter_enable = 1'b0;
+
   wire              dac_fir_valid;
   wire    [35:0]    dac_fir_data;
 
@@ -112,23 +114,22 @@ module axi_dac_interpolate_filter (
     end
   end
 
-  always @(*) begin
+  always @(posedge dac_clk) begin
     case (filter_mask)
-      3'h1: dac_int_data = dac_cic_data[31:16];
-      3'h2: dac_int_data = dac_cic_data[31:16];
-      3'h3: dac_int_data = dac_cic_data[31:16];
-      3'h6: dac_int_data = dac_cic_data[31:16];
-      3'h7: dac_int_data = dac_cic_data[31:16];
-      default: dac_int_data = dac_data;
+      3'b000: filter_enable <= 1'b0;
+      default: filter_enable <= 1'b1;
+    endcase
+  end
+
+  always @(*) begin
+    case (filter_enable)
+      1'b0: dac_int_data = dac_data;
+      default: dac_int_data = dac_cic_data[31:16];
     endcase
 
     case (filter_mask)
-      3'h1: dac_filt_int_valid = dac_fir_valid;
-      3'h2: dac_filt_int_valid = dac_fir_valid;
-      3'h3: dac_filt_int_valid = dac_fir_valid;
-      3'h6: dac_filt_int_valid = dac_fir_valid;
-      3'h7: dac_filt_int_valid = dac_fir_valid;
-      default: dac_filt_int_valid = dac_valid & !dma_transfer_suspend;
+      1'b0: dac_filt_int_valid = dac_valid & !dma_transfer_suspend;
+      default: dac_filt_int_valid = dac_fir_valid;
     endcase
 
     case (filter_mask)