From 50d018fc11d7466f307a8d2ae4e7d0ae90e00af3 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 18 May 2016 13:24:04 -0400 Subject: [PATCH] arradio- rfifo/wfifo added --- projects/arradio/c5soc/system_constr.sdc | 60 +++--- projects/arradio/common/arradio_bd.qsys | 259 ++++++++++++++++++----- 2 files changed, 241 insertions(+), 78 deletions(-) diff --git a/projects/arradio/c5soc/system_constr.sdc b/projects/arradio/c5soc/system_constr.sdc index d6dd5ca69..2848a0de7 100644 --- a/projects/arradio/c5soc/system_constr.sdc +++ b/projects/arradio/c5soc/system_constr.sdc @@ -3,41 +3,41 @@ create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}] create_clock -period "12.500 ns" -name dma_clk [get_pins {*sys_hps*h2f_user0_clk}] create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}] -create_clock -period 4.0 -name v_rx_clk derive_pll_clocks derive_clock_uncertainty -create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}] +#create_clock -period 4.0 -name v_rx_clk +#create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}] -set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_frame_in}] -set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[0]}] -set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[1]}] -set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[2]}] -set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[3]}] -set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[4]}] -set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[5]}] -set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_frame_in}] -clock_fall -add_delay -set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[0]}] -clock_fall -add_delay -set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[1]}] -clock_fall -add_delay -set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[2]}] -clock_fall -add_delay -set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[3]}] -clock_fall -add_delay -set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[4]}] -clock_fall -add_delay -set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[5]}] -clock_fall -add_delay +#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_frame_in}] +#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[0]}] +#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[1]}] +#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[2]}] +#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[3]}] +#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[4]}] +#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[5]}] +#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_frame_in}] -clock_fall -add_delay +#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[0]}] -clock_fall -add_delay +#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[1]}] -clock_fall -add_delay +#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[2]}] -clock_fall -add_delay +#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[3]}] -clock_fall -add_delay +#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[4]}] -clock_fall -add_delay +#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[5]}] -clock_fall -add_delay -set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_frame_out}] -set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[0]}] -set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[1]}] -set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[2]}] -set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[3]}] -set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[4]}] -set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[5]}] -set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay -set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay -set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay -set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay -set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay -set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay -set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay +#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_frame_out}] +#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[0]}] +#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[1]}] +#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[2]}] +#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[3]}] +#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[4]}] +#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[5]}] +#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay +#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay +#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay +#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay +#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay +#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay +#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay diff --git a/projects/arradio/common/arradio_bd.qsys b/projects/arradio/common/arradio_bd.qsys index 14f13bf65..dbd04f1ef 100755 --- a/projects/arradio/common/arradio_bd.qsys +++ b/projects/arradio/common/arradio_bd.qsys @@ -81,6 +81,14 @@ type = "String"; } } + element arradio_bd + { + datum _originalDeviceFamily + { + value = "Cyclone V"; + type = "String"; + } + } element axi_ad9361 { datum _sortIndex @@ -106,7 +114,7 @@ { datum _sortIndex { - value = "7"; + value = "9"; type = "int"; } datum sopceditor_expanded @@ -123,11 +131,11 @@ type = "String"; } } - element axi_dmac_dac + element axi_dac_dma { datum _sortIndex { - value = "9"; + value = "10"; type = "int"; } datum sopceditor_expanded @@ -136,7 +144,7 @@ type = "boolean"; } } - element axi_dmac_dac.s_axi + element axi_dac_dma.s_axi { datum baseAddress { @@ -144,24 +152,11 @@ type = "String"; } } - element dac_upack - { - datum _sortIndex - { - value = "8"; - type = "int"; - } - datum sopceditor_expanded - { - value = "1"; - type = "boolean"; - } - } element gpio { datum _sortIndex { - value = "11"; + value = "12"; type = "int"; } } @@ -185,7 +180,7 @@ { datum _sortIndex { - value = "10"; + value = "11"; type = "int"; } datum sopceditor_expanded @@ -222,7 +217,7 @@ { datum _sortIndex { - value = "6"; + value = "7"; type = "int"; } datum sopceditor_expanded @@ -239,6 +234,27 @@ type = "int"; } } + element util_dac_rfifo + { + datum _sortIndex + { + value = "6"; + type = "int"; + } + } + element util_dac_upack + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + datum sopceditor_expanded + { + value = "1"; + type = "boolean"; + } + } } ]]> @@ -307,21 +323,21 @@ dir="end" /> - + internal="axi_dac_dma.fifo_rd_clock" /> + - + @@ -391,10 +407,6 @@ - - - - @@ -454,21 +466,26 @@ - + + + + + + + + + + + - + end="util_dac_rfifo.if_dout_clk" /> + + + + end="axi_dac_dma.m_src_axi_clock" /> + end="axi_dac_dma.s_axi_clock" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + start="util_dac_upack.if_dac_data" + end="axi_dac_dma.if_fifo_rd_dout"> @@ -660,8 +780,8 @@ + start="util_adc_wfifo.if_din_ovf" + end="axi_ad9361.if_adc_dovf"> @@ -671,8 +791,8 @@ + start="util_dac_upack.if_dma_xfer_in" + end="axi_dac_dma.if_fifo_rd_xfer_req"> @@ -682,7 +802,7 @@ @@ -690,16 +810,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + end="axi_dac_dma.m_src_axi_reset" /> + end="axi_dac_dma.s_axi_reset" />