arradio- rfifo/wfifo added
Rejeesh Kutty
parent
bf0b90229a
commit
50d018fc11
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@ -3,41 +3,41 @@ create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}]
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create_clock -period "12.500 ns" -name dma_clk [get_pins {*sys_hps*h2f_user0_clk}]
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create_clock -period 4.0 -name rx_clk [get_ports {rx_clk_in}]
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create_clock -period 4.0 -name v_rx_clk
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derive_pll_clocks
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derive_clock_uncertainty
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create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}]
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#create_clock -period 4.0 -name v_rx_clk
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#create_generated_clock -source [get_clocks {*axi_ad9361*alt_clk*divclk}] -name v_fb_clk [get_ports {tx_clk_out}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_frame_in}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[0]}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[1]}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[2]}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[3]}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[4]}]
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set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[5]}]
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_frame_in}] -clock_fall -add_delay
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[0]}] -clock_fall -add_delay
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[1]}] -clock_fall -add_delay
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[2]}] -clock_fall -add_delay
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[3]}] -clock_fall -add_delay
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[4]}] -clock_fall -add_delay
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set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[5]}] -clock_fall -add_delay
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#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_frame_in}]
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#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[0]}]
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#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[1]}]
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#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[2]}]
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#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[3]}]
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#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[4]}]
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#set_input_delay -clock {v_rx_clk} -max 1.2 [get_ports {rx_data_in[5]}]
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#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_frame_in}] -clock_fall -add_delay
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#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[0]}] -clock_fall -add_delay
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#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[1]}] -clock_fall -add_delay
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#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[2]}] -clock_fall -add_delay
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#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[3]}] -clock_fall -add_delay
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#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[4]}] -clock_fall -add_delay
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#set_input_delay -clock {v_rx_clk} -min 0.2 [get_ports {rx_data_in[5]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_frame_out}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[0]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[1]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[2]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[3]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[4]}]
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set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[5]}]
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay
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set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay
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#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_frame_out}]
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#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[0]}]
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#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[1]}]
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#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[2]}]
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#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[3]}]
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#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[4]}]
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#set_output_delay -clock {v_fb_clk} -max 1.2 [get_ports {tx_data_out[5]}]
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#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_frame_out}] -clock_fall -add_delay
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#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[0]}] -clock_fall -add_delay
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#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[1]}] -clock_fall -add_delay
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#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[2]}] -clock_fall -add_delay
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#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[3]}] -clock_fall -add_delay
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#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[4]}] -clock_fall -add_delay
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#set_output_delay -clock {v_fb_clk} -min 0.2 [get_ports {tx_data_out[5]}] -clock_fall -add_delay
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@ -81,6 +81,14 @@
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type = "String";
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}
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}
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element arradio_bd
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{
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datum _originalDeviceFamily
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{
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value = "Cyclone V";
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type = "String";
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}
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}
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element axi_ad9361
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{
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datum _sortIndex
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@ -106,7 +114,7 @@
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{
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datum _sortIndex
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{
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value = "7";
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value = "9";
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type = "int";
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}
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datum sopceditor_expanded
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@ -123,11 +131,11 @@
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type = "String";
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}
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}
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element axi_dmac_dac
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element axi_dac_dma
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{
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datum _sortIndex
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{
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value = "9";
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value = "10";
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type = "int";
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}
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datum sopceditor_expanded
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@ -136,7 +144,7 @@
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type = "boolean";
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}
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}
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element axi_dmac_dac.s_axi
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element axi_dac_dma.s_axi
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{
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datum baseAddress
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{
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@ -144,24 +152,11 @@
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type = "String";
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}
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}
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element dac_upack
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{
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datum _sortIndex
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{
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value = "8";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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element gpio
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{
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datum _sortIndex
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{
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value = "11";
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value = "12";
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type = "int";
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}
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}
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@ -185,7 +180,7 @@
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{
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datum _sortIndex
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{
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value = "10";
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value = "11";
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type = "int";
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}
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datum sopceditor_expanded
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@ -222,7 +217,7 @@
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{
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datum _sortIndex
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{
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value = "6";
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value = "7";
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type = "int";
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}
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datum sopceditor_expanded
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@ -239,6 +234,27 @@
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type = "int";
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}
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}
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element util_dac_rfifo
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{
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datum _sortIndex
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{
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value = "6";
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type = "int";
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}
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}
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element util_dac_upack
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{
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datum _sortIndex
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{
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value = "8";
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type = "int";
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}
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datum sopceditor_expanded
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{
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value = "1";
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type = "boolean";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="FIFO" />
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@ -307,21 +323,21 @@
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dir="end" />
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<interface
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name="axi_dmac_dac_fifo_rd_clock"
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internal="axi_dmac_dac.fifo_rd_clock" />
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<interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dmac_dac.fifo_rd_if" />
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internal="axi_dac_dma.fifo_rd_clock" />
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<interface name="axi_dmac_dac_fifo_rd_if" internal="axi_dac_dma.fifo_rd_if" />
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<interface
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name="axi_dmac_dac_intr"
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internal="axi_dmac_dac.interrupt_sender"
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internal="axi_dac_dma.interrupt_sender"
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type="interrupt"
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dir="end" />
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<interface
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name="axi_dmac_dac_m_src_axi"
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internal="axi_dmac_dac.m_src_axi"
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internal="axi_dac_dma.m_src_axi"
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type="axi4"
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dir="start" />
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<interface
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name="axi_dmac_dac_s_axi"
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internal="axi_dmac_dac.s_axi"
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internal="axi_dac_dma.s_axi"
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type="axi4lite"
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dir="end" />
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<interface
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@ -374,7 +390,7 @@
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<parameter name="ID" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="1" />
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</module>
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<module name="axi_dmac_dac" kind="axi_dmac" version="1.0" enabled="1">
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<module name="axi_dac_dma" kind="axi_dmac" version="1.0" enabled="1">
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<parameter name="ASYNC_CLK_DEST_REQ" value="1" />
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<parameter name="ASYNC_CLK_REQ_SRC" value="1" />
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<parameter name="ASYNC_CLK_SRC_DEST" value="1" />
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@ -391,10 +407,6 @@
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<parameter name="ID" value="0" />
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<parameter name="SYNC_TRANSFER_START" value="0" />
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</module>
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<module name="dac_upack" kind="util_upack" version="1.0" enabled="1">
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<parameter name="CHANNEL_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="gpio" kind="altera_avalon_pio" version="15.1" enabled="1">
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<parameter name="bitClearingEdgeCapReg" value="false" />
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<parameter name="bitModifyingOutReg" value="false" />
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@ -454,21 +466,26 @@
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="util_adc_wfifo" kind="util_wfifo" version="1.0" enabled="1">
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<parameter name="DIN_ADDRESS_WIDTH" value="8" />
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<parameter name="DIN_ADDRESS_WIDTH" value="5" />
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<parameter name="DIN_DATA_WIDTH" value="16" />
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<parameter name="DOUT_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="util_dac_rfifo" kind="util_rfifo" version="1.0" enabled="1">
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<parameter name="DIN_ADDRESS_WIDTH" value="5" />
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<parameter name="DIN_DATA_WIDTH" value="16" />
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<parameter name="DOUT_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<module name="util_dac_upack" kind="util_upack" version="1.0" enabled="1">
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<parameter name="CHANNEL_DATA_WIDTH" value="16" />
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<parameter name="NUM_OF_CHANNELS" value="4" />
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</module>
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<connection
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="axi_ad9361.if_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="dac_upack.if_dac_clk" />
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<connection
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kind="clock"
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version="15.1"
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@ -478,7 +495,7 @@
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kind="clock"
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version="15.1"
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start="axi_ad9361.if_l_clk"
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end="axi_dmac_dac.if_fifo_rd_clk" />
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end="util_dac_rfifo.if_dout_clk" />
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<connection
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kind="clock"
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version="15.1"
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@ -490,11 +507,26 @@
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version="15.1"
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start="mem_clk.out_clk"
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end="util_adc_pack.if_adc_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="mem_clk.out_clk"
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end="util_dac_upack.if_dac_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="mem_clk.out_clk"
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end="util_dac_rfifo.if_din_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="mem_clk.out_clk"
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end="util_adc_wfifo.if_dout_clk" />
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<connection
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kind="clock"
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version="15.1"
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start="mem_clk.out_clk"
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end="axi_dac_dma.if_fifo_rd_clk" />
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<connection
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kind="clock"
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version="15.1"
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@ -509,7 +541,7 @@
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kind="clock"
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version="15.1"
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start="mem_clk.out_clk"
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end="axi_dmac_dac.m_src_axi_clock" />
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end="axi_dac_dma.m_src_axi_clock" />
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<connection
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kind="clock"
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version="15.1"
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@ -524,7 +556,7 @@
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kind="clock"
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version="15.1"
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start="sys_clk.out_clk"
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end="axi_dmac_dac.s_axi_clock" />
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end="axi_dac_dma.s_axi_clock" />
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<connection
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kind="conduit"
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version="15.1"
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@ -591,6 +623,72 @@
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="util_dac_upack.dac_ch_0"
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end="util_dac_rfifo.din_0">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="util_dac_upack.dac_ch_1"
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end="util_dac_rfifo.din_1">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="axi_ad9361.dac_ch_1"
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end="util_dac_rfifo.dout_1">
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<parameter name="endPort" value="" />
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<parameter name="endPortLSB" value="0" />
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<parameter name="startPort" value="" />
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<parameter name="startPortLSB" value="0" />
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<parameter name="width" value="0" />
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</connection>
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<connection
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kind="conduit"
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version="15.1"
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start="util_dac_upack.dac_ch_2"
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end="util_dac_rfifo.din_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_upack.dac_ch_3"
|
||||
end="util_dac_rfifo.din_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_ad9361.dac_ch_3"
|
||||
end="util_dac_rfifo.dout_3">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
|
|
@ -602,6 +700,28 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_rfifo.dout_0"
|
||||
end="axi_ad9361.dac_ch_0">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="util_dac_rfifo.dout_2"
|
||||
end="axi_ad9361.dac_ch_2">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
|
|
@ -649,8 +769,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="dac_upack.if_dac_data"
|
||||
end="axi_dmac_dac.if_fifo_rd_dout">
|
||||
start="util_dac_upack.if_dac_data"
|
||||
end="axi_dac_dma.if_fifo_rd_dout">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
|
@ -660,8 +780,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="dac_upack.if_dma_xfer_in"
|
||||
end="axi_dmac_dac.if_fifo_rd_xfer_req">
|
||||
start="util_adc_wfifo.if_din_ovf"
|
||||
end="axi_ad9361.if_adc_dovf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
|
@ -671,8 +791,8 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_dac.if_fifo_rd_en"
|
||||
end="dac_upack.if_dac_valid">
|
||||
start="util_dac_upack.if_dma_xfer_in"
|
||||
end="axi_dac_dma.if_fifo_rd_xfer_req">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
|
|
@ -682,7 +802,7 @@
|
|||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dmac_dac.if_fifo_rd_underflow"
|
||||
start="util_dac_rfifo.if_dout_unf"
|
||||
end="axi_ad9361.if_dac_dunf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
|
|
@ -690,16 +810,59 @@
|
|||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dac_dma.if_fifo_rd_en"
|
||||
end="util_dac_upack.if_dac_valid">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_dac_dma.if_fifo_rd_underflow"
|
||||
end="util_dac_rfifo.if_din_unf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="conduit"
|
||||
version="15.1"
|
||||
start="axi_adc_dma.if_fifo_wr_overflow"
|
||||
end="util_adc_wfifo.if_dout_ovf">
|
||||
<parameter name="endPort" value="" />
|
||||
<parameter name="endPortLSB" value="0" />
|
||||
<parameter name="startPort" value="" />
|
||||
<parameter name="startPortLSB" value="0" />
|
||||
<parameter name="width" value="0" />
|
||||
</connection>
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_rst"
|
||||
end="util_adc_wfifo.if_din_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="axi_ad9361.if_rst"
|
||||
end="util_dac_rfifo.if_dout_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="util_adc_pack.if_adc_rst" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="util_dac_rfifo.if_din_rstn" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
|
|
@ -714,7 +877,7 @@
|
|||
kind="reset"
|
||||
version="15.1"
|
||||
start="mem_rst.out_reset"
|
||||
end="axi_dmac_dac.m_src_axi_reset" />
|
||||
end="axi_dac_dma.m_src_axi_reset" />
|
||||
<connection
|
||||
kind="reset"
|
||||
version="15.1"
|
||||
|
|
@ -739,7 +902,7 @@
|
|||
kind="reset"
|
||||
version="15.1"
|
||||
start="sys_rst.out_reset"
|
||||
end="axi_dmac_dac.s_axi_reset" />
|
||||
end="axi_dac_dma.s_axi_reset" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
||||
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
||||
<interconnectRequirement
|
||||
|
|
|
|||
Loading…
Reference in New Issue