From 6711390c0125dfffe7546fe8bfc15e07281a3b3d Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:11:58 +0100 Subject: [PATCH 01/91] dmac: fifo_inf: Handle overflow and underflow correctly Refactor the fifo_inf modules to always correctly generate the underflow and overflow status signals. Before it was possible that in some cases they were not generated when they should have been. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/dest_fifo_inf.v | 25 ++++++++++--------------- library/axi_dmac/src_fifo_inf.v | 29 +++++------------------------ 2 files changed, 15 insertions(+), 39 deletions(-) diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v index 20ecf2c88..acd527978 100644 --- a/library/axi_dmac/dest_fifo_inf.v +++ b/library/axi_dmac/dest_fifo_inf.v @@ -53,8 +53,8 @@ module dmac_dest_fifo_inf ( input en, output [C_DATA_WIDTH-1:0] dout, - output reg valid, - output reg underflow, + output valid, + output underflow, output fifo_ready, input fifo_valid, @@ -80,28 +80,23 @@ wire data_enabled; wire _fifo_ready; assign fifo_ready = _fifo_ready | ~enabled; -reg data_ready; +reg en_d1; +wire data_ready; wire data_valid; always @(posedge clk) begin if (resetn == 1'b0) begin - data_ready <= 1'b1; - underflow <= 1'b0; - valid <= 1'b0; + en_d1 <= 1'b0; end else begin - if (enable == 1'b1) begin - valid <= data_valid & en; - data_ready <= en & data_valid; - underflow <= en & ~data_valid; - end else begin - valid <= 1'b0; - data_ready <= 1'b1; - underflow <= en; - end + en_d1 <= en; end end +assign underflow = en_d1 & (~data_valid | ~enable); +assign data_ready = en_d1 & (data_valid | ~enable); +assign valid = en_d1 & data_valid & enable; + dmac_data_mover # ( .C_ID_WIDTH(C_ID_WIDTH), .C_DATA_WIDTH(C_DATA_WIDTH), diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v index fedf7fb54..449e064a0 100644 --- a/library/axi_dmac/src_fifo_inf.v +++ b/library/axi_dmac/src_fifo_inf.v @@ -69,21 +69,18 @@ parameter C_ID_WIDTH = 3; parameter C_DATA_WIDTH = 64; parameter C_BEATS_PER_BURST_WIDTH = 4; -reg valid = 1'b0; wire ready; -reg [C_DATA_WIDTH-1:0] buffer = 'h00; -reg buffer_sync = 1'b0; reg needs_sync = 1'b0; -wire has_sync = ~needs_sync | buffer_sync; -wire sync_valid = valid & has_sync; +wire has_sync = ~needs_sync | sync; +wire sync_valid = en & ready & has_sync; always @(posedge clk) begin if (resetn == 1'b0) begin needs_sync <= 1'b0; end else begin - if (ready && valid && buffer_sync) begin + if (ready && en && sync) begin needs_sync <= 1'b0; end else if (req_valid && req_ready) begin needs_sync <= req_sync_transfer_start; @@ -91,30 +88,14 @@ begin end end -always @(posedge clk) -begin - if (en) begin - buffer <= din; - buffer_sync <= sync; - end -end - always @(posedge clk) begin if (resetn == 1'b0) begin - valid <= 1'b0; overflow <= 1'b0; end else begin if (enable) begin - if (en) begin - valid <= 1'b1; - end else if (ready || ~xfer_req) begin - valid <= 1'b0; - end - overflow <= en & valid & ~ready; + overflow <= en & ~ready; end else begin - if (ready || ~xfer_req) - valid <= 1'b0; overflow <= en; end end @@ -147,7 +128,7 @@ dmac_data_mover # ( .s_axi_ready(ready), .s_axi_valid(sync_valid), - .s_axi_data(buffer), + .s_axi_data(din), .m_axi_ready(fifo_ready), .m_axi_valid(fifo_valid), .m_axi_data(fifo_data), From 4a695692657e20ae22b87c86916e648e55d1a67e Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:29:39 +0100 Subject: [PATCH 02/91] axi_dmac: request_generator: Stop generating requests when disabled Currently when the DMAC gets disabled the request_generator will still generate all remaining burst requests for the currently active transfer. While these requests will be ignored by the source and destination component this can still take a fair amount of time for long transfers. So just stop generating burst requests once the DMAC is being disabled. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_generator.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v index 04ab50b8c..e02232891 100644 --- a/library/axi_dmac/request_generator.v +++ b/library/axi_dmac/request_generator.v @@ -78,6 +78,8 @@ begin burst_count <= 'h00; id <= 'h0; req_ready <= 1'b1; + end else if (enable == 1'b0) begin + req_ready <= 1'b1; end else begin if (req_ready) begin if (req_valid && enable) begin From 96b2a6d49a357e55890e0e8c280ea89bba8af2b5 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:31:08 +0100 Subject: [PATCH 03/91] axi_dmac: Use internal enable signal for the request generator All components should use the internal 'do_enable' signal instead of the external 'enable' signal. The former correctly incorporates the shutdown sequence and does not get asserted again until the shutdown has been completed. Using the external signal can cause problems when it is disabled and enabled again in close proximity. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_arb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 0f50ab588..f9b451bf7 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -1013,7 +1013,7 @@ dmac_request_generator #( .req_ready(req_gen_ready), .req_burst_count(req_length[C_DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), - .enable(enable), + .enable(do_enable), .pause(pause), .eot(request_eot) From ea84e93e1d86062d39f05d1042b56b3d9a480ee2 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:23:05 +0100 Subject: [PATCH 04/91] axi_dmac: Correctly handle shutdown for the request splitter We need to make sure to not prematurely de-assert the s_valid signal for the request splitter when disabling the DMAC. Otherwise it is possible that under certain conditions the DMAC is disabled with a partially accepted request and when it is enabled again it will continue in an inconsistent state which can lead to transfer corruption or pipeline stalls. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac.v | 2 +- library/axi_dmac/request_arb.v | 19 +++++++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index 226d3b56f..c32b441db 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -198,7 +198,7 @@ localparam DMA_TYPE_AXI_MM = 0; localparam DMA_TYPE_AXI_STREAM = 1; localparam DMA_TYPE_FIFO = 2; -localparam PCORE_VERSION = 'h00040061; +localparam PCORE_VERSION = 'h00040062; localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM; localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM; diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index f9b451bf7..0d3d146d4 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -883,15 +883,30 @@ axi_register_slice #( // We do not accept any requests until all components are enabled +reg _req_valid = 1'b0; wire _req_ready; -assign req_ready = _req_ready & enabled; + +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + _req_valid <= 1'b0; + end else begin + if (_req_valid == 1'b1 && _req_ready == 1'b1) begin + _req_valid <= 1'b0; + end else if (req_valid == 1'b1 && enabled == 1'b1) begin + _req_valid <= 1'b1; + end + end +end + +assign req_ready = _req_ready & _req_valid & enable; splitter #( .C_NUM_M(3) ) i_req_splitter ( .clk(req_aclk), .resetn(req_aresetn), - .s_valid(req_valid & enabled), + .s_valid(_req_valid), .s_ready(_req_ready), .m_valid({ req_gen_valid, From e15f0cd2c64c0cc4ad67b2421920946f2ea885f5 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:11:58 +0100 Subject: [PATCH 05/91] dmac: fifo_inf: Handle overflow and underflow correctly Refactor the fifo_inf modules to always correctly generate the underflow and overflow status signals. Before it was possible that in some cases they were not generated when they should have been. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/dest_fifo_inf.v | 25 ++++++++++--------------- library/axi_dmac/src_fifo_inf.v | 29 +++++------------------------ 2 files changed, 15 insertions(+), 39 deletions(-) diff --git a/library/axi_dmac/dest_fifo_inf.v b/library/axi_dmac/dest_fifo_inf.v index 20ecf2c88..acd527978 100644 --- a/library/axi_dmac/dest_fifo_inf.v +++ b/library/axi_dmac/dest_fifo_inf.v @@ -53,8 +53,8 @@ module dmac_dest_fifo_inf ( input en, output [C_DATA_WIDTH-1:0] dout, - output reg valid, - output reg underflow, + output valid, + output underflow, output fifo_ready, input fifo_valid, @@ -80,28 +80,23 @@ wire data_enabled; wire _fifo_ready; assign fifo_ready = _fifo_ready | ~enabled; -reg data_ready; +reg en_d1; +wire data_ready; wire data_valid; always @(posedge clk) begin if (resetn == 1'b0) begin - data_ready <= 1'b1; - underflow <= 1'b0; - valid <= 1'b0; + en_d1 <= 1'b0; end else begin - if (enable == 1'b1) begin - valid <= data_valid & en; - data_ready <= en & data_valid; - underflow <= en & ~data_valid; - end else begin - valid <= 1'b0; - data_ready <= 1'b1; - underflow <= en; - end + en_d1 <= en; end end +assign underflow = en_d1 & (~data_valid | ~enable); +assign data_ready = en_d1 & (data_valid | ~enable); +assign valid = en_d1 & data_valid & enable; + dmac_data_mover # ( .C_ID_WIDTH(C_ID_WIDTH), .C_DATA_WIDTH(C_DATA_WIDTH), diff --git a/library/axi_dmac/src_fifo_inf.v b/library/axi_dmac/src_fifo_inf.v index fedf7fb54..449e064a0 100644 --- a/library/axi_dmac/src_fifo_inf.v +++ b/library/axi_dmac/src_fifo_inf.v @@ -69,21 +69,18 @@ parameter C_ID_WIDTH = 3; parameter C_DATA_WIDTH = 64; parameter C_BEATS_PER_BURST_WIDTH = 4; -reg valid = 1'b0; wire ready; -reg [C_DATA_WIDTH-1:0] buffer = 'h00; -reg buffer_sync = 1'b0; reg needs_sync = 1'b0; -wire has_sync = ~needs_sync | buffer_sync; -wire sync_valid = valid & has_sync; +wire has_sync = ~needs_sync | sync; +wire sync_valid = en & ready & has_sync; always @(posedge clk) begin if (resetn == 1'b0) begin needs_sync <= 1'b0; end else begin - if (ready && valid && buffer_sync) begin + if (ready && en && sync) begin needs_sync <= 1'b0; end else if (req_valid && req_ready) begin needs_sync <= req_sync_transfer_start; @@ -91,30 +88,14 @@ begin end end -always @(posedge clk) -begin - if (en) begin - buffer <= din; - buffer_sync <= sync; - end -end - always @(posedge clk) begin if (resetn == 1'b0) begin - valid <= 1'b0; overflow <= 1'b0; end else begin if (enable) begin - if (en) begin - valid <= 1'b1; - end else if (ready || ~xfer_req) begin - valid <= 1'b0; - end - overflow <= en & valid & ~ready; + overflow <= en & ~ready; end else begin - if (ready || ~xfer_req) - valid <= 1'b0; overflow <= en; end end @@ -147,7 +128,7 @@ dmac_data_mover # ( .s_axi_ready(ready), .s_axi_valid(sync_valid), - .s_axi_data(buffer), + .s_axi_data(din), .m_axi_ready(fifo_ready), .m_axi_valid(fifo_valid), .m_axi_data(fifo_data), From 23eb0d2428584c150d0b058813950b566d9596d3 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:29:39 +0100 Subject: [PATCH 06/91] axi_dmac: request_generator: Stop generating requests when disabled Currently when the DMAC gets disabled the request_generator will still generate all remaining burst requests for the currently active transfer. While these requests will be ignored by the source and destination component this can still take a fair amount of time for long transfers. So just stop generating burst requests once the DMAC is being disabled. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_generator.v | 2 ++ 1 file changed, 2 insertions(+) diff --git a/library/axi_dmac/request_generator.v b/library/axi_dmac/request_generator.v index 04ab50b8c..e02232891 100644 --- a/library/axi_dmac/request_generator.v +++ b/library/axi_dmac/request_generator.v @@ -78,6 +78,8 @@ begin burst_count <= 'h00; id <= 'h0; req_ready <= 1'b1; + end else if (enable == 1'b0) begin + req_ready <= 1'b1; end else begin if (req_ready) begin if (req_valid && enable) begin From 81a17121b0b50306a6fc01525a56833eec3a0ea0 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:31:08 +0100 Subject: [PATCH 07/91] axi_dmac: Use internal enable signal for the request generator All components should use the internal 'do_enable' signal instead of the external 'enable' signal. The former correctly incorporates the shutdown sequence and does not get asserted again until the shutdown has been completed. Using the external signal can cause problems when it is disabled and enabled again in close proximity. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_arb.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 0f50ab588..f9b451bf7 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -1013,7 +1013,7 @@ dmac_request_generator #( .req_ready(req_gen_ready), .req_burst_count(req_length[C_DMA_LENGTH_WIDTH-1:BYTES_PER_BURST_WIDTH]), - .enable(enable), + .enable(do_enable), .pause(pause), .eot(request_eot) From 277161c14368d23d6aed66f93f1206c89c6b5480 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Thu, 19 Feb 2015 14:23:05 +0100 Subject: [PATCH 08/91] axi_dmac: Correctly handle shutdown for the request splitter We need to make sure to not prematurely de-assert the s_valid signal for the request splitter when disabling the DMAC. Otherwise it is possible that under certain conditions the DMAC is disabled with a partially accepted request and when it is enabled again it will continue in an inconsistent state which can lead to transfer corruption or pipeline stalls. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/axi_dmac.v | 2 +- library/axi_dmac/request_arb.v | 19 +++++++++++++++++-- 2 files changed, 18 insertions(+), 3 deletions(-) diff --git a/library/axi_dmac/axi_dmac.v b/library/axi_dmac/axi_dmac.v index 226d3b56f..c32b441db 100644 --- a/library/axi_dmac/axi_dmac.v +++ b/library/axi_dmac/axi_dmac.v @@ -198,7 +198,7 @@ localparam DMA_TYPE_AXI_MM = 0; localparam DMA_TYPE_AXI_STREAM = 1; localparam DMA_TYPE_FIFO = 2; -localparam PCORE_VERSION = 'h00040061; +localparam PCORE_VERSION = 'h00040062; localparam HAS_DEST_ADDR = C_DMA_TYPE_DEST == DMA_TYPE_AXI_MM; localparam HAS_SRC_ADDR = C_DMA_TYPE_SRC == DMA_TYPE_AXI_MM; diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index f9b451bf7..0d3d146d4 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -883,15 +883,30 @@ axi_register_slice #( // We do not accept any requests until all components are enabled +reg _req_valid = 1'b0; wire _req_ready; -assign req_ready = _req_ready & enabled; + +always @(posedge req_aclk) +begin + if (req_aresetn == 1'b0) begin + _req_valid <= 1'b0; + end else begin + if (_req_valid == 1'b1 && _req_ready == 1'b1) begin + _req_valid <= 1'b0; + end else if (req_valid == 1'b1 && enabled == 1'b1) begin + _req_valid <= 1'b1; + end + end +end + +assign req_ready = _req_ready & _req_valid & enable; splitter #( .C_NUM_M(3) ) i_req_splitter ( .clk(req_aclk), .resetn(req_aresetn), - .s_valid(req_valid & enabled), + .s_valid(_req_valid), .s_ready(_req_ready), .m_valid({ req_gen_valid, From a81bc7e46324259ff8b736a8efd8ce4a4ffde34a Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 20 Feb 2015 16:12:11 +0200 Subject: [PATCH 09/91] Motor control cores updated for motcon2 --- library/axi_mc_controller/axi_mc_controller.v | 42 +- .../axi_mc_controller_ip.tcl | 1 + library/axi_mc_controller/control_registers.v | 8 +- library/axi_mc_controller/delay.v | 80 ++++ library/axi_mc_controller/motor_driver.v | 82 +++- library/axi_mc_current_monitor/ad7401.v | 4 +- .../axi_mc_current_monitor.v | 443 ++---------------- .../axi_mc_current_monitor_ip.tcl | 0 library/axi_mc_speed/axi_mc_speed.v | 103 +--- library/axi_mc_speed/axi_mc_speed_ip.tcl | 0 library/axi_mc_speed/debouncer.v | 1 + library/axi_mc_speed/delay_30_degrees.v | 12 +- library/axi_mc_speed/speed_detector.v | 8 +- 13 files changed, 252 insertions(+), 532 deletions(-) mode change 100755 => 100644 library/axi_mc_controller/axi_mc_controller_ip.tcl create mode 100644 library/axi_mc_controller/delay.v mode change 100755 => 100644 library/axi_mc_current_monitor/axi_mc_current_monitor_ip.tcl mode change 100755 => 100644 library/axi_mc_speed/axi_mc_speed_ip.tcl diff --git a/library/axi_mc_controller/axi_mc_controller.v b/library/axi_mc_controller/axi_mc_controller.v index dd3e2adc1..0d5abb199 100644 --- a/library/axi_mc_controller/axi_mc_controller.v +++ b/library/axi_mc_controller/axi_mc_controller.v @@ -47,7 +47,6 @@ module axi_mc_controller // physical interface - input fmc_m1_fault_i, output fmc_m1_en_o, output pwm_ah_o, output pwm_al_o, @@ -55,7 +54,7 @@ module axi_mc_controller output pwm_bl_o, output pwm_ch_o, output pwm_cl_o, - output [7:0] gpo_o, + output [3:0] gpo_o, // controller connections @@ -77,11 +76,9 @@ module axi_mc_controller output[1:0] sensors_o, input [2:0] position_i, -// dma interface +// channel interface output adc_clk_o, - input adc_dovf_i, - input adc_dunf_i, output adc_enable_c0, output adc_enable_c1, output adc_enable_c2, @@ -137,13 +134,10 @@ module axi_mc_controller //------------------------------------------------------------------------------ // internal registers -reg adc_valid = 'd0; -reg [31:0] adc_data = 'd0; -reg [31:0] up_rdata = 'd0; -reg up_wack = 'd0; -reg up_rack = 'd0; -reg pwm_gen_clk = 'd0; -reg one_chan_reg = 'd0; +reg [31:0] up_rdata = 'd0; +reg up_wack = 'd0; +reg up_rack = 'd0; +reg pwm_gen_clk = 'd0; //------------------------------------------------------------------------------ //----------- Wires Declarations ----------------------------------------------- @@ -196,16 +190,12 @@ wire star_delta_s; wire dir_s; wire [10:0] pwm_open_s; wire [10:0] pwm_s; - -wire [10:0] gpo_s; - wire dpwm_ah_s; wire dpwm_al_s; wire dpwm_bh_s; wire dpwm_bl_s; wire dpwm_ch_s; wire dpwm_cl_s; - wire foc_ctrl_s; //------------------------------------------------------------------------------ @@ -237,7 +227,6 @@ assign adc_data_c5 = ctrl_data5_i; assign adc_data_c6 = ctrl_data6_i; assign adc_data_c7 = ctrl_data7_i; - assign ctrl_rst_o = !run_s; // monitor signals @@ -252,11 +241,6 @@ assign pwm_bl_o = foc_ctrl_s ? pwm_b_i : dpwm_bl_s; assign pwm_ch_o = foc_ctrl_s ? !pwm_c_i : dpwm_ch_s; assign pwm_cl_o = foc_ctrl_s ? pwm_c_i : dpwm_cl_s; -// assign gpo - -assign gpo_o[7:4] = gpo_s[10:7]; -assign gpo_o[3:0] = gpo_s[3:0]; - // clock generation always @(posedge ref_clk) @@ -264,7 +248,6 @@ begin pwm_gen_clk <= ~pwm_gen_clk; // generate 50 MHz clk end - // processor read interface always @(negedge up_rstn or posedge up_clk) begin @@ -284,7 +267,7 @@ end motor_driver #( .PWM_BITS(11)) motor_driver_inst( - .clk_i(ref_clk), + .clk_i(ctrl_data_clk), .pwm_clk_i(pwm_gen_clk), .rst_n_i(up_rstn) , .run_i(run_s), @@ -322,7 +305,7 @@ control_registers control_reg_inst( .kp1_o(), .ki1_o(), .kd1_o(), - .gpo_o(gpo_s), + .gpo_o(gpo_o), .reference_speed_o(), .oloop_matlab_o(foc_ctrl_s), .err_i(), @@ -707,9 +690,9 @@ up_adc_common i_up_adc_common( .adc_ddr_edgesel(), .adc_pin_mode(), .adc_status(1'b1), - .adc_sync_status(1'b0), - .adc_status_ovf(adc_dovf_i), - .adc_status_unf(adc_dunf_i), + .adc_sync_status(1'b1), + .adc_status_ovf(), + .adc_status_unf(), .adc_clk_ratio(32'd1), .adc_start_code(), .adc_sync(), @@ -735,7 +718,7 @@ up_adc_common i_up_adc_common( .drp_ready(1'b0), .drp_locked(1'b0), .up_usr_chanmax(), - .adc_usr_chanmax(8'd0), + .adc_usr_chanmax(8'd7), .up_adc_gpio_in(32'h0), .up_adc_gpio_out(), .up_rstn (up_rstn), @@ -784,4 +767,3 @@ endmodule // *************************************************************************** // *************************************************************************** - diff --git a/library/axi_mc_controller/axi_mc_controller_ip.tcl b/library/axi_mc_controller/axi_mc_controller_ip.tcl old mode 100755 new mode 100644 index d5421994b..8165b3b31 --- a/library/axi_mc_controller/axi_mc_controller_ip.tcl +++ b/library/axi_mc_controller/axi_mc_controller_ip.tcl @@ -17,6 +17,7 @@ adi_ip_files axi_mc_controller [list \ "$ad_hdl_dir/library/common/up_adc_common.v" \ "$ad_hdl_dir/library/common/up_adc_channel.v" \ "motor_driver.v" \ + "delay.v" \ "control_registers.v" \ "axi_mc_controller.v" ] diff --git a/library/axi_mc_controller/control_registers.v b/library/axi_mc_controller/control_registers.v index f8a831c53..45c74380f 100644 --- a/library/axi_mc_controller/control_registers.v +++ b/library/axi_mc_controller/control_registers.v @@ -66,8 +66,8 @@ module control_registers output break_o, output dir_o, output star_delta_o, - output [1:0] sensors_o, - output [10:0] gpo_o, + output [ 1:0] sensors_o, + output [ 3:0] gpo_o, output oloop_matlab_o, output calibrate_adcs_o ); @@ -96,8 +96,6 @@ reg [10:0] gpo_r; //----------- Wires Declarations ----------------------------------------------- //------------------------------------------------------------------------------ -//internal signals - wire up_wreq_s; wire up_rreq_s; @@ -115,7 +113,7 @@ assign star_delta_o = control_r[4]; // Select between star [0] o assign sensors_o = control_r[9:8]; // Select between Hall[00] and BEMF[01] sensors assign calibrate_adcs_o = control_r[16]; assign oloop_matlab_o = control_r[12]; // Select between open loop control [0] and matlab control [1] -assign gpo_o = control_r[30:20]; +assign gpo_o = control_r[23:20]; assign pwm_open_o = pwm_open_r[10:0]; // PWM value, for open loop control assign reference_speed_o = reference_speed_r; diff --git a/library/axi_mc_controller/delay.v b/library/axi_mc_controller/delay.v new file mode 100644 index 000000000..a4a401c38 --- /dev/null +++ b/library/axi_mc_controller/delay.v @@ -0,0 +1,80 @@ +// ----------------------------------------------------------------------------- +// +// Copyright 2014(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY +// AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +// INTELLECTUAL PROPERTY RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ----------------------------------------------------------------------------- +// FILE NAME : delay.v +// MODULE NAME : debouncer +// AUTHOR : ACozma +// AUTHOR’S EMAIL : andrei.cozma@analog.com +// +// ----------------------------------------------------------------------------- + +`timescale 1ns / 1ps + +module delay +//----------- Parameters Declarations ------------------------------------------- +#( + parameter DELAY = 128 +) +//----------- Ports Declarations ----------------------------------------------- +( + input clk_i, + input rst_n_i, + input sig_i, + output reg sig_o +); +//------------------------------------------------------------------------------ +//----------- Registers Declarations ------------------------------------------- +//------------------------------------------------------------------------------ +reg [DELAY-1:0] shift_reg; + +//------------------------------------------------------------------------------ +//----------- Assign/Always Blocks --------------------------------------------- +//------------------------------------------------------------------------------ +always @(posedge clk_i) +begin + if(rst_n_i == 0) + begin + shift_reg <= 0; + sig_o <= 0; + end + else + begin + shift_reg <= {shift_reg[DELAY-2:0], sig_i}; + sig_o <= shift_reg[DELAY-1]; + end +end + +endmodule diff --git a/library/axi_mc_controller/motor_driver.v b/library/axi_mc_controller/motor_driver.v index 3fa6b017f..1d557f446 100644 --- a/library/axi_mc_controller/motor_driver.v +++ b/library/axi_mc_controller/motor_driver.v @@ -90,6 +90,19 @@ wire align_complete; wire [PWMBW:0] pwm_duty_s; wire [1:0] commutation_table[0:2]; +wire pwm_al_s; +wire pwm_ah_s; +wire pwm_bl_s; +wire pwm_bh_s; +wire pwm_cl_s; +wire pwm_ch_s; +wire pwmd_al_s; +wire pwmd_ah_s; +wire pwmd_bl_s; +wire pwmd_bh_s; +wire pwmd_cl_s; +wire pwmd_ch_s; + //------------------------------------------------------------------------------ //----------- Local Parameters ------------------------------------------------- //------------------------------------------------------------------------------ @@ -97,9 +110,10 @@ wire [1:0] commutation_table[0:2]; localparam OFF = 3'b001; localparam ALIGN = 3'b010; localparam RUN = 3'b100; +localparam DT = 20; localparam [PWMBW:0] ALIGN_PWM_DUTY = 2**(PWMBW) + 2**(PWMBW-3); -localparam [15:0] ALIGN_TIME = 16'h4000; +localparam [15:0] ALIGN_TIME = 16'h8000; localparam [1:0] COMMUTATION_TABLE_DELTA_CW_0[0:5] = { 2'd1,-2'd1, 2'd1,-2'd1, 2'd1,-2'd1}; @@ -116,6 +130,51 @@ localparam [1:0] COMMUTATION_TABLE_STAR_CCW_0[0:5] = {-2'd1, 2'd1, 2'd0, 2'd0, localparam [1:0] COMMUTATION_TABLE_STAR_CCW_1[0:5] = { 2'd0,-2'd1,-2'd1, 2'd1, 2'd1, 2'd0}; localparam [1:0] COMMUTATION_TABLE_STAR_CCW_2[0:5] = { 2'd1, 2'd0, 2'd1,-2'd1, 2'd0,-2'd1}; +delay #( + .DELAY(DT)) + delay_ah_i ( + .clk_i (clk_i), + .rst_n_i (pwm_ah_s), + .sig_i (pwm_ah_s), + .sig_o (pwmd_ah_s)); +delay #( + .DELAY(DT)) + delay_al_i ( + .clk_i (clk_i), + .rst_n_i (pwm_al_s), + .sig_i (pwm_al_s), + .sig_o (pwmd_al_s)); + +delay #( + .DELAY(DT)) + delay_bh_i ( + .clk_i (clk_i), + .rst_n_i (pwm_bh_s), + .sig_i (pwm_bh_s), + .sig_o (pwmd_bh_s)); +delay #( + .DELAY(DT)) + delay_bl_i ( + .clk_i (clk_i), + .rst_n_i (pwm_bl_s), + .sig_i (pwm_bl_s), + .sig_o (pwmd_bl_s)); + +delay #( + .DELAY(DT)) + delay_ch_i ( + .clk_i (clk_i), + .rst_n_i (pwm_ch_s), + .sig_i (pwm_ch_s), + .sig_o (pwmd_ch_s)); +delay #( + .DELAY(DT)) + delay_cl_i ( + .clk_i (clk_i), + .rst_n_i (pwm_cl_s), + .sig_i (pwm_cl_s), + .sig_o (pwmd_cl_s)); + //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ @@ -136,14 +195,23 @@ assign commutation_table[2] = star_delta_i ? //Motor Phases Control -assign AH_o = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 1; -assign AL_o = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 1; +assign pwm_ah_s = commutation_table[0] == 2'd1 ? ~pwm_s : commutation_table[0] == -2'd1 ? pwm_s : 0; +assign pwm_al_s = commutation_table[0] == 2'd1 ? pwm_s : commutation_table[0] == -2'd1 ? ~pwm_s : 0; -assign BH_o = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 1; -assign BL_o = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 1; +assign pwm_bh_s = commutation_table[1] == 2'd1 ? ~pwm_s : commutation_table[1] == -2'd1 ? pwm_s : 0; +assign pwm_bl_s = commutation_table[1] == 2'd1 ? pwm_s : commutation_table[1] == -2'd1 ? ~pwm_s : 0; -assign CH_o = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 1; -assign CL_o = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 1; +assign pwm_ch_s = commutation_table[2] == 2'd1 ? ~pwm_s : commutation_table[2] == -2'd1 ? pwm_s : 0; +assign pwm_cl_s = commutation_table[2] == 2'd1 ? pwm_s : commutation_table[2] == -2'd1 ? ~pwm_s : 0; + +assign AL_o = pwmd_ah_s? 0 : pwmd_al_s; +assign AH_o = pwmd_ah_s; + +assign BL_o = pwmd_bh_s ? 0 : pwmd_bl_s; +assign BH_o = pwmd_bh_s; + +assign CL_o = pwmd_ch_s ? 0 : pwmd_cl_s; +assign CH_o = pwmd_ch_s; //Control the current motor state always @(posedge clk_i) diff --git a/library/axi_mc_current_monitor/ad7401.v b/library/axi_mc_current_monitor/ad7401.v index 496c4ee3f..b54dc8930 100644 --- a/library/axi_mc_current_monitor/ad7401.v +++ b/library/axi_mc_current_monitor/ad7401.v @@ -77,8 +77,7 @@ module ad7401 output reg adc_status_o, //AD7401 control and data interface - input adc_mdata_i, // AD7401 MDAT pin - output adc_mclkin_o // AD7401 MCLKIN pin + input adc_mdata_i // AD7401 MDAT pin ); //------------------------------------------------------------------------------ @@ -113,7 +112,6 @@ localparam WAIT_DATA_RDY_LOW_STATE = 5'b10000; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ -assign adc_mclkin_o = adc_clk_i; // use clock signal for driver and for ADC // synchronize data on fpga_clki always @(posedge fpga_clk_i) diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor.v b/library/axi_mc_current_monitor/axi_mc_current_monitor.v index 873d50613..e27c0c78c 100644 --- a/library/axi_mc_current_monitor/axi_mc_current_monitor.v +++ b/library/axi_mc_current_monitor/axi_mc_current_monitor.v @@ -37,8 +37,7 @@ `timescale 1ns/100ps -module axi_mc_current_monitor -#( +module axi_mc_current_monitor #( parameter C_S_AXI_MIN_SIZE = 32'hffff ) ( @@ -46,30 +45,22 @@ module axi_mc_current_monitor // physical interface input adc_ia_dat_i, - output adc_ia_clk_o, + output adc_enable_ia, input adc_ib_dat_i, - output adc_ib_clk_o, - input adc_it_dat_i, - output adc_it_clk_o, + output adc_enable_ib, input adc_vbus_dat_i, - output adc_vbus_clk_o, + output adc_enable_vbus, + output adc_enable_stub, + output adc_clk_o, input ref_clk, + input adc_clk_i, - output [17:0] ia_o, - output [17:0] ib_o, - output [17:0] it_o, + output [15:0] ia_o, + output [15:0] ib_o, + output [15:0] vbus_o, output i_ready_o, - // dma interface - - output adc_clk_o, - output adc_dwr_o, - output [63:0] adc_ddata_o, - output adc_dsync_o, - input adc_dovf_i, - input adc_dunf_i, - // axi interface input s_axi_aclk, @@ -90,40 +81,16 @@ module axi_mc_current_monitor output s_axi_rvalid, output [1:0] s_axi_rresp, output [31:0] s_axi_rdata, - input s_axi_rready, - - // debug signals - - output adc_mon_valid, - output [31:0] adc_mon_data + input s_axi_rready ); //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ -reg adc_valid = 'd0; -reg [63:0] adc_data = 'd0; -reg [47:0] adc_data_3 = 'd0; reg [31:0] up_rdata = 'd0; -reg up_wack = 'd0; -reg up_rack = 'd0; -reg [1:0] adc_data_cnt = 'd0; -reg [9:0] adc_clk_cnt = 'd0; // used to generate 10 MHz clock for ADCs -reg adc_clk_reg = 'd0; // used to generate 10 MHz clock for ADCs - -reg acq_run_reg = 'd0; // register used for synchronizing data acquisition -reg adc_valid_3 = 'd0; -reg [47:0] adc_data_3_1110 = 'd0; -reg [47:0] adc_data_3_1101 = 'd0; -reg [47:0] adc_data_3_1011 = 'd0; -reg [47:0] adc_data_3_0111 = 'd0; -reg [63:0] adc_data_1110 = 'd0; -reg [63:0] adc_data_1101 = 'd0; -reg [63:0] adc_data_1011 = 'd0; -reg [63:0] adc_data_0111 = 'd0; -reg adc_dsync_r_3 = 'd0; -reg adc_dsync_r = 'd0; +reg up_wack = 'd0; +reg up_rack = 'd0; //------------------------------------------------------------------------------ //----------- Wires Declarations ----------------------------------------------- @@ -148,27 +115,22 @@ wire [31:0] up_rdata_0_s; wire [31:0] up_rdata_1_s; wire [31:0] up_rdata_2_s; wire [31:0] up_rdata_3_s; -wire up_ack_0_s; -wire up_ack_1_s; -wire up_ack_2_s; -wire up_ack_3_s; +wire up_rack_0_s; +wire up_rack_1_s; +wire up_rack_2_s; +wire up_rack_3_s; +wire up_wack_0_s; +wire up_wack_1_s; +wire up_wack_2_s; +wire up_wack_3_s; wire adc_status_a_s; wire [15:0] adc_data_ia_s ; wire data_rd_ready_ia_s; wire adc_status_b_s; wire [15:0] adc_data_ib_s; -wire adc_status_it_s; -wire [15:0] adc_data_it_s; -wire [15:0] adc_data_it_n_s; wire adc_status_vbus_s; -wire [15:0] adc_data_vbus_s ; -wire adc_enable_ia; -wire adc_enable_ib; -wire adc_enable_it; -wire adc_enable_vbus; - -wire adc_clk_s; +wire [15:0] adc_data_vbus_s; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- @@ -179,304 +141,17 @@ wire adc_clk_s; assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; -assign adc_clk_o = ref_clk; // use reference clock to send data to the dma -assign adc_dwr_o = adc_valid; -assign adc_ddata_o = adc_data; -assign adc_dsync_o = adc_dsync_r; - -// monitor signals - -assign adc_mon_valid = data_rd_ready_ia_s; -assign adc_mon_data[15: 0] = adc_data[15:0]; -assign adc_mon_data[31:16] = {adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia, adc_rst, data_rd_ready_ia_s, adc_data_cnt, adc_ia_clk_o, adc_data_ia_s[6:0]}; - // current outputs -assign i_ready_o = data_rd_ready_ia_s; -assign ia_o = {adc_data_ia_s - 16'h7FFF, 2'b00}; -assign ib_o = {adc_data_ib_s - 16'h7FFF, 2'b00}; -assign it_o = {adc_data_it_s, 2'b00}; -assign adc_data_it_n_s = 65535 - adc_data_it_s; +assign i_ready_o = data_rd_ready_ia_s; + +assign ia_o = adc_data_ia_s ; +assign ib_o = adc_data_ib_s ; +assign vbus_o = adc_data_vbus_s; // adc clock -assign adc_clk_s = adc_clk_reg; - -// ADC clock generation - -always @(posedge ref_clk) -begin - if(adc_clk_cnt < 10'd4) - begin - adc_clk_cnt <= adc_clk_cnt + 1; - end - else - begin - adc_clk_cnt <= 10'd0; - adc_clk_reg <= ~adc_clk_reg; - end -end - -// adc channels - dma interface - -always @(posedge ref_clk) -begin - if(data_rd_ready_ia_s == 1'b1) - begin - adc_valid_3 <= adc_data_cnt[0] | adc_data_cnt[1]; - adc_dsync_r_3 <= adc_data_cnt[0] | ~adc_data_cnt[1]; - adc_data_3_1110[47:32] <= adc_data_vbus_s; - adc_data_3_1110[31:16] <= adc_data_it_n_s; - adc_data_3_1110[15:0] <= adc_data_ib_s; - adc_data_3_1101[47:32] <= adc_data_vbus_s; - adc_data_3_1101[31:16] <= adc_data_it_n_s; - adc_data_3_1101[15:0] <= adc_data_ia_s; - adc_data_3_1011[47:32] <= adc_data_vbus_s; - adc_data_3_1011[31:16] <= adc_data_ib_s; - adc_data_3_1011[15:0] <= adc_data_ia_s; - adc_data_3_0111[47:32] <= adc_data_it_n_s; - adc_data_3_0111[31:16] <= adc_data_ib_s; - adc_data_3_0111[15:0] <= adc_data_ia_s; - case(adc_data_cnt) - 2'b11: - begin - adc_data_1110[63:48] <= adc_data_vbus_s; - adc_data_1110[47:32] <= adc_data_it_n_s; - adc_data_1110[31:16] <= adc_data_ib_s; - adc_data_1110[15:0] <= adc_data_3_1110[47:32]; - adc_data_1101[63:48] <= adc_data_vbus_s; - adc_data_1101[47:32] <= adc_data_it_n_s; - adc_data_1101[31:16] <= adc_data_ia_s; - adc_data_1101[15:0] <= adc_data_3_1101[47:32]; - adc_data_1011[63:48] <= adc_data_vbus_s; - adc_data_1011[47:32] <= adc_data_ib_s; - adc_data_1011[31:16] <= adc_data_ia_s; - adc_data_1011[15:0] <= adc_data_3_1011[47:32]; - adc_data_0111[63:48] <= adc_data_it_n_s; - adc_data_0111[47:32] <= adc_data_ib_s; - adc_data_0111[31:16] <= adc_data_ia_s; - adc_data_0111[15:0] <= adc_data_3_0111[47:32]; - end - 2'b10: - begin - adc_data_1110[63:48] <= adc_data_it_n_s; - adc_data_1110[47:32] <= adc_data_ib_s; - adc_data_1110[31:16] <= adc_data_3_1110[47:32]; - adc_data_1110[15:0] <= adc_data_3_1110[31:16]; - adc_data_1101[63:48] <= adc_data_it_n_s; - adc_data_1101[47:32] <= adc_data_ia_s; - adc_data_1101[31:16] <= adc_data_3_1101[47:32]; - adc_data_1101[15:0] <= adc_data_3_1101[31:16]; - adc_data_1011[63:48] <= adc_data_ib_s; - adc_data_1011[47:32] <= adc_data_ia_s; - adc_data_1011[31:16] <= adc_data_3_1011[47:32]; - adc_data_1011[15:0] <= adc_data_3_1011[31:16]; - adc_data_0111[63:48] <= adc_data_ib_s; - adc_data_0111[47:32] <= adc_data_ia_s; - adc_data_0111[31:16] <= adc_data_3_0111[47:32]; - adc_data_0111[15:0] <= adc_data_3_0111[31:16]; - end - 2'b01: - begin - adc_data_1110[63:48] <= adc_data_ib_s; - adc_data_1110[47:32] <= adc_data_3_1110[47:32]; - adc_data_1110[31:16] <= adc_data_3_1110[31:16]; - adc_data_1110[15:0] <= adc_data_3_1110[15:0]; - adc_data_1101[63:48] <= adc_data_ia_s; - adc_data_1101[47:32] <= adc_data_3_1101[47:32]; - adc_data_1101[31:16] <= adc_data_3_1101[31:16]; - adc_data_1101[15:0] <= adc_data_3_1101[15:0]; - adc_data_1011[63:48] <= adc_data_ia_s; - adc_data_1011[47:32] <= adc_data_3_1011[47:32]; - adc_data_1011[31:16] <= adc_data_3_1011[31:16]; - adc_data_1011[15:0] <= adc_data_3_1011[15:0]; - adc_data_0111[63:48] <= adc_data_ia_s; - adc_data_0111[47:32] <= adc_data_3_0111[47:32]; - adc_data_0111[31:16] <= adc_data_3_0111[31:16]; - adc_data_0111[15:0] <= adc_data_3_0111[15:0]; - end - 2'b00: - begin - adc_data_1110[63:48] <= 16'hdead; - adc_data_1110[47:32] <= 16'hdead; - adc_data_1110[31:16] <= 16'hdead; - adc_data_1110[15:0] <= 16'hdead; - adc_data_1101[63:48] <= 16'hdead; - adc_data_1101[47:32] <= 16'hdead; - adc_data_1101[31:16] <= 16'hdead; - adc_data_1101[15:0] <= 16'hdead; - adc_data_1011[63:48] <= 16'hdead; - adc_data_1011[47:32] <= 16'hdead; - adc_data_1011[31:16] <= 16'hdead; - adc_data_1011[15:0] <= 16'hdead; - adc_data_0111[63:48] <= 16'hdead; - adc_data_0111[47:32] <= 16'hdead; - adc_data_0111[31:16] <= 16'hdead; - adc_data_0111[15:0] <= 16'hdead; - end - endcase - end -end - -always @(posedge ref_clk) -begin - if(data_rd_ready_ia_s == 1'b1) - begin - case({adc_enable_vbus, adc_enable_it, adc_enable_ib, adc_enable_ia}) - 4'b1111: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= 1'b1; - adc_data[63:48] <= adc_data_vbus_s; - adc_data[47:32] <= adc_data_it_n_s; - adc_data[31:16] <= adc_data_ib_s; - adc_data[15: 0] <= adc_data_ia_s; - end - 4'b1110: - begin - adc_dsync_r <= adc_dsync_r_3; - adc_valid <= adc_valid_3; - adc_data <= adc_data_1110; - end - 4'b1101: - begin - adc_dsync_r <= adc_dsync_r_3; - adc_valid <= adc_valid_3; - adc_data <= adc_data_1101; - end - 4'b1100: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[0]; - adc_data[63:48] <= adc_data_vbus_s; - adc_data[47:32] <= adc_data_it_n_s; - adc_data[31:16] <= adc_data[63:48]; - adc_data[15: 0] <= adc_data[47:32]; - end - 4'b1011: - begin - adc_dsync_r <= adc_dsync_r_3; - adc_valid <= adc_valid_3; - adc_data <= adc_data_1011; - end - 4'b1010: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[0]; - adc_data[63:48] <= adc_data_vbus_s; - adc_data[47:32] <= adc_data_ib_s; - adc_data[31:16] <= adc_data[63:48]; - adc_data[15: 0] <= adc_data[47:32]; - end - 4'b1001: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[0]; - adc_data[63:48] <= adc_data_vbus_s; - adc_data[47:32] <= adc_data_ia_s; - adc_data[31:16] <= adc_data[63:48]; - adc_data[15: 0] <= adc_data[47:32]; - end - 4'b1000: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[1] & adc_data_cnt[0]; - adc_data[63:48] <= adc_data_vbus_s; - adc_data[47:32] <= adc_data[63:48]; - adc_data[31:16] <= adc_data[47:32]; - adc_data[15: 0] <= adc_data[31:16]; - end - 4'b0111: - begin - adc_dsync_r <= adc_dsync_r_3; - adc_valid <= adc_valid_3; - adc_data <= adc_data_0111; - end - 4'b0110: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[0]; - adc_data[63:48] <= adc_data_it_n_s; - adc_data[47:32] <= adc_data_ib_s; - adc_data[31:16] <= adc_data[63:48]; - adc_data[15: 0] <= adc_data[47:32]; - end - 4'b0101: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[0]; - adc_data[63:48] <= adc_data_it_n_s; - adc_data[47:32] <= adc_data_ia_s; - adc_data[31:16] <= adc_data[63:48]; - adc_data[15: 0] <= adc_data[47:32]; - end - 4'b0100: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[1] & adc_data_cnt[0]; - adc_data[63:48] <= adc_data_it_n_s; - adc_data[47:32] <= adc_data[63:48]; - adc_data[31:16] <= adc_data[47:32]; - adc_data[15: 0] <= adc_data[31:16]; - end - 4'b0011: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[0]; - adc_data[63:48] <= adc_data_ib_s; - adc_data[47:32] <= adc_data_ia_s; - adc_data[31:16] <= adc_data[63:48]; - adc_data[15: 0] <= adc_data[47:32]; - end - 4'b0010: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[1] & adc_data_cnt[0]; - adc_data[63:48] <= adc_data_ib_s; - adc_data[47:32] <= adc_data[63:48]; - adc_data[31:16] <= adc_data[47:32]; - adc_data[15: 0] <= adc_data[31:16]; - end - 4'b0001: - begin - adc_dsync_r <= 1'b1; - adc_data_3 <= 48'd0; - adc_valid <= adc_data_cnt[1] & adc_data_cnt[0]; - adc_data[63:48] <= adc_data_ia_s; - adc_data[47:32] <= adc_data[63:48]; - adc_data[31:16] <= adc_data[47:32]; - adc_data[15: 0] <= adc_data[31:16]; - end - default: - begin - adc_dsync_r <= 1'b0; - adc_data_3 <= 48'd0; - adc_valid <= 1'b1; - adc_data[63:48] <= 16'hdead; - adc_data[47:32] <= 16'hdead; - adc_data[31:16] <= 16'hdead; - adc_data[15: 0] <= 16'hdead; - end - endcase - adc_data_cnt <= adc_data_cnt + 2'b1; - end - else - begin - adc_valid <= 1'b0; - adc_data <= adc_data; - adc_data_cnt <= adc_data_cnt; - end -end +assign adc_clk_o = adc_clk_i; // processor read interface @@ -485,14 +160,14 @@ begin if(up_rstn == 0) begin up_rdata <= 'd0; - up_rack <= 'd0; - up_wack <= 'd0; + up_rack <= 'd0; + up_wack <= 'd0; end else begin - up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s | up_rdata_3_s ; - up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ; - up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s ; + up_rdata <= up_adc_common_rdata_s | up_rdata_0_s | up_rdata_1_s | up_rdata_2_s |up_rdata_3_s ; + up_rack <= up_adc_common_rack_s | up_rack_0_s | up_rack_1_s | up_rack_2_s | up_rack_3_s ; + up_wack <= up_adc_common_wack_s | up_wack_0_s | up_wack_1_s | up_wack_2_s | up_wack_3_s; end end @@ -500,46 +175,33 @@ end ad7401 ia_if( .fpga_clk_i(ref_clk), - .adc_clk_i(adc_clk_s), + .adc_clk_i(adc_clk_o), .reset_i(adc_rst), .adc_status_o(adc_status_a_s), .data_o(adc_data_ia_s), .data_rd_ready_o(data_rd_ready_ia_s), - .adc_mdata_i(adc_ia_dat_i), - .adc_mclkin_o(adc_ia_clk_o)); + .adc_mdata_i(adc_ia_dat_i)); ad7401 ib_if( .fpga_clk_i(ref_clk), - .adc_clk_i(adc_clk_s), + .adc_clk_i(adc_clk_o), .reset_i(adc_rst), .adc_status_o(adc_status_b_s), .data_o(adc_data_ib_s), .data_rd_ready_o(), - .adc_mdata_i(adc_ib_dat_i), - .adc_mclkin_o(adc_ib_clk_o)); - -ad7401 it_if( - .fpga_clk_i(ref_clk), - .adc_clk_i(adc_clk_s), - .reset_i(adc_rst), - .adc_status_o(adc_status_it_s), - .data_o(adc_data_it_s), - .data_rd_ready_o(), - .adc_mdata_i(adc_it_dat_i), - .adc_mclkin_o(adc_it_clk_o)); + .adc_mdata_i(adc_ib_dat_i)); ad7401 vbus_if( .fpga_clk_i(ref_clk), - .adc_clk_i(adc_clk_s), + .adc_clk_i(adc_clk_o), .reset_i(adc_rst), .adc_status_o(adc_status_vbus_s), .data_o(adc_data_vbus_s), .data_rd_ready_o(), - .adc_mdata_i(adc_vbus_dat_i), - .adc_mclkin_o(adc_vbus_clk_o)); + .adc_mdata_i(adc_vbus_dat_i)); up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia( - .adc_clk(adc_clk_s), + .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_ia), .adc_iqcor_enb(), @@ -585,7 +247,7 @@ up_adc_channel #(.PCORE_ADC_CHID(0)) i_up_adc_channel_ia( .up_rack (up_rack_0_s)); up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib( - .adc_clk(adc_clk_s), + .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_enable(adc_enable_ib), .adc_iqcor_enb(), @@ -628,10 +290,10 @@ up_adc_channel #(.PCORE_ADC_CHID(1)) i_up_adc_channel_ib( .up_rdata (up_rdata_1_s), .up_rack (up_rack_1_s)); -up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it( - .adc_clk(adc_clk_s), +up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_vbus( + .adc_clk(adc_clk_o), .adc_rst(adc_rst), - .adc_enable(adc_enable_it), + .adc_enable(adc_enable_vbus), .adc_iqcor_enb(), .adc_dcfilt_enb(), .adc_dfmt_se(), @@ -672,10 +334,10 @@ up_adc_channel #(.PCORE_ADC_CHID(2)) i_up_adc_channel_it( .up_rdata (up_rdata_2_s), .up_rack (up_rack_2_s)); -up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus( - .adc_clk(adc_clk_s), +up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_stub( + .adc_clk(adc_clk_o), .adc_rst(adc_rst), - .adc_enable(adc_enable_vbus), + .adc_enable(adc_enable_stub), .adc_iqcor_enb(), .adc_dcfilt_enb(), .adc_dfmt_se(), @@ -720,15 +382,15 @@ up_adc_channel #(.PCORE_ADC_CHID(3)) i_up_adc_channel_vbus( up_adc_common i_up_adc_common( .mmcm_rst(), - .adc_clk(adc_clk_s), + .adc_clk(adc_clk_o), .adc_rst(adc_rst), .adc_r1_mode(), .adc_ddr_edgesel(), .adc_pin_mode(), .adc_status(1'b1), - .adc_sync_status(1'b0), - .adc_status_ovf(adc_dovf_i), - .adc_status_unf(adc_dunf_i), + .adc_sync_status(1'b1), + .adc_status_ovf(), + .adc_status_unf(), .adc_clk_ratio(32'd1), .adc_start_code(), .adc_sync(), @@ -758,7 +420,7 @@ up_adc_common i_up_adc_common( .drp_locked(1'b0), .up_usr_chanmax(), - .adc_usr_chanmax(8'd0), + .adc_usr_chanmax(8'd3), .up_adc_gpio_in(32'h0), .up_adc_gpio_out(), @@ -808,4 +470,3 @@ endmodule // *************************************************************************** // *************************************************************************** - diff --git a/library/axi_mc_current_monitor/axi_mc_current_monitor_ip.tcl b/library/axi_mc_current_monitor/axi_mc_current_monitor_ip.tcl old mode 100755 new mode 100644 diff --git a/library/axi_mc_speed/axi_mc_speed.v b/library/axi_mc_speed/axi_mc_speed.v index 1515a7287..c26591fbd 100644 --- a/library/axi_mc_speed/axi_mc_speed.v +++ b/library/axi_mc_speed/axi_mc_speed.v @@ -39,14 +39,12 @@ module axi_mc_speed #( - parameter C_S_AXI_MIN_SIZE = 32'hffff, - parameter MOTOR_CONTROL_REVISION = 2 + parameter C_S_AXI_MIN_SIZE = 32'hffff ) //----------- Ports Declarations ----------------------------------------------- ( // physical interface input [2:0] position_i, - input [2:0] bemf_i, output [2:0] position_o, output [31:0] speed_o, output new_speed_o, @@ -54,16 +52,7 @@ module axi_mc_speed input ref_clk, - // dma interface - - output adc_clk_o, - output adc_dwr_o, - output [31:0] adc_ddata_o, - input adc_dovf_i, - input adc_dunf_i, - // axi interface - input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, @@ -82,19 +71,11 @@ module axi_mc_speed output s_axi_rvalid, output [ 1:0] s_axi_rresp, output [31:0] s_axi_rdata, - input s_axi_rready, - -// debug signals - - output adc_mon_valid, - output [31:0] adc_mon_data); + input s_axi_rready); //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ - -reg adc_valid = 'd0; -reg [31:0] adc_data = 'd0; reg [31:0] up_rdata = 'd0; reg up_wack = 'd0; reg up_rack = 'd0; @@ -103,14 +84,11 @@ reg up_rack = 'd0; //----------- Wires Declarations ----------------------------------------------- //------------------------------------------------------------------------------ // internal clocks & resets - wire adc_rst; wire up_rstn; wire up_clk; // internal signals - -wire adc_start_s; wire [31:0] speed_data_s; wire adc_enable_s; wire adc_status_s; @@ -123,45 +101,25 @@ wire [31:0] up_adc_common_rdata_s; wire up_adc_common_wack_s; wire up_adc_common_rack_s; wire [31:0] pid_s; - -wire [ 2:0] position_s; -wire [ 2:0] bemf_s; -wire [ 2:0] bemf_delayed_s; -wire new_speed_s; -wire [ 2:0] bemf_multiplex_s; +wire [ 2:0] position_s; +wire [ 2:0] bemf_s; +wire [ 2:0] bemf_delayed_s; +wire new_speed_s; +wire [ 2:0] bemf_multiplex_s; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ // signal name changes - assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; -assign adc_clk_o = ref_clk; -assign adc_dwr_o = adc_valid; -assign adc_ddata_o = adc_data; - -// monitor signals - -assign adc_mon_valid = new_speed_s; -assign adc_mon_data = { 20'h0, bemf_multiplex_s, bemf_s, bemf_delayed_s, position_s }; - -assign bemf_multiplex_s =(MOTOR_CONTROL_REVISION == 2) ? position_i : bemf_i; +assign bemf_s = position_s ; assign position_o =(hall_bemf_i == 2'b01) ? bemf_delayed_s : position_s; assign new_speed_o = new_speed_s; assign speed_o = speed_data_s; -// adc channels - dma interface - -always @(posedge ref_clk) -begin - adc_data <= speed_data_s; - adc_valid <= new_speed_s; -end - // processor read interface - always @(negedge up_rstn or posedge up_clk) begin if(up_rstn == 0) @@ -178,7 +136,6 @@ begin end // HALL sensors debouncers - debouncer #( .DEBOUNCER_LEN(400)) position_0( @@ -203,31 +160,6 @@ position_2( .sig_i(position_i[2]), .sig_o(position_s[2])); -// BEMF debouncer -debouncer -#( .DEBOUNCER_LEN(400)) -bemf_0( - .clk_i(ref_clk), - .rst_i(adc_rst), - .sig_i(bemf_multiplex_s[0]), - .sig_o(bemf_s[0])); - -debouncer -#( .DEBOUNCER_LEN(400)) -bemf_1( - .clk_i(ref_clk), - .rst_i(adc_rst), - .sig_i(bemf_multiplex_s[1]), - .sig_o(bemf_s[1])); - -debouncer -#( .DEBOUNCER_LEN(400)) -bemf_2( - .clk_i(ref_clk), - .rst_i(adc_rst), - .sig_i(bemf_multiplex_s[2]), - .sig_o(bemf_s[2])); - delay_30_degrees delay_30_degrees_i1( .clk_i(ref_clk), .rst_i(adc_rst), @@ -247,8 +179,7 @@ speed_detector_inst( .current_speed_o(), .speed_o(speed_data_s)); - // common processor control - +// common processor control up_adc_common i_up_adc_common( .mmcm_rst(), .adc_clk(ref_clk), @@ -257,9 +188,15 @@ up_adc_common i_up_adc_common( .adc_ddr_edgesel(), .adc_pin_mode(), .adc_status(1'b1), - .adc_status_ovf(adc_dovf_i), - .adc_status_unf(adc_dunf_i), + .adc_sync_status(1'b1), + .adc_status_ovf(), + .adc_status_unf(), .adc_clk_ratio(32'd1), + .adc_start_code(), + .adc_sync(), + .up_status_pn_err(1'b0), + .up_status_pn_oos(1'b0), + .up_status_or(1'b0), .delay_clk(1'b0), .delay_rst(), .delay_sel(), @@ -279,8 +216,8 @@ up_adc_common i_up_adc_common( .drp_ready(1'b0), .drp_locked(1'b0), .up_usr_chanmax(), - .adc_usr_chanmax(8'd0), - .up_adc_gpio_in(), + .adc_usr_chanmax(8'd2), + .up_adc_gpio_in(32'h0), .up_adc_gpio_out(), .up_rstn(up_rstn), .up_clk(up_clk), @@ -294,7 +231,6 @@ up_adc_common i_up_adc_common( .up_rack (up_adc_common_rack_s)); // up bus interface - up_axi i_up_axi( .up_rstn(up_rstn), .up_clk(up_clk), @@ -325,6 +261,5 @@ up_axi i_up_axi( .up_rack (up_rack)); endmodule - // *************************************************************************** // *************************************************************************** diff --git a/library/axi_mc_speed/axi_mc_speed_ip.tcl b/library/axi_mc_speed/axi_mc_speed_ip.tcl old mode 100755 new mode 100644 diff --git a/library/axi_mc_speed/debouncer.v b/library/axi_mc_speed/debouncer.v index d48869e26..33def31bc 100644 --- a/library/axi_mc_speed/debouncer.v +++ b/library/axi_mc_speed/debouncer.v @@ -77,6 +77,7 @@ reg [DEBOUNCER_LEN-1:0] shift_reg; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ + always @(posedge clk_i) begin if(rst_i == 1) diff --git a/library/axi_mc_speed/delay_30_degrees.v b/library/axi_mc_speed/delay_30_degrees.v index ef6363848..407a66628 100644 --- a/library/axi_mc_speed/delay_30_degrees.v +++ b/library/axi_mc_speed/delay_30_degrees.v @@ -83,12 +83,12 @@ localparam IDLE = 6'b100000; //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ -reg [5:0] state; // current state -reg [5:0] next_state; // next state -reg [2:0] position_old; // saves the latest position -reg [31:0] speed_count; // counts the current speed of rotation -reg [31:0] speed_divider; // divides the speed of rotation by 2, correspoding to 30 degrees -reg [31:0] delay_count; // Applied the delay to the input signal +reg [5:0] state = RESET; // current state +reg [5:0] next_state = RESET; // next state +reg [2:0] position_old = 3'h0; // saves the latest position +reg [31:0] speed_count = 32'h0; // counts the current speed of rotation +reg [31:0] speed_divider = 32'h0; // divides the speed of rotation by 2, correspoding to 30 degrees +reg [31:0] delay_count = 32'h0; // Applied the delay to the input signal //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- diff --git a/library/axi_mc_speed/speed_detector.v b/library/axi_mc_speed/speed_detector.v index ac09d238c..43962928d 100644 --- a/library/axi_mc_speed/speed_detector.v +++ b/library/axi_mc_speed/speed_detector.v @@ -77,9 +77,7 @@ module speed_detector //------------------------------------------------------------------------------ //----------- Local Parameters ------------------------------------------------- //------------------------------------------------------------------------------ - localparam AW = LOG_2_AW - 1; - localparam MAX_SPEED_CNT = 32'h10000; //State machine @@ -94,14 +92,13 @@ localparam IDLE = 8'b10000000; //------------------------------------------------------------------------------ //----------- Registers Declarations ------------------------------------------- //------------------------------------------------------------------------------ - reg [ 2:0] position_old; reg [63:0] avg_register; reg [63:0] avg_register_stable; reg [31:0] cnt_period; -reg [31:0] decimation; // register used to divide by ten the speed +reg [31:0] decimation; // register used to divide by ten the speed reg [31:0] cnt_period_old; -reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM +reg [31:0] fifo [0:((2**LOG_2_AW)-1)]; // 32 bit wide RAM reg [AW:0] write_addr; reg [AW:0] read_addr; @@ -113,7 +110,6 @@ reg [ 7:0] next_state; //------------------------------------------------------------------------------ //----------- Assign/Always Blocks --------------------------------------------- //------------------------------------------------------------------------------ - // Count ticks per position always @(posedge clk_i) begin From cf456caa0e0b2dceb88c94dd701bd249d818bcec Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 20 Feb 2015 16:13:54 +0200 Subject: [PATCH 10/91] util_gmii_to_rgmii: Gmii to RGMII converter for the motcon2 project --- library/util_gmii_to_rgmii/mdc_mdio.v | 112 ++++++ .../util_gmii_to_rgmii/util_gmii_to_rgmii.v | 329 ++++++++++++++++++ .../util_gmii_to_rgmii_ip.tcl | 17 + 3 files changed, 458 insertions(+) create mode 100644 library/util_gmii_to_rgmii/mdc_mdio.v create mode 100644 library/util_gmii_to_rgmii/util_gmii_to_rgmii.v create mode 100644 library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl diff --git a/library/util_gmii_to_rgmii/mdc_mdio.v b/library/util_gmii_to_rgmii/mdc_mdio.v new file mode 100644 index 000000000..fa7bab93d --- /dev/null +++ b/library/util_gmii_to_rgmii/mdc_mdio.v @@ -0,0 +1,112 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +module mdc_mdio ( + + mdio_mdc, + mdio_in_w, + mdio_in_r, + + speed_select, + duplex_mode); + + parameter PHY_AD = 5'b10000; + + input mdio_mdc; + input mdio_in_w; + input mdio_in_r; + output [ 1:0] speed_select; + output duplex_mode; + + localparam IDLE = 2'b01; + localparam ACQUIRE = 2'b10; + + wire preamble; + + reg [ 1:0] current_state = IDLE; + reg [ 1:0] next_state = IDLE; + reg [31:0] data_in = 32'h0; + reg [31:0] data_in_r = 32'h0; + reg [ 5:0] data_counter = 6'h0; + reg [ 1:0] speed_select = 2'h0; + reg duplex_mode = 1'h0; + + assign preamble = &data_in; + + always @(posedge mdio_mdc) begin + current_state <= next_state; + data_in <= {data_in[30:0], mdio_in_w}; + if (current_state == ACQUIRE) begin + data_counter <= data_counter + 1; + end else begin + data_counter <= 0; + end + if (data_counter == 6'h1f) begin + if (data_in[31] == 1'b0 && data_in[29:28]==2'b10 && data_in[27:23] == PHY_AD && data_in[22:18] == 5'h11) begin + speed_select <= data_in_r[16:15] ; + duplex_mode <= data_in_r[14]; + end + end + end + + always @(negedge mdio_mdc) begin + data_in_r <= {data_in_r[30:0], mdio_in_r}; + end + + always @(*) begin + case (current_state) + IDLE: begin + if (preamble == 1 && mdio_in_w == 0) begin + next_state <= ACQUIRE; + end else begin + next_state <= IDLE; + end + end + ACQUIRE: begin + if (data_counter == 6'h1f) begin + next_state <= IDLE; + end else begin + next_state <= ACQUIRE; + end + end + default: begin + next_state <= IDLE; + end + endcase + end + +endmodule diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v new file mode 100644 index 000000000..5c165cc67 --- /dev/null +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -0,0 +1,329 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// based on XILINX xapp692 +// specific for MOTCON2 ADI board +// works correctly if the PHY is set with Autonegotiation on + +module util_gmii_to_rgmii ( + + clk_20m, + clk_25m, + clk_125m, + + reset, + + rgmii_td, + rgmii_tx_ctl, + rgmii_txc, + rgmii_rd, + rgmii_rx_ctl, + rgmii_rxc, + + mdio_mdc, + mdio_in_w, + mdio_in_r, + + gmii_txd, + gmii_tx_en, + gmii_tx_er, + gmii_tx_clk, + gmii_crs, + gmii_col, + gmii_rxd, + gmii_rx_dv, + gmii_rx_er, + gmii_rx_clk); + + parameter PHY_AD = 5'b10000; + + input clk_20m; + input clk_25m; + input clk_125m; + + input reset; + + output [ 3:0] rgmii_td; + output rgmii_tx_ctl; + output rgmii_txc; + input [ 3:0] rgmii_rd; + input rgmii_rx_ctl; + input rgmii_rxc; + + input mdio_mdc; + input mdio_in_w; + input mdio_in_r; + + input [ 7:0] gmii_txd; + input gmii_tx_en; + input gmii_tx_er; + output gmii_tx_clk; + output gmii_crs; + output gmii_col; + output [ 7:0] gmii_rxd; + output gmii_rx_dv; + output gmii_rx_er; + output gmii_rx_clk; + + // wires + wire clk_2_5m; + wire clk_100msps; + wire [ 3:0] rgmii_rd_delay; + wire [ 7:0] gmii_rxd_s; + wire [ 3:0] gmii_txd_low; + wire rgmii_rx_ctl_delay; + wire gmii_rx_er_s; + wire rgmii_rxc_s; + wire rgmii_rx_ctl_clk_s; + wire rgmii_rx_ctl_s; + wire rgmii_rxc_bufmr; + + wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps + wire duplex_mode; // 1 full, 0 half + + // registers + reg tx_reset_d1; + reg tx_reset_sync; + reg rx_reset_d1; + reg rx_reset_sync; + reg [ 7:0] gmii_txd_r; + reg gmii_tx_en_r; + reg gmii_tx_er_r; + + // assignments + assign gigabit = speed_selection [1]; + + assign gmii_tx_clk = gmii_tx_clk_s; + assign rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; + assign gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; + assign gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r) & ( gmii_rx_dv_s | gmii_rx_er_s) ; + assign gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r | gmii_rx_dv_s | gmii_rx_er_s); + + assign gmii_rxd = gmii_rxd_s; + assign gmii_rx_dv = gmii_rx_dv_s; + assign gmii_rx_er = gmii_rx_er_s; + assign gmii_rx_er_s = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + + always @(posedge gmii_tx_clk_s) begin + tx_reset_d1 <= reset; + tx_reset_sync <= tx_reset_d1; + end + + always @(posedge gmii_tx_clk_s) begin + if (tx_reset_sync == 1'b1) begin + gmii_txd_r <= 8'h0; + gmii_tx_en_r <= 1'b0; + gmii_tx_er_r <= 1'b0; + end + else + begin + gmii_txd_r <= gmii_txd; + gmii_tx_en_r <= gmii_tx_en; + gmii_tx_er_r <= gmii_tx_er; + end + end + + BUFR #( + .BUFR_DIVIDE("8"), + .SIM_DEVICE("7SERIES") + ) clk_2_5_divide ( + .I(clk_20m), + .CE(1), + .CLR(0), + .O(clk_2_5m)); + + BUFGMUX #( + .CLK_SEL_TYPE ("SYNC") + ) clk_tx_mux0 ( + .S(speed_selection[0]), + .I0(clk_2_5m), + .I1(clk_25m), + .O(clk_100msps)); + + BUFGMUX #( + .CLK_SEL_TYPE ("SYNC") + ) clk_tx_mux1 ( + .S(speed_selection[1]), + .I0(clk_100msps), + .I1(clk_125m), + .O(gmii_tx_clk_s)); + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_txc_out ( + .Q (rgmii_txc), + .C (gmii_tx_clk_s), + .CE(1), + .D1(1), + .D2(0), + .R(tx_reset_sync), + .S(0)); + + generate + genvar i; + for (i = 0; i < 4; i = i + 1) begin : gen_tx_data + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_td_out ( + .Q (rgmii_td[i]), + .C (gmii_tx_clk_s), + .CE(1), + .D1(gmii_txd_r[i]), + .D2(gmii_txd_low[i]), + .R(tx_reset_sync), + .S(0)); + end + endgenerate + + ODDR #( + .DDR_CLK_EDGE("SAME_EDGE") + ) rgmii_tx_ctl_out ( + .Q (rgmii_tx_ctl), + .C (gmii_tx_clk_s), + .CE(1), + .D1(gmii_tx_en_r), + .D2(rgmii_tx_ctl_r), + .R(tx_reset_sync), + .S(0)); + + + always @(posedge rgmii_rxc_s) begin + rx_reset_d1 <= reset; + rx_reset_sync <= rx_reset_d1; + end + + BUFMR bufmr_rgmii_rxc( + .I(rgmii_rxc), + .O(rgmii_rxc_bufmr)); + + BUFR #( + .SIM_DEVICE("7SERIES"), + .BUFR_DIVIDE(1) + ) bufr_rgmii_rx_clk ( + .I(rgmii_rxc_bufmr), + .CE(1), + .CLR(0), + .O(rgmii_rxc_s)); + + BUFR #( + .SIM_DEVICE("7SERIES"), + .BUFR_DIVIDE(1) + ) bufr_rgmii_rx_ctl_clk ( + .I(rgmii_rxc_bufmr), + .CE(1), + .CLR(0), + .O(rgmii_rx_ctl_clk_s)); + + BUFG bufg_rgmii_rx_clk ( + .I(rgmii_rxc_s), + .O(gmii_rx_clk)); + + IDELAYE2 #( + .IDELAY_TYPE("FIXED"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA"), + .DELAY_SRC("IDATAIN") + ) delay_rgmii_rx_ctl ( + .IDATAIN(rgmii_rx_ctl), + .DATAOUT(rgmii_rx_ctl_delay), + .DATAIN(0), + .C(0), + .CE(0), + .INC(0), + .CINVCTRL(0), + .CNTVALUEOUT(), + .LD(0), + .LDPIPEEN(0), + .CNTVALUEIN(0), + .REGRST(0)); + + generate + for (i = 0; i < 4; i = i + 1) begin + IDELAYE2 #( + .IDELAY_TYPE("FIXED"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA"), + .DELAY_SRC("IDATAIN") + ) delay_rgmii_rd ( + .IDATAIN(rgmii_rd[i]), + .DATAOUT(rgmii_rd_delay[i]), + .DATAIN(0), + .C(0), + .CE(0), + .INC(0), + .CINVCTRL(0), + .CNTVALUEOUT(), + .LD(0), + .LDPIPEEN(0), + .CNTVALUEIN(0), + .REGRST(0)); + + IDDR #( + .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + ) rgmii_rx_iddr ( + .Q1(gmii_rxd_s[i]), + .Q2(gmii_rxd_s[i+4]), + .C(rgmii_rxc_s), + .CE(1), + .D(rgmii_rd_delay[i]), + .R(0), + .S(0)); + end + endgenerate + + IDDR #( + .DDR_CLK_EDGE("SAME_EDGE_PIPELINED") + ) rgmii_rx_ctl_iddr ( + .Q1(gmii_rx_dv_s), + .Q2(rgmii_rx_ctl_s), + .C(rgmii_rx_ctl_clk_s), + .CE(1), + .D(rgmii_rx_ctl_delay), + .R(0), + .S(0)); + + mdc_mdio #( + .PHY_AD(PHY_AD) + ) mdc_mdio_in( + .mdio_mdc(mdio_mdc), + .mdio_in_w(mdio_in_w), + .mdio_in_r(mdio_in_r), + .speed_select(speed_selection), + .duplex_mode(duplex_mode)); + +endmodule diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl new file mode 100644 index 000000000..c8355a911 --- /dev/null +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii_ip.tcl @@ -0,0 +1,17 @@ +# ip + +source ../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip.tcl + +adi_ip_create util_gmii_to_rgmii +adi_ip_files util_gmii_to_rgmii [list \ + "mdc_mdio.v" \ + "util_gmii_to_rgmii.v" ] + +adi_ip_properties_lite util_gmii_to_rgmii + +ipx::infer_bus_interface {gmii_tx_clk gmii_txd gmii_tx_en gmii_tx_er gmii_crs gmii_col gmii_rx_clk gmii_rxd gmii_rx_dv gmii_rx_er} xilinx.com:interface:gmii_rtl:1.0 [ipx::current_core] +set_property name {gmii} [ipx::get_bus_interface gmii_rtl_1 [ipx::current_core]] +ipx::infer_bus_interface {rgmii_td rgmii_tx_ctl rgmii_txc rgmii_rd rgmii_rx_ctl rgmii_rxc} xilinx.com:interface:rgmii_rtl:1.0 [ipx::current_core] + +ipx::save_core [ipx::current_core] From 1b19a1b78acecd4539cb692bf7928ffcc7774be6 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 20 Feb 2015 16:15:01 +0200 Subject: [PATCH 11/91] Motcon2 initial commit --- .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 704 ++++++++++++++++++ projects/motcon2_fmc/zed/system_bd.tcl | 4 + projects/motcon2_fmc/zed/system_constr.xdc | 198 +++++ projects/motcon2_fmc/zed/system_top.v | 497 +++++++++++++ 4 files changed, 1403 insertions(+) create mode 100644 projects/motcon2_fmc/common/motcon2_fmc_bd.tcl create mode 100644 projects/motcon2_fmc/zed/system_bd.tcl create mode 100644 projects/motcon2_fmc/zed/system_constr.xdc create mode 100644 projects/motcon2_fmc/zed/system_top.v diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl new file mode 100644 index 000000000..f871dba8f --- /dev/null +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -0,0 +1,704 @@ + + # motor control + + + # port definition + + + # gpio + set_property LEFT 34 [get_bd_ports GPIO_I] + set_property LEFT 34 [get_bd_ports GPIO_O] + set_property LEFT 34 [get_bd_ports GPIO_T] + + # position detection interface + set position_m1_i [ create_bd_port -dir I -from 2 -to 0 position_m1_i ] + set position_m2_i [ create_bd_port -dir I -from 2 -to 0 position_m2_i ] + + # current monitor interface + # clock + set adc_clk_o [ create_bd_port -dir O adc_clk_o ] + # data motor 1 + set adc_m1_ia_dat_i [ create_bd_port -dir I adc_m1_ia_dat_i ] + set adc_m1_ib_dat_i [ create_bd_port -dir I adc_m1_ib_dat_i ] + set adc_m1_vbus_dat_i [ create_bd_port -dir I adc_m1_vbus_dat_i ] + # data motor 2 + set adc_m2_ia_dat_i [ create_bd_port -dir I adc_m2_ia_dat_i ] + set adc_m2_ib_dat_i [ create_bd_port -dir I adc_m2_ib_dat_i ] + set adc_m2_vbus_dat_i [ create_bd_port -dir I adc_m2_vbus_dat_i ] + + # motor control interface + set gpo_o [ create_bd_port -dir o -from 3 -to 0 gpo_o] + # motor 1 + set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o] + set pwm_m1_al_o [ create_bd_port -dir O pwm_m1_al_o] + set pwm_m1_ah_o [ create_bd_port -dir O pwm_m1_ah_o] + set pwm_m1_cl_o [ create_bd_port -dir O pwm_m1_cl_o] + set pwm_m1_ch_o [ create_bd_port -dir O pwm_m1_ch_o] + set pwm_m1_bl_o [ create_bd_port -dir O pwm_m1_bl_o] + set pwm_m1_bh_o [ create_bd_port -dir O pwm_m1_bh_o] + # motor 2 + set fmc_m2_en_o [ create_bd_port -dir O fmc_m2_en_o] + set pwm_m2_al_o [ create_bd_port -dir O pwm_m2_al_o] + set pwm_m2_ah_o [ create_bd_port -dir O pwm_m2_ah_o] + set pwm_m2_cl_o [ create_bd_port -dir O pwm_m2_cl_o] + set pwm_m2_ch_o [ create_bd_port -dir O pwm_m2_ch_o] + set pwm_m2_bl_o [ create_bd_port -dir O pwm_m2_bl_o] + set pwm_m2_bh_o [ create_bd_port -dir O pwm_m2_bh_o] + + # interrupts + set motcon2_c_m1_intr [create_bd_port -dir O motcon2_c_m1_intr] + set motcon2_c_m2_intr [create_bd_port -dir O motcon2_c_m2_intr] + set motcon2_s_d1_intr [create_bd_port -dir O motcon2_s_d1_intr] + set motcon2_s_d2_intr [create_bd_port -dir O motcon2_s_d2_intr] + set motcon2_ctrl_m1_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m1_intr ] + set motcon2_ctrl_m2_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m2_intr ] + + # Ethernet + # phy 1 + set eth1_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii ] + # phy 2 + set eth2_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth2_rgmii ] + #common mdio interface + set eth_mdio_mdc [ create_bd_port -dir O eth_mdio_mdc ] + set eth_mdio_o [ create_bd_port -dir O eth_mdio_o ] + set eth_mdio_t [ create_bd_port -dir O eth_mdio_t ] + set eth_mdio_i [ create_bd_port -dir I eth_mdio_i ] + #common reset + set eth_phy_rst_n [ create_bd_port -dir O eth_phy_rst_n ] + # reference clock for the delay interface used for the gmii to rgmii conversion + set refclk [ create_bd_port -dir o -type clk refclk ] + set refclk_rst [ create_bd_port -dir o -from 0 -to 0 -type rst refclk_rst ] + + # iic + create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ee2 + set iic_ee2_intr [create_bd_port -dir O iic_ee2_intr] + + # spi + set spi_csn_i [create_bd_port -dir I spi_csn_i] + set spi_csn_o [create_bd_port -dir O spi_csn_o] + set spi_sclk_i [create_bd_port -dir I spi_sclk_i] + set spi_sclk_o [create_bd_port -dir O spi_sclk_o] + set spi_mosi_i [create_bd_port -dir I spi_mosi_i] + set spi_mosi_o [create_bd_port -dir O spi_mosi_o] + set spi_miso_i [create_bd_port -dir I spi_miso_i] + + # xadc interface + #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 + #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 + #create_bd_port -dir O -from 4 -to 0 muxaddr_out + + + # core instantiation and configuration + + + # additions to default configuration + # increase cpu interconnect to accomodate new cores + set_property -dict [list CONFIG.NUM_MI {21}] $axi_cpu_interconnect + # Enable additional peripherals from the PS7 block + set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_ENET0_ENET0_IO {EMIO} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {1} ] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_ps7 + set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {35}] $sys_ps7 + + # Add additional clocks to be used by gmii to rgmii modules and current monitoring modules + set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen + + # speed detectors + # speed detector core motor 1 + set speed_detector_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m1 ] + # dma motor 1 + set speed_detector_m1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m1_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m1_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m1_dma + # speed detector core motor 2 + set speed_detector_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 speed_detector_m2 ] + # dma motor 2 + set speed_detector_m2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 speed_detector_m2_dma] + set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $speed_detector_m2_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $speed_detector_m2_dma + + # current monitor peripherals + # current monitor core motor 1 + set current_monitor_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m1 ] + # dma motor 1 + set current_monitor_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m1_dma ] + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m1_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m1_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m1_dma + # data packer motor 1 + # + set current_monitor_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m1_apack] + set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m1_apack +# set current_monitor_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m1_pack ] +# set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m1_pack +# set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m1_pack + + # current monitor core motor 2 + set current_monitor_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 current_monitor_m2 ] + # dma motor 2 + set current_monitor_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 current_monitor_m2_dma ] + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $current_monitor_m2_dma + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {0}] $current_monitor_m2_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $current_monitor_m2_dma + # data packer motor 2 + set current_monitor_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 current_monitor_m2_apack] + set_property -dict [list CONFIG.CHANNELS {4}] $current_monitor_m2_apack + #set current_monitor_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 current_monitor_m2_pack ] + #set_property -dict [ list CONFIG.CH_CNT {4} ] $current_monitor_m2_pack + #set_property -dict [ list CONFIG.CH_DW {16} ] $current_monitor_m2_pack + + #controller + # controller core motor 1 + set controller_m1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m1 ] + # dma motor 1 + set controller_m1_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m1_dma ] + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m1_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m1_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m1_dma + # data packer motor 1 + set controller_m1_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m1_apack] + set_property -dict [list CONFIG.CHANNELS {8}] $controller_m1_apack + set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m1_apack + + #set controller_m1_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m1_pack ] + #set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m1_pack + #set_property -dict [ list CONFIG.CH_DW {32} ] $controller_m1_pack + # controller core motor 2 + set controller_m2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 controller_m2 ] + # dma motor 2 + set controller_m2_dma [ create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 controller_m2_dma ] + set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $controller_m2_dma + set_property -dict [list CONFIG.C_CYCLIC {0}] $controller_m2_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $controller_m2_dma + # data packer motor 2 + #set controller_m2_pack [ create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 controller_m2_pack ] + #set_property -dict [ list CONFIG.CH_CNT {8} ] $controller_m2_pack + set controller_m2_apack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 controller_m2_apack] + set_property -dict [list CONFIG.CHANNELS {8}] $controller_m2_apack + set_property -dict [list CONFIG.DATA_WIDTH {32}] $controller_m2_apack + + #ethernet gmii to rgmii converters + # phy 1 + set gmii_to_rgmii_eth1 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth1 ] + set_property -dict [list CONFIG.PHY_AD {"00000"}] [get_bd_cells gmii_to_rgmii_eth1] + # phy 2 + set gmii_to_rgmii_eth2 [ create_bd_cell -type ip -vlnv analog.com:user:util_gmii_to_rgmii:1.0 gmii_to_rgmii_eth2 ] + set_property -dict [list CONFIG.PHY_AD {"00001"}] [get_bd_cells gmii_to_rgmii_eth2] + + # iic + set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] + + # xadc + #set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ] + #set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core + #set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core + #set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core + #set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core + #set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core + #set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core + #set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core + + # additional interconnect + set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ] + set_property -dict [ list CONFIG.NUM_SI {6} CONFIG.NUM_MI {1} ] $axi_mem_interconnect + + + # connections + + + # speed detector + # motor 1 + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1/ref_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m1_dma/fifo_wr_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m1_dma/m_dest_axi_aresetn] + + connect_bd_net -net position_m1_i_1 [get_bd_ports position_m1_i] [get_bd_pins speed_detector_m1/position_i] + connect_bd_net -net speed_detector_adc_new_speed_m1 [get_bd_pins speed_detector_m1/new_speed_o] [get_bd_pins speed_detector_m1_dma/fifo_wr_en] + connect_bd_net -net speed_detector_adc_speed_m1 [get_bd_pins speed_detector_m1/speed_o] [get_bd_pins speed_detector_m1_dma/fifo_wr_din] + # motor 2 + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2/ref_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins speed_detector_m2_dma/fifo_wr_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins speed_detector_m2_dma/m_dest_axi_aresetn] + + connect_bd_net -net position_m2_i_1 [get_bd_ports position_m2_i] [get_bd_pins speed_detector_m2/position_i] + connect_bd_net -net speed_detector_adc_new_speed_m2 [get_bd_pins speed_detector_m2/new_speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_en] + connect_bd_net -net speed_detector_adc_speed_m2 [get_bd_pins speed_detector_m2/speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_din] + + # interrupt + connect_bd_net -net speed_detector_m1_dma_intr [get_bd_pins speed_detector_m1_dma/irq] [get_bd_ports motcon2_s_d1_intr] + connect_bd_net -net speed_detector_m2_dma_intr [get_bd_pins speed_detector_m2_dma/irq] [get_bd_ports motcon2_s_d2_intr] + + # current monitor + connect_bd_net -net current_monitor_m1_adc_clk_o [get_bd_ports adc_clk_o] [get_bd_pins current_monitor_m1/adc_clk_o] + # motor 1 + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1/ref_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m1_dma/fifo_wr_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/m_dest_axi_aresetn] + + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins current_monitor_m1/adc_ia_dat_i] + connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins current_monitor_m1/adc_ib_dat_i] + connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins current_monitor_m1/adc_vbus_dat_i] + + connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m1_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0] + connect_bd_net -net current_monitor_m1_adc_enable_ia [get_bd_pins current_monitor_m1/adc_enable_ia] [get_bd_pins current_monitor_m1_apack/chan_enable_0] + connect_bd_net -net current_monitor_m1_adc_enable_ib [get_bd_pins current_monitor_m1/adc_enable_ib] [get_bd_pins current_monitor_m1_apack/chan_enable_1] + connect_bd_net -net current_monitor_m1_adc_enable_vbus [get_bd_pins current_monitor_m1/adc_enable_vbus] [get_bd_pins current_monitor_m1_apack/chan_enable_2] + connect_bd_net -net current_monitor_m1_adc_enable_stub [get_bd_pins current_monitor_m1/adc_enable_stub] [get_bd_pins current_monitor_m1_apack/chan_enable_3] + connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_0] [get_bd_pins current_monitor_m1/i_ready_o] + connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_1] [get_bd_pins current_monitor_m1/i_ready_o] + connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_2] [get_bd_pins current_monitor_m1/i_ready_o] + connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_apack/chan_valid_3] [get_bd_pins current_monitor_m1/i_ready_o] + connect_bd_net [get_bd_pins current_monitor_m1/ia_o] [get_bd_pins current_monitor_m1_apack/chan_data_0] + connect_bd_net [get_bd_pins current_monitor_m1/ib_o] [get_bd_pins current_monitor_m1_apack/chan_data_1] + connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_apack/chan_data_2] + connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_apack/chan_data_3] + connect_bd_net [get_bd_pins current_monitor_m1_apack/ddata] [get_bd_pins current_monitor_m1_dma/fifo_wr_din] + connect_bd_net [get_bd_pins current_monitor_m1_apack/dvalid] [get_bd_pins current_monitor_m1_dma/fifo_wr_en] + +# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m1_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0] +# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset] +# connect_bd_net -net current_monitor_m1_adc_enable_ia [get_bd_pins current_monitor_m1/adc_enable_ia] [get_bd_pins current_monitor_m1_pack/adc_enable_0] +# connect_bd_net -net current_monitor_m1_adc_enable_ib [get_bd_pins current_monitor_m1/adc_enable_ib] [get_bd_pins current_monitor_m1_pack/adc_enable_1] +# connect_bd_net -net current_monitor_m1_adc_enable_vbus [get_bd_pins current_monitor_m1/adc_enable_vbus] [get_bd_pins current_monitor_m1_pack/adc_enable_2] +# connect_bd_net -net current_monitor_m1_adc_enable_stub [get_bd_pins current_monitor_m1/adc_enable_stub] [get_bd_pins current_monitor_m1_pack/adc_enable_3] +# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_0] [get_bd_pins current_monitor_m1/i_ready_o] +# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_1] [get_bd_pins current_monitor_m1/i_ready_o] +# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_2] [get_bd_pins current_monitor_m1/i_ready_o] +# connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins current_monitor_m1_pack/adc_valid_3] [get_bd_pins current_monitor_m1/i_ready_o] +# connect_bd_net [get_bd_pins current_monitor_m1/ia_o] [get_bd_pins current_monitor_m1_pack/adc_data_0] +# connect_bd_net [get_bd_pins current_monitor_m1/ib_o] [get_bd_pins current_monitor_m1_pack/adc_data_1] +# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_2] +# connect_bd_net [get_bd_pins current_monitor_m1/vbus_o] [get_bd_pins current_monitor_m1_pack/adc_data_3] +# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_data] [get_bd_pins current_monitor_m1_dma/fifo_wr_din] +# connect_bd_net [get_bd_pins current_monitor_m1_pack/adc_valid] [get_bd_pins current_monitor_m1_dma/fifo_wr_en] + + # motor 2 + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2/ref_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/fifo_wr_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins current_monitor_m2_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/m_dest_axi_aresetn] + + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net adc_m2_ia_dat_i_1 [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins current_monitor_m2/adc_ia_dat_i] + connect_bd_net -net adc_m2_ib_dat_i_1 [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins current_monitor_m2/adc_ib_dat_i] + connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins current_monitor_m2/adc_vbus_dat_i] + + connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m2_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0] + connect_bd_net -net current_monitor_m2_adc_enable_ia [get_bd_pins current_monitor_m2/adc_enable_ia] [get_bd_pins current_monitor_m2_apack/chan_enable_0] + connect_bd_net -net current_monitor_m2_adc_enable_ib [get_bd_pins current_monitor_m2/adc_enable_ib] [get_bd_pins current_monitor_m2_apack/chan_enable_1] + connect_bd_net -net current_monitor_m2_adc_enable_vbus [get_bd_pins current_monitor_m2/adc_enable_vbus] [get_bd_pins current_monitor_m2_apack/chan_enable_2] + connect_bd_net -net current_monitor_m2_adc_enable_stub [get_bd_pins current_monitor_m2/adc_enable_stub] [get_bd_pins current_monitor_m2_apack/chan_enable_3] + connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_0] [get_bd_pins current_monitor_m2/i_ready_o] + connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_1] [get_bd_pins current_monitor_m2/i_ready_o] + connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_2] [get_bd_pins current_monitor_m2/i_ready_o] + connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_apack/chan_valid_3] [get_bd_pins current_monitor_m2/i_ready_o] + connect_bd_net [get_bd_pins current_monitor_m2/ia_o] [get_bd_pins current_monitor_m2_apack/chan_data_0] + connect_bd_net [get_bd_pins current_monitor_m2/ib_o] [get_bd_pins current_monitor_m2_apack/chan_data_1] + connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_apack/chan_data_2] + connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_apack/chan_data_3] + connect_bd_net [get_bd_pins current_monitor_m2_apack/ddata] [get_bd_pins current_monitor_m2_dma/fifo_wr_din] + connect_bd_net [get_bd_pins current_monitor_m2_apack/dvalid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en] +# connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins current_monitor_m2_pack/adc_clk] [get_bd_pins sys_ps7/FCLK_CLK0] +# connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins current_monitor_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset] +# connect_bd_net -net current_monitor_m2_adc_enable_ia [get_bd_pins current_monitor_m2/adc_enable_ia] [get_bd_pins current_monitor_m2_pack/adc_enable_0] +# connect_bd_net -net current_monitor_m2_adc_enable_ib [get_bd_pins current_monitor_m2/adc_enable_ib] [get_bd_pins current_monitor_m2_pack/adc_enable_1] +# connect_bd_net -net current_monitor_m2_adc_enable_vbus [get_bd_pins current_monitor_m2/adc_enable_vbus] [get_bd_pins current_monitor_m2_pack/adc_enable_2] +# connect_bd_net -net current_monitor_m2_adc_enable_stub [get_bd_pins current_monitor_m2/adc_enable_stub] [get_bd_pins current_monitor_m2_pack/adc_enable_3] +# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_0] [get_bd_pins current_monitor_m2/i_ready_o] +# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_1] [get_bd_pins current_monitor_m2/i_ready_o] +# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_2] [get_bd_pins current_monitor_m2/i_ready_o] +# connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins current_monitor_m2_pack/adc_valid_3] [get_bd_pins current_monitor_m2/i_ready_o] +# connect_bd_net [get_bd_pins current_monitor_m2/ia_o] [get_bd_pins current_monitor_m2_pack/adc_data_0] +# connect_bd_net [get_bd_pins current_monitor_m2/ib_o] [get_bd_pins current_monitor_m2_pack/adc_data_1] +# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_2] +# connect_bd_net [get_bd_pins current_monitor_m2/vbus_o] [get_bd_pins current_monitor_m2_pack/adc_data_3] +# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_valid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en] +# connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_data] [get_bd_pins current_monitor_m2_dma/fifo_wr_din] + + # interrupts + connect_bd_net -net axi_current_monitor_1_dma_intr [get_bd_pins current_monitor_m1_dma/irq] [get_bd_ports motcon2_c_m1_intr] + connect_bd_net -net axi_current_monitor_2_dma_intr [get_bd_pins current_monitor_m2_dma/irq] [get_bd_ports motcon2_c_m2_intr] + + #controller + # motor 1 + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/fifo_wr_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1_dma/m_dest_axi_aresetn] + + connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins controller_m1/fmc_m1_en_o] + connect_bd_net -net axi_mc_controller_m1_pwm_al_o [get_bd_ports pwm_m1_al_o] [get_bd_pins controller_m1/pwm_al_o] + connect_bd_net -net axi_mc_controller_m1_pwm_ah_o [get_bd_ports pwm_m1_ah_o] [get_bd_pins controller_m1/pwm_ah_o] + connect_bd_net -net axi_mc_controller_m1_pwm_bl_o [get_bd_ports pwm_m1_bl_o] [get_bd_pins controller_m1/pwm_bl_o] + connect_bd_net -net axi_mc_controller_m1_pwm_bh_o [get_bd_ports pwm_m1_bh_o] [get_bd_pins controller_m1/pwm_bh_o] + connect_bd_net -net axi_mc_controller_m1_pwm_cl_o [get_bd_ports pwm_m1_cl_o] [get_bd_pins controller_m1/pwm_cl_o] + connect_bd_net -net axi_mc_controller_m1_pwm_ch_o [get_bd_ports pwm_m1_ch_o] [get_bd_pins controller_m1/pwm_ch_o] + + connect_bd_net -net axi_mc_controller_m1_sensors_o [get_bd_pins controller_m1/sensors_o] [get_bd_pins speed_detector_m1/hall_bemf_i] + connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins controller_m1/position_i] [get_bd_pins speed_detector_m1/position_o] + connect_bd_net -net current_monitor_m1_i_ready_o [get_bd_pins controller_m1/ctrl_data_valid_i] [get_bd_pins current_monitor_m1/i_ready_o] + + #connect_bd_net -net controller_m1_adc_clk_o [get_bd_pins controller_m1_pack/adc_clk] [get_bd_pins controller_m1/adc_clk_o] + #connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m1_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset] + + #connect_bd_net -net controller_m1_adc_enable_c0 [get_bd_pins controller_m1/adc_enable_c0] [get_bd_pins controller_m1_pack/adc_enable_0] + #connect_bd_net -net controller_m1_adc_enable_c1 [get_bd_pins controller_m1/adc_enable_c1] [get_bd_pins controller_m1_pack/adc_enable_1] + #connect_bd_net -net controller_m1_adc_enable_c2 [get_bd_pins controller_m1/adc_enable_c2] [get_bd_pins controller_m1_pack/adc_enable_2] + #connect_bd_net -net controller_m1_adc_enable_c3 [get_bd_pins controller_m1/adc_enable_c3] [get_bd_pins controller_m1_pack/adc_enable_3] + #connect_bd_net -net controller_m1_adc_enable_c4 [get_bd_pins controller_m1/adc_enable_c4] [get_bd_pins controller_m1_pack/adc_enable_4] + #connect_bd_net -net controller_m1_adc_enable_c5 [get_bd_pins controller_m1/adc_enable_c5] [get_bd_pins controller_m1_pack/adc_enable_5] + #connect_bd_net -net controller_m1_adc_enable_c6 [get_bd_pins controller_m1/adc_enable_c6] [get_bd_pins controller_m1_pack/adc_enable_6] + #connect_bd_net -net controller_m1_adc_enable_c7 [get_bd_pins controller_m1/adc_enable_c7] [get_bd_pins controller_m1_pack/adc_enable_7] + + #connect_bd_net -net controller_m1_adc_valid_c0 [get_bd_pins controller_m1/adc_valid_c0] [get_bd_pins controller_m1_pack/adc_valid_0] + #connect_bd_net -net controller_m1_adc_valid_c1 [get_bd_pins controller_m1/adc_valid_c1] [get_bd_pins controller_m1_pack/adc_valid_1] + #connect_bd_net -net controller_m1_adc_valid_c2 [get_bd_pins controller_m1/adc_valid_c2] [get_bd_pins controller_m1_pack/adc_valid_2] + #connect_bd_net -net controller_m1_adc_valid_c3 [get_bd_pins controller_m1/adc_valid_c3] [get_bd_pins controller_m1_pack/adc_valid_3] + #connect_bd_net -net controller_m1_adc_valid_c4 [get_bd_pins controller_m1/adc_valid_c4] [get_bd_pins controller_m1_pack/adc_valid_4] + #connect_bd_net -net controller_m1_adc_valid_c5 [get_bd_pins controller_m1/adc_valid_c5] [get_bd_pins controller_m1_pack/adc_valid_5] + #connect_bd_net -net controller_m1_adc_valid_c6 [get_bd_pins controller_m1/adc_valid_c6] [get_bd_pins controller_m1_pack/adc_valid_6] + #connect_bd_net -net controller_m1_adc_valid_c7 [get_bd_pins controller_m1/adc_valid_c7] [get_bd_pins controller_m1_pack/adc_valid_7] + + #connect_bd_net -net controller_m1_data_c0 [get_bd_pins controller_m1/adc_data_c0] [get_bd_pins controller_m1_pack/adc_data_0] + #connect_bd_net -net controller_m1_data_c1 [get_bd_pins controller_m1/adc_data_c1] [get_bd_pins controller_m1_pack/adc_data_1] + #connect_bd_net -net controller_m1_data_c2 [get_bd_pins controller_m1/adc_data_c2] [get_bd_pins controller_m1_pack/adc_data_2] + #connect_bd_net -net controller_m1_data_c3 [get_bd_pins controller_m1/adc_data_c3] [get_bd_pins controller_m1_pack/adc_data_3] + #connect_bd_net -net controller_m1_data_c4 [get_bd_pins controller_m1/adc_data_c4] [get_bd_pins controller_m1_pack/adc_data_4] + #connect_bd_net -net controller_m1_data_c5 [get_bd_pins controller_m1/adc_data_c5] [get_bd_pins controller_m1_pack/adc_data_5] + #connect_bd_net -net controller_m1_data_c6 [get_bd_pins controller_m1/adc_data_c6] [get_bd_pins controller_m1_pack/adc_data_6] + #connect_bd_net -net controller_m1_data_c7 [get_bd_pins controller_m1/adc_data_c7] [get_bd_pins controller_m1_pack/adc_data_7] + + #connect_bd_net [get_bd_pins controller_m1_pack/adc_data] [get_bd_pins controller_m1_dma/fifo_wr_din] + #connect_bd_net [get_bd_pins controller_m1_pack/adc_valid] [get_bd_pins controller_m1_dma/fifo_wr_en] + + connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins controller_m1_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0] + + connect_bd_net -net controller_m1_adc_enable_c0 [get_bd_pins controller_m1/adc_enable_c0] [get_bd_pins controller_m1_apack/chan_enable_0] + connect_bd_net -net controller_m1_adc_enable_c1 [get_bd_pins controller_m1/adc_enable_c1] [get_bd_pins controller_m1_apack/chan_enable_1] + connect_bd_net -net controller_m1_adc_enable_c2 [get_bd_pins controller_m1/adc_enable_c2] [get_bd_pins controller_m1_apack/chan_enable_2] + connect_bd_net -net controller_m1_adc_enable_c3 [get_bd_pins controller_m1/adc_enable_c3] [get_bd_pins controller_m1_apack/chan_enable_3] + connect_bd_net -net controller_m1_adc_enable_c4 [get_bd_pins controller_m1/adc_enable_c4] [get_bd_pins controller_m1_apack/chan_enable_4] + connect_bd_net -net controller_m1_adc_enable_c5 [get_bd_pins controller_m1/adc_enable_c5] [get_bd_pins controller_m1_apack/chan_enable_5] + connect_bd_net -net controller_m1_adc_enable_c6 [get_bd_pins controller_m1/adc_enable_c6] [get_bd_pins controller_m1_apack/chan_enable_6] + connect_bd_net -net controller_m1_adc_enable_c7 [get_bd_pins controller_m1/adc_enable_c7] [get_bd_pins controller_m1_apack/chan_enable_7] + + connect_bd_net -net controller_m1_adc_valid_c0 [get_bd_pins controller_m1/adc_valid_c0] [get_bd_pins controller_m1_apack/chan_valid_0] + connect_bd_net -net controller_m1_adc_valid_c1 [get_bd_pins controller_m1/adc_valid_c1] [get_bd_pins controller_m1_apack/chan_valid_1] + connect_bd_net -net controller_m1_adc_valid_c2 [get_bd_pins controller_m1/adc_valid_c2] [get_bd_pins controller_m1_apack/chan_valid_2] + connect_bd_net -net controller_m1_adc_valid_c3 [get_bd_pins controller_m1/adc_valid_c3] [get_bd_pins controller_m1_apack/chan_valid_3] + connect_bd_net -net controller_m1_adc_valid_c4 [get_bd_pins controller_m1/adc_valid_c4] [get_bd_pins controller_m1_apack/chan_valid_4] + connect_bd_net -net controller_m1_adc_valid_c5 [get_bd_pins controller_m1/adc_valid_c5] [get_bd_pins controller_m1_apack/chan_valid_5] + connect_bd_net -net controller_m1_adc_valid_c6 [get_bd_pins controller_m1/adc_valid_c6] [get_bd_pins controller_m1_apack/chan_valid_6] + connect_bd_net -net controller_m1_adc_valid_c7 [get_bd_pins controller_m1/adc_valid_c7] [get_bd_pins controller_m1_apack/chan_valid_7] + + connect_bd_net -net controller_m1_data_c0 [get_bd_pins controller_m1/adc_data_c0] [get_bd_pins controller_m1_apack/chan_data_0] + connect_bd_net -net controller_m1_data_c1 [get_bd_pins controller_m1/adc_data_c1] [get_bd_pins controller_m1_apack/chan_data_1] + connect_bd_net -net controller_m1_data_c2 [get_bd_pins controller_m1/adc_data_c2] [get_bd_pins controller_m1_apack/chan_data_2] + connect_bd_net -net controller_m1_data_c3 [get_bd_pins controller_m1/adc_data_c3] [get_bd_pins controller_m1_apack/chan_data_3] + connect_bd_net -net controller_m1_data_c4 [get_bd_pins controller_m1/adc_data_c4] [get_bd_pins controller_m1_apack/chan_data_4] + connect_bd_net -net controller_m1_data_c5 [get_bd_pins controller_m1/adc_data_c5] [get_bd_pins controller_m1_apack/chan_data_5] + connect_bd_net -net controller_m1_data_c6 [get_bd_pins controller_m1/adc_data_c6] [get_bd_pins controller_m1_apack/chan_data_6] + connect_bd_net -net controller_m1_data_c7 [get_bd_pins controller_m1/adc_data_c7] [get_bd_pins controller_m1_apack/chan_data_7] + + connect_bd_net [get_bd_pins controller_m1_apack/ddata] [get_bd_pins controller_m1_dma/fifo_wr_din] + connect_bd_net [get_bd_pins controller_m1_apack/dvalid] [get_bd_pins controller_m1_dma/fifo_wr_en] + + # motor 2 + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/ref_clk] $sys_100m_clk_source + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2/s_axi_aresetn] $sys_100m_resetn_source + + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/m_dest_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/fifo_wr_clk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2_dma/s_axi_aresetn] + connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2_dma/m_dest_axi_aresetn] + + connect_bd_net -net axi_mc_controller_m2_fmc_m1_en_o [get_bd_ports fmc_m2_en_o] [get_bd_pins controller_m2/fmc_m1_en_o] + connect_bd_net -net axi_mc_controller_m2_pwm_al_o [get_bd_ports pwm_m2_al_o] [get_bd_pins controller_m2/pwm_al_o] + connect_bd_net -net axi_mc_controller_m2_pwm_ah_o [get_bd_ports pwm_m2_ah_o] [get_bd_pins controller_m2/pwm_ah_o] + connect_bd_net -net axi_mc_controller_m2_pwm_bl_o [get_bd_ports pwm_m2_bl_o] [get_bd_pins controller_m2/pwm_bl_o] + connect_bd_net -net axi_mc_controller_m2_pwm_bh_o [get_bd_ports pwm_m2_bh_o] [get_bd_pins controller_m2/pwm_bh_o] + connect_bd_net -net axi_mc_controller_m2_pwm_cl_o [get_bd_ports pwm_m2_cl_o] [get_bd_pins controller_m2/pwm_cl_o] + connect_bd_net -net axi_mc_controller_m2_pwm_ch_o [get_bd_ports pwm_m2_ch_o] [get_bd_pins controller_m2/pwm_ch_o] + + connect_bd_net -net axi_mc_controller_m2_sensors_o [get_bd_pins controller_m2/sensors_o] [get_bd_pins speed_detector_m2/hall_bemf_i] + connect_bd_net -net axi_mc_speed_2_position_o [get_bd_pins controller_m2/position_i] [get_bd_pins speed_detector_m2/position_o] + connect_bd_net -net current_monitor_m2_i_ready_o [get_bd_pins controller_m2/ctrl_data_valid_i] [get_bd_pins current_monitor_m2/i_ready_o] + + #connect_bd_net -net controller_m2_adc_clk_o [get_bd_pins controller_m2_pack/adc_clk] [get_bd_pins controller_m2/adc_clk_o] + #connect_bd_net -net [get_bd_nets sys_rstgen_peripheral_reset] [get_bd_pins controller_m2_pack/adc_rst] [get_bd_pins sys_rstgen/peripheral_reset] + + #connect_bd_net -net controller_m2_adc_enable_c0 [get_bd_pins controller_m2/adc_enable_c0] [get_bd_pins controller_m2_pack/adc_enable_0] + #connect_bd_net -net controller_m2_adc_enable_c1 [get_bd_pins controller_m2/adc_enable_c1] [get_bd_pins controller_m2_pack/adc_enable_1] + #connect_bd_net -net controller_m2_adc_enable_c2 [get_bd_pins controller_m2/adc_enable_c2] [get_bd_pins controller_m2_pack/adc_enable_2] + #connect_bd_net -net controller_m2_adc_enable_c3 [get_bd_pins controller_m2/adc_enable_c3] [get_bd_pins controller_m2_pack/adc_enable_3] + #connect_bd_net -net controller_m2_adc_enable_c4 [get_bd_pins controller_m2/adc_enable_c4] [get_bd_pins controller_m2_pack/adc_enable_4] + #connect_bd_net -net controller_m2_adc_enable_c5 [get_bd_pins controller_m2/adc_enable_c5] [get_bd_pins controller_m2_pack/adc_enable_5] + #connect_bd_net -net controller_m2_adc_enable_c6 [get_bd_pins controller_m2/adc_enable_c6] [get_bd_pins controller_m2_pack/adc_enable_6] + #connect_bd_net -net controller_m2_adc_enable_c7 [get_bd_pins controller_m2/adc_enable_c7] [get_bd_pins controller_m2_pack/adc_enable_7] + + #connect_bd_net -net controller_m2_adc_valid_c0 [get_bd_pins controller_m2/adc_valid_c0] [get_bd_pins controller_m2_pack/adc_valid_0] + #connect_bd_net -net controller_m2_adc_valid_c1 [get_bd_pins controller_m2/adc_valid_c1] [get_bd_pins controller_m2_pack/adc_valid_1] + #connect_bd_net -net controller_m2_adc_valid_c2 [get_bd_pins controller_m2/adc_valid_c2] [get_bd_pins controller_m2_pack/adc_valid_2] + #connect_bd_net -net controller_m2_adc_valid_c3 [get_bd_pins controller_m2/adc_valid_c3] [get_bd_pins controller_m2_pack/adc_valid_3] + #connect_bd_net -net controller_m2_adc_valid_c4 [get_bd_pins controller_m2/adc_valid_c4] [get_bd_pins controller_m2_pack/adc_valid_4] + #connect_bd_net -net controller_m2_adc_valid_c5 [get_bd_pins controller_m2/adc_valid_c5] [get_bd_pins controller_m2_pack/adc_valid_5] + #connect_bd_net -net controller_m2_adc_valid_c6 [get_bd_pins controller_m2/adc_valid_c6] [get_bd_pins controller_m2_pack/adc_valid_6] + #connect_bd_net -net controller_m2_adc_valid_c7 [get_bd_pins controller_m2/adc_valid_c7] [get_bd_pins controller_m2_pack/adc_valid_7] + + #connect_bd_net -net controller_m2_data_c0 [get_bd_pins controller_m2/adc_data_c0] [get_bd_pins controller_m2_pack/adc_data_0] + #connect_bd_net -net controller_m2_data_c1 [get_bd_pins controller_m2/adc_data_c1] [get_bd_pins controller_m2_pack/adc_data_1] + #connect_bd_net -net controller_m2_data_c2 [get_bd_pins controller_m2/adc_data_c2] [get_bd_pins controller_m2_pack/adc_data_2] + #connect_bd_net -net controller_m2_data_c3 [get_bd_pins controller_m2/adc_data_c3] [get_bd_pins controller_m2_pack/adc_data_3] + #connect_bd_net -net controller_m2_data_c4 [get_bd_pins controller_m2/adc_data_c4] [get_bd_pins controller_m2_pack/adc_data_4] + #connect_bd_net -net controller_m2_data_c5 [get_bd_pins controller_m2/adc_data_c5] [get_bd_pins controller_m2_pack/adc_data_5] + #connect_bd_net -net controller_m2_data_c6 [get_bd_pins controller_m2/adc_data_c6] [get_bd_pins controller_m2_pack/adc_data_6] + #connect_bd_net -net controller_m2_data_c7 [get_bd_pins controller_m2/adc_data_c7] [get_bd_pins controller_m2_pack/adc_data_7] + + #connect_bd_net [get_bd_pins controller_m2_pack/adc_data] [get_bd_pins controller_m2_dma/fifo_wr_din] + #connect_bd_net [get_bd_pins controller_m2_pack/adc_valid] [get_bd_pins controller_m2_dma/fifo_wr_en] + + connect_bd_net -net [get_bd_nets sys_100m_clk] [get_bd_pins controller_m2_apack/clk] [get_bd_pins sys_ps7/FCLK_CLK0] + + connect_bd_net -net controller_m2_adc_enable_c0 [get_bd_pins controller_m2/adc_enable_c0] [get_bd_pins controller_m2_apack/chan_enable_0] + connect_bd_net -net controller_m2_adc_enable_c1 [get_bd_pins controller_m2/adc_enable_c1] [get_bd_pins controller_m2_apack/chan_enable_1] + connect_bd_net -net controller_m2_adc_enable_c2 [get_bd_pins controller_m2/adc_enable_c2] [get_bd_pins controller_m2_apack/chan_enable_2] + connect_bd_net -net controller_m2_adc_enable_c3 [get_bd_pins controller_m2/adc_enable_c3] [get_bd_pins controller_m2_apack/chan_enable_3] + connect_bd_net -net controller_m2_adc_enable_c4 [get_bd_pins controller_m2/adc_enable_c4] [get_bd_pins controller_m2_apack/chan_enable_4] + connect_bd_net -net controller_m2_adc_enable_c5 [get_bd_pins controller_m2/adc_enable_c5] [get_bd_pins controller_m2_apack/chan_enable_5] + connect_bd_net -net controller_m2_adc_enable_c6 [get_bd_pins controller_m2/adc_enable_c6] [get_bd_pins controller_m2_apack/chan_enable_6] + connect_bd_net -net controller_m2_adc_enable_c7 [get_bd_pins controller_m2/adc_enable_c7] [get_bd_pins controller_m2_apack/chan_enable_7] + + connect_bd_net -net controller_m2_adc_valid_c0 [get_bd_pins controller_m2/adc_valid_c0] [get_bd_pins controller_m2_apack/chan_valid_0] + connect_bd_net -net controller_m2_adc_valid_c1 [get_bd_pins controller_m2/adc_valid_c1] [get_bd_pins controller_m2_apack/chan_valid_1] + connect_bd_net -net controller_m2_adc_valid_c2 [get_bd_pins controller_m2/adc_valid_c2] [get_bd_pins controller_m2_apack/chan_valid_2] + connect_bd_net -net controller_m2_adc_valid_c3 [get_bd_pins controller_m2/adc_valid_c3] [get_bd_pins controller_m2_apack/chan_valid_3] + connect_bd_net -net controller_m2_adc_valid_c4 [get_bd_pins controller_m2/adc_valid_c4] [get_bd_pins controller_m2_apack/chan_valid_4] + connect_bd_net -net controller_m2_adc_valid_c5 [get_bd_pins controller_m2/adc_valid_c5] [get_bd_pins controller_m2_apack/chan_valid_5] + connect_bd_net -net controller_m2_adc_valid_c6 [get_bd_pins controller_m2/adc_valid_c6] [get_bd_pins controller_m2_apack/chan_valid_6] + connect_bd_net -net controller_m2_adc_valid_c7 [get_bd_pins controller_m2/adc_valid_c7] [get_bd_pins controller_m2_apack/chan_valid_7] + + connect_bd_net -net controller_m2_data_c0 [get_bd_pins controller_m2/adc_data_c0] [get_bd_pins controller_m2_apack/chan_data_0] + connect_bd_net -net controller_m2_data_c1 [get_bd_pins controller_m2/adc_data_c1] [get_bd_pins controller_m2_apack/chan_data_1] + connect_bd_net -net controller_m2_data_c2 [get_bd_pins controller_m2/adc_data_c2] [get_bd_pins controller_m2_apack/chan_data_2] + connect_bd_net -net controller_m2_data_c3 [get_bd_pins controller_m2/adc_data_c3] [get_bd_pins controller_m2_apack/chan_data_3] + connect_bd_net -net controller_m2_data_c4 [get_bd_pins controller_m2/adc_data_c4] [get_bd_pins controller_m2_apack/chan_data_4] + connect_bd_net -net controller_m2_data_c5 [get_bd_pins controller_m2/adc_data_c5] [get_bd_pins controller_m2_apack/chan_data_5] + connect_bd_net -net controller_m2_data_c6 [get_bd_pins controller_m2/adc_data_c6] [get_bd_pins controller_m2_apack/chan_data_6] + connect_bd_net -net controller_m2_data_c7 [get_bd_pins controller_m2/adc_data_c7] [get_bd_pins controller_m2_apack/chan_data_7] + + connect_bd_net [get_bd_pins controller_m2_apack/ddata] [get_bd_pins controller_m2_dma/fifo_wr_din] + connect_bd_net [get_bd_pins controller_m2_apack/dvalid] [get_bd_pins controller_m2_dma/fifo_wr_en] + # interrupts + connect_bd_net -net controller_m1_dma_intr [get_bd_pins controller_m1_dma/irq] [get_bd_ports motcon2_ctrl_m1_intr] + connect_bd_net -net controller_m2_dma_intr [get_bd_pins controller_m2_dma/irq] [get_bd_ports motcon2_ctrl_m2_intr] + + # ethernet + + connect_bd_net -net sys_200m_clk [get_bd_ports refclk] [get_bd_pins sys_ps7/FCLK_CLK1] + connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_ports refclk_rst] + connect_bd_net -net sys_100m_resetn [get_bd_ports eth_phy_rst_n] + connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_MDC] [get_bd_ports eth_mdio_mdc] + connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_O] [get_bd_ports eth_mdio_o] + connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_T] [get_bd_ports eth_mdio_t] + connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_I] [get_bd_ports eth_mdio_i] + # phy 1 + connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth1/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_0] + connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii] + connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth1/mdio_mdc] + connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_w] + connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_r] + # phy 2 + connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] + connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii] + connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + + connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth2/mdio_mdc] + connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_w] + connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_r] + + # xadc + #connect_bd_net -net sys_100m_clk [get_bd_pins xadc_core/s_axi_aclk] $sys_100m_clk_source + #connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_core/s_axi_aresetn] $sys_100m_resetn_source + #connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_core/Vaux0] [get_bd_intf_ports Vaux0] + #connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_core/Vaux8] [get_bd_intf_ports Vaux8] + #connect_bd_net -net xadc_muxout [get_bd_pins /xadc_core/muxaddr_out] [get_bd_ports muxaddr_out] + + # iic + connect_bd_net -net sys_100m_clk [get_bd_pins iic_ee2/s_axi_aclk] + connect_bd_net -net sys_100m_resetn [get_bd_pins iic_ee2/s_axi_aresetn] + connect_bd_intf_net [get_bd_intf_pins iic_ee2/IIC] [get_bd_intf_ports iic_ee2] + connect_bd_net -net iic_ee2_irq [get_bd_pins iic_ee2/iic2intc_irpt] [get_bd_ports iic_ee2_intr] + + # spi + connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] + connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O] + connect_bd_net -net spi_sclk_i [get_bd_ports spi_sclk_i] [get_bd_pins sys_ps7/SPI0_SCLK_I] + connect_bd_net -net spi_sclk_o [get_bd_ports spi_sclk_o] [get_bd_pins sys_ps7/SPI0_SCLK_O] + connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins sys_ps7/SPI0_MOSI_I] + connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] + connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + + # cpu interconnect + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M16_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M17_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M18_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M19_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M20_ACLK] $sys_100m_clk_source + + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M16_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M17_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M18_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M19_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M20_ARESETN] $sys_100m_resetn_source + + connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins iic_ee2/S_AXI] -boundary_type upper [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] +# connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins xadc_core/s_axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins speed_detector_m1/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins speed_detector_m1_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins speed_detector_m2/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins speed_detector_m2_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins current_monitor_m1/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins current_monitor_m1_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins current_monitor_m2/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins current_monitor_m2_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m17_axi [get_bd_intf_pins axi_cpu_interconnect/M17_AXI] [get_bd_intf_pins controller_m1/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m18_axi [get_bd_intf_pins axi_cpu_interconnect/M18_AXI] [get_bd_intf_pins controller_m1_dma/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m19_axi [get_bd_intf_pins axi_cpu_interconnect/M19_AXI] [get_bd_intf_pins controller_m2/s_axi] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m20_axi [get_bd_intf_pins axi_cpu_interconnect/M20_AXI] [get_bd_intf_pins controller_m2_dma/s_axi] + + # mem interconnect + connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S04_ACLK] $sys_100m_clk_source + connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S05_ACLK] $sys_100m_clk_source + + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S04_ARESETN] $sys_100m_resetn_source + connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S05_ARESETN] $sys_100m_resetn_source + + connect_bd_intf_net -intf_net axi_mem_interconnect_m00_axi [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] + connect_bd_intf_net -intf_net axi_mem_interconnect_s00_axi [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins speed_detector_m1_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s01_axi [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins speed_detector_m2_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins current_monitor_m1_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins current_monitor_m2_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s04_axi [get_bd_intf_pins axi_mem_interconnect/S04_AXI] [get_bd_intf_pins controller_m1_dma/m_dest_axi] + connect_bd_intf_net -intf_net axi_mem_interconnect_s05_axi [get_bd_intf_pins axi_mem_interconnect/S05_AXI] [get_bd_intf_pins controller_m2_dma/m_dest_axi] + + # address map + create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m1/s_axi/axi_lite] SEG_data_s_d1 + create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m1/s_axi/axi_lite] SEG_data_c_m1 + create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m1/s_axi/axi_lite] SEG_data_c1 + create_bd_addr_seg -range 0x10000 -offset 0x40440000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2/s_axi/axi_lite] SEG_data_s_d2 + create_bd_addr_seg -range 0x10000 -offset 0x40450000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2/s_axi/axi_lite] SEG_data_c_m2 + create_bd_addr_seg -range 0x10000 -offset 0x40460000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2/s_axi/axi_lite] SEG_data_c2 + create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m1_dma/s_axi/axi_lite] SEG_data_s_d1_dma + create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m1_dma/s_axi/axi_lite] SEG_data_c_m1_dma + create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m1_dma/s_axi/axi_lite] SEG_data_c1_dma + create_bd_addr_seg -range 0x10000 -offset 0x40540000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2_dma/s_axi/axi_lite] SEG_data_s_d2_dma + create_bd_addr_seg -range 0x10000 -offset 0x40550000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2_dma/s_axi/axi_lite] SEG_data_c_m2_dma + create_bd_addr_seg -range 0x10000 -offset 0x40560000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2_dma/s_axi/axi_lite] SEG_data_c2_dma +# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_core/s_axi_lite/Reg] SEG_data_xadc + create_bd_addr_seg -range 0x10000 -offset 0x41510000 $sys_addr_cntrl_space [get_bd_addr_segs iic_ee2/S_AXI/Reg] SEG_iic_ee2_Reg + + create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces current_monitor_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces current_monitor_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces controller_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm + create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces controller_m2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm diff --git a/projects/motcon2_fmc/zed/system_bd.tcl b/projects/motcon2_fmc/zed/system_bd.tcl new file mode 100644 index 000000000..139113832 --- /dev/null +++ b/projects/motcon2_fmc/zed/system_bd.tcl @@ -0,0 +1,4 @@ + + source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + source ../common/motcon2_fmc_bd.tcl + diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc new file mode 100644 index 000000000..04547ea1a --- /dev/null +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -0,0 +1,198 @@ + +#DEBUG + +# Motor Control +#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 + +set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[0]}] +set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[1]}] +set_property -dict {PACKAGE_PIN B16 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[2]}] + +set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[0]}] ; #M2_SENSOR_A +set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[1]}] ; #M2_SENSOR_B +set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVCMOS25} [get_ports {position_m2_i[2]}] ; #M2_SENSOR_C + +set_property -dict {PACKAGE_PIN C20 IOSTANDARD LVCMOS25} [get_ports vt_enable] + +set_property -dict {PACKAGE_PIN N17 IOSTANDARD LVCMOS25} [get_ports fmc_m1_en_o] +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ah_o] +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS25} [get_ports pwm_m1_al_o] +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bh_o] +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pwm_m1_bl_o] +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVCMOS25} [get_ports pwm_m1_ch_o] +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVCMOS25} [get_ports pwm_m1_cl_o] +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dh_o] +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports pwm_m1_dl_o] + +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports fmc_m2_en_o] +set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ah_o] +set_property -dict {PACKAGE_PIN J17 IOSTANDARD LVCMOS25} [get_ports pwm_m2_al_o] +set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bh_o] +set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVCMOS25} [get_ports pwm_m2_bl_o] +set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_ch_o] +set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVCMOS25} [get_ports pwm_m2_cl_o] +set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dh_o] +set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVCMOS25} [get_ports pwm_m2_dl_o] +set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVCMOS25 } [get_ports adc_clk_o] +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25 } [get_ports adc_m1_vbus_dat_i] +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25 } [get_ports adc_m2_vbus_dat_i] +set_property -dict {PACKAGE_PIN R19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ia_dat_i] +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25 } [get_ports adc_m1_ib_dat_i] +set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ia_dat_i] +set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25 } [get_ports adc_m2_ib_dat_i] + +# GPO +set_property -dict {PACKAGE_PIN A16 IOSTANDARD LVCMOS25 } [get_ports {gpo[0]}] +set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS25 } [get_ports {gpo[1]}] +set_property -dict {PACKAGE_PIN C15 IOSTANDARD LVCMOS25 } [get_ports {gpo[2]}] +set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}] + +# GPI +set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}] +set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}] + + +#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}] +#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}] +#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}] +#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}] + +#set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] +#set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] +#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] +#set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8] + +# SPI +set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sel1_rdc ] +set_property -dict {PACKAGE_PIN D22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_miso ] +set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_mosi ] +set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sck ] + +#FMC_SAMPLE_N +set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVCMOS25} [get_ports fmc_sample_n] + +# IIC +set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_scl_io] +set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_ee2_sda_io] + +# Ethernet common +set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVCMOS25} [get_ports eth_mdio_mdc] +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25 PULLUP true} [get_ports eth_mdio_io] +set_property -dict {PACKAGE_PIN G20 IOSTANDARD LVCMOS25} [get_ports eth_phy_rst_n] + +# Ethernet 1 +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rxc] +set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_rx_ctl] +set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[0]}] +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}] +set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}] +set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}] + +# Ethernet 2 +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc] +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rx_ctl] +set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[0]}] +set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}] +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}] +set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}] +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc] +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}] + +# Ethernet common + +set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] + +set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] +set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] +set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2] +set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2] +set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] +set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] +set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3] +set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3] +set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] +set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] + +# Ethernet 1 + +# Clock Period Constraints +create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] +#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] +#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] + +create_clock -name eth1_rx_clk_vir -period 8 + +set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}] +set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] +set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}] + +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] + +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -setup +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -setup +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -hold +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -hold + +set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -setup 0 +set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -hold -1 + +set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] +set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] +set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay +set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay + +# Ethernet 2 + +# Clock Period Constraints +create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] +#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] +#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] + +create_clock -name eth2_rx_clk_vir -period 8 +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps] +set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] + +set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}] +set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] +set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}] + +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] + +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -setup +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -setup +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -hold +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -hold + +set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -setup 0 +set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -hold -1 + +set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup +set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup +set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold +set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold + +set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] +set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] +set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay +set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay diff --git a/projects/motcon2_fmc/zed/system_top.v b/projects/motcon2_fmc/zed/system_top.v new file mode 100644 index 000000000..2d5db19bc --- /dev/null +++ b/projects/motcon2_fmc/zed/system_top.v @@ -0,0 +1,497 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2015(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + eth1_rgmii_rd, + eth1_rgmii_rx_ctl, + eth1_rgmii_rxc, + eth1_rgmii_td, + eth1_rgmii_tx_ctl, + eth1_rgmii_txc, + + eth2_rgmii_rd, + eth2_rgmii_rx_ctl, + eth2_rgmii_rxc, + eth2_rgmii_td, + eth2_rgmii_tx_ctl, + eth2_rgmii_txc, + + eth_mdio_io, + eth_mdio_mdc, + eth_phy_rst_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + position_m1_i, + position_m2_i, + adc_clk_o, + adc_m1_ia_dat_i, + adc_m1_ib_dat_i, + adc_m1_vbus_dat_i, + fmc_m1_en_o, + fmc_m2_en_o, + adc_m2_ia_dat_i, + adc_m2_ib_dat_i, + adc_m2_vbus_dat_i, + pwm_m1_ah_o, + pwm_m1_al_o, + pwm_m1_bh_o, + pwm_m1_bl_o, + pwm_m1_ch_o, + pwm_m1_cl_o, + pwm_m1_dh_o, + pwm_m1_dl_o, + pwm_m2_ah_o, + pwm_m2_al_o, + pwm_m2_bh_o, + pwm_m2_bl_o, + pwm_m2_ch_o, + pwm_m2_cl_o, + pwm_m2_dh_o, + pwm_m2_dl_o, + vt_enable, +/* vauxn0, + vauxn8, + vauxp0, + vauxp8, + muxaddr_out,*/ + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + spdif, + + iic_scl, + iic_sda, + iic_mux_scl, + iic_mux_sda, + + iic_ee2_scl_io, + iic_ee2_sda_io, + + fmc_spi1_sel1_rdc, + fmc_spi1_miso, + fmc_spi1_mosi, + fmc_spi1_sck, + fmc_sample_n, + gpo, + gpi, + + otg_vbusoc); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + input [3:0] eth1_rgmii_rd; + input eth1_rgmii_rx_ctl; + input eth1_rgmii_rxc; + output [3:0] eth1_rgmii_td; + output eth1_rgmii_tx_ctl; + output eth1_rgmii_txc; + + input [3:0] eth2_rgmii_rd; + input eth2_rgmii_rx_ctl; + input eth2_rgmii_rxc; + output [3:0] eth2_rgmii_td; + output eth2_rgmii_tx_ctl; + output eth2_rgmii_txc; + + inout eth_mdio_io; + output eth_mdio_mdc; + output eth_phy_rst_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [31:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + input [2:0] position_m1_i; + input [2:0] position_m2_i; + output adc_clk_o; + output fmc_m1_en_o; + input adc_m1_ia_dat_i; + input adc_m1_ib_dat_i; + input adc_m1_vbus_dat_i; + output fmc_m2_en_o; + input adc_m2_ia_dat_i; + input adc_m2_ib_dat_i; + input adc_m2_vbus_dat_i; + output pwm_m1_ah_o; + output pwm_m1_al_o; + output pwm_m1_bh_o; + output pwm_m1_bl_o; + output pwm_m1_ch_o; + output pwm_m1_cl_o; + output pwm_m1_dh_o; + output pwm_m1_dl_o; + output pwm_m2_ah_o; + output pwm_m2_al_o; + output pwm_m2_bh_o; + output pwm_m2_bl_o; + output pwm_m2_ch_o; + output pwm_m2_cl_o; + output pwm_m2_dh_o; + output pwm_m2_dl_o; + + output vt_enable; + +/* input vauxn0; + input vauxn8; + input vauxp0; + input vauxp8; + output [ 3:0] muxaddr_out;*/ + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + + inout iic_scl; + inout iic_sda; + inout [ 1:0] iic_mux_scl; + inout [ 1:0] iic_mux_sda; + + inout iic_ee2_scl_io; + inout iic_ee2_sda_io; + + output fmc_spi1_sel1_rdc; + input fmc_spi1_miso; + output fmc_spi1_mosi; + output fmc_spi1_sck; + output fmc_sample_n; + output [ 3:0] gpo; + input [ 1:0] gpi; + + input otg_vbusoc; + + // internal signals + + wire [34:0] gpio_i; + wire [34:0] gpio_o; + wire [34:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + wire [15:0] ps_intrs; + + wire refclk; + wire refclk_rst; + + wire eth_mdio_o; + wire eth_mdio_i; + wire eth_mdio_t; + + reg idelayctrl_reset; + reg [ 3:0] idelay_reset_cnt; + + // assignments + + assign fmc_sample_n = gpio_o[32]; + assign gpio_i[34:33] = gpi[1:0]; + assign vt_enable = 1'b1; + assign pwm_m1_dh_o = 1'b0; + assign pwm_m1_dl_o = 1'b0; + assign pwm_m2_dh_o = 1'b0; + assign pwm_m2_dl_o = 1'b0; + // instantiations + + ad_iobuf #( + .DATA_WIDTH(32)) + i_gpio_bd ( + .dt(gpio_t[31:0]), + .di(gpio_o[31:0]), + .do(gpio_i[31:0]), + .dio(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2)) + i_iic_mux_scl ( + .dt({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .di(iic_mux_scl_o_s), + .do(iic_mux_scl_i_s), + .dio(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2)) + i_iic_mux_sda ( + .dt({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .di(iic_mux_sda_o_s), + .do(iic_mux_sda_i_s), + .dio(iic_mux_sda)); + + ad_iobuf #( + .DATA_WIDTH(1)) + i_mdio_io ( + .dt(eth_mdio_t), + .di(eth_mdio_o), + .do(eth_mdio_i), + .dio(eth_mdio_io)); + + always @(posedge refclk) begin + if (refclk_rst == 1'b1) begin + idelay_reset_cnt <= 4'h0; + idelayctrl_reset <= 1'b1; + end else begin + idelayctrl_reset <= 1'b1; + case (idelay_reset_cnt) + 4'h0: idelay_reset_cnt <= 4'h1; + 4'h1: idelay_reset_cnt <= 4'h2; + 4'h2: idelay_reset_cnt <= 4'h3; + 4'h3: idelay_reset_cnt <= 4'h4; + 4'h4: idelay_reset_cnt <= 4'h5; + 4'h5: idelay_reset_cnt <= 4'h6; + 4'h6: idelay_reset_cnt <= 4'h7; + 4'h7: idelay_reset_cnt <= 4'h8; + 4'h8: idelay_reset_cnt <= 4'h9; + 4'h9: idelay_reset_cnt <= 4'ha; + 4'ha: idelay_reset_cnt <= 4'hb; + 4'hb: idelay_reset_cnt <= 4'hc; + 4'hc: idelay_reset_cnt <= 4'hd; + 4'hd: idelay_reset_cnt <= 4'he; + default: begin + idelay_reset_cnt <= 4'he; + idelayctrl_reset <= 1'b0; + end + endcase + end + end + + IDELAYCTRL dlyctrl ( + .RDY(), + .REFCLK(refclk), + .RST(idelayctrl_reset)); + + system_wrapper i_system_wrapper ( + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + + .eth1_rgmii_rd(eth1_rgmii_rd), + .eth1_rgmii_rx_ctl(eth1_rgmii_rx_ctl), + .eth1_rgmii_rxc(eth1_rgmii_rxc), + .eth1_rgmii_td(eth1_rgmii_td), + .eth1_rgmii_tx_ctl(eth1_rgmii_tx_ctl), + .eth1_rgmii_txc(eth1_rgmii_txc), + + .eth2_rgmii_rd(eth2_rgmii_rd), + .eth2_rgmii_rx_ctl(eth2_rgmii_rx_ctl), + .eth2_rgmii_rxc(eth2_rgmii_rxc), + .eth2_rgmii_td(eth2_rgmii_td), + .eth2_rgmii_tx_ctl(eth2_rgmii_tx_ctl), + .eth2_rgmii_txc(eth2_rgmii_txc), + + .eth_phy_rst_n(eth_phy_rst_n), + .eth_mdio_o(eth_mdio_o), + .eth_mdio_t(eth_mdio_t), + .eth_mdio_i(eth_mdio_i), + .eth_mdio_mdc(eth_mdio_mdc), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .position_m1_i(position_m1_i), + .position_m2_i(position_m2_i), + .adc_clk_o(adc_clk_o), + .fmc_m1_en_o(fmc_m1_en_o), + .adc_m1_ia_dat_i(adc_m1_ia_dat_i), + .adc_m1_ib_dat_i(adc_m1_ib_dat_i), + .adc_m1_vbus_dat_i(adc_m1_vbus_dat_i), + .fmc_m2_en_o(fmc_m2_en_o), + .adc_m2_ia_dat_i(adc_m2_ia_dat_i), + .adc_m2_ib_dat_i(adc_m2_ib_dat_i), + .adc_m2_vbus_dat_i(adc_m2_vbus_dat_i), + .gpo_o(gpo), + .pwm_m1_ah_o(pwm_m1_ah_o), + .pwm_m1_al_o(pwm_m1_al_o), + .pwm_m1_bh_o(pwm_m1_bh_o), + .pwm_m1_bl_o(pwm_m1_bl_o), + .pwm_m1_ch_o(pwm_m1_ch_o), + .pwm_m1_cl_o(pwm_m1_cl_o), + .pwm_m2_ah_o(pwm_m2_ah_o), + .pwm_m2_al_o(pwm_m2_al_o), + .pwm_m2_bh_o(pwm_m2_bh_o), + .pwm_m2_bl_o(pwm_m2_bl_o), + .pwm_m2_ch_o(pwm_m2_ch_o), + .pwm_m2_cl_o(pwm_m2_cl_o), +/* .Vaux0_v_n(vauxn0), + .Vaux0_v_p(vauxp0), + .Vaux8_v_n(vauxn8), + .Vaux8_v_p(vauxp8), + .muxaddr_out(muxaddr_out),*/ + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_I (iic_mux_scl_i_s), + .iic_mux_scl_O (iic_mux_scl_o_s), + .iic_mux_scl_T (iic_mux_scl_t_s), + .iic_mux_sda_I (iic_mux_sda_i_s), + .iic_mux_sda_O (iic_mux_sda_o_s), + .iic_mux_sda_T (iic_mux_sda_t_s), + .ps_intr_10 (ps_intrs[10]), + .ps_intr_11 (ps_intrs[11]), + .ps_intr_12 (ps_intrs[12]), + .ps_intr_13 (ps_intrs[13]), + .ps_intr_0 (ps_intrs[0]), + .ps_intr_1 (ps_intrs[1]), + .ps_intr_2 (ps_intrs[2]), + .ps_intr_3 (ps_intrs[3]), + .ps_intr_4 (ps_intrs[4]), + .ps_intr_5 (ps_intrs[5]), + .ps_intr_6 (ps_intrs[6]), + .ps_intr_7 (ps_intrs[7]), + .ps_intr_8 (ps_intrs[8]), + .ps_intr_9 (ps_intrs[9]), + .iic_fmc_intr(ps_intrs[13]), + .iic_ee2_intr(ps_intrs[12]), + .motcon2_s_d1_intr(ps_intrs[11]), + .motcon2_c_m1_intr(ps_intrs[10]), + .motcon2_ctrl_m1_intr(ps_intrs[9]), + .motcon2_s_d2_intr(ps_intrs[8]), + .motcon2_c_m2_intr(ps_intrs[7]), + .motcon2_ctrl_m2_intr(ps_intrs[6]), + .iic_ee2_scl_io(iic_ee2_scl_io), + .iic_ee2_sda_io(iic_ee2_sda_io), + .spi_csn_i (1'b1), + .spi_csn_o (fmc_spi1_sel1_rdc), + .spi_miso_i (fmc_spi1_miso), + .spi_mosi_i (1'b0), + .spi_mosi_o (fmc_spi1_mosi), + .spi_sclk_i (1'b0), + .spi_sclk_o (fmc_spi1_sck), + .refclk(refclk), + .refclk_rst(refclk_rst), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif)); + +endmodule + +// *************************************************************************** +// *************************************************************************** From 6cd7c51f607a4d80fce52d83d4b5e04e0793b01d Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 20 Feb 2015 16:15:41 +0200 Subject: [PATCH 12/91] removed motcon1_fmc project, as the new motor control cores are not backward compatible --- .../motcon1_fmc/common/motcon1_fmc_bd.tcl | 450 ------------------ projects/motcon1_fmc/zed/system_bd.tcl | 5 - projects/motcon1_fmc/zed/system_constr.xdc | 86 ---- projects/motcon1_fmc/zed/system_project.tcl | 14 - projects/motcon1_fmc/zed/system_top.v | 341 ------------- 5 files changed, 896 deletions(-) delete mode 100644 projects/motcon1_fmc/common/motcon1_fmc_bd.tcl delete mode 100644 projects/motcon1_fmc/zed/system_bd.tcl delete mode 100644 projects/motcon1_fmc/zed/system_constr.xdc delete mode 100644 projects/motcon1_fmc/zed/system_project.tcl delete mode 100644 projects/motcon1_fmc/zed/system_top.v diff --git a/projects/motcon1_fmc/common/motcon1_fmc_bd.tcl b/projects/motcon1_fmc/common/motcon1_fmc_bd.tcl deleted file mode 100644 index e3003e052..000000000 --- a/projects/motcon1_fmc/common/motcon1_fmc_bd.tcl +++ /dev/null @@ -1,450 +0,0 @@ - - # motor control - - # position detection interface - - set position_i [ create_bd_port -dir I -from 2 -to 0 position_i ] - - # current monitor 1 interface - - set adc_ia_dat_i [ create_bd_port -dir I adc_ia_dat_i ] - set adc_ib_dat_i [ create_bd_port -dir I adc_ib_dat_i ] - set adc_it_dat_i [ create_bd_port -dir I adc_it_dat_i ] - set adc_vbus_dat_i [ create_bd_port -dir I adc_vbus_dat_i ] - set adc_ia_clk_o [ create_bd_port -dir O adc_ia_clk_o ] - set adc_ib_clk_o [ create_bd_port -dir O adc_ib_clk_o ] - set adc_it_clk_o [ create_bd_port -dir O adc_it_clk_o ] - set adc_vbus_clk_o [ create_bd_port -dir O adc_vbus_clk_o ] - - # cuurrent monitor 2 interface - - set adc_ia_dat_d_i [ create_bd_port -dir I adc_ia_dat_d_i ] - set adc_ib_dat_d_i [ create_bd_port -dir I adc_ib_dat_d_i ] - set adc_it_dat_d_i [ create_bd_port -dir I adc_it_dat_d_i ] - set adc_ia_clk_d_o [ create_bd_port -dir O adc_ia_clk_d_o ] - set adc_ib_clk_d_o [ create_bd_port -dir O adc_ib_clk_d_o ] - set adc_it_clk_d_o [ create_bd_port -dir O adc_it_clk_d_o ] - - # motor control interface - - set fmc_m1_fault_i [ create_bd_port -dir I fmc_m1_fault_i ] - set fmc_m1_en_o [ create_bd_port -dir O fmc_m1_en_o ] - - set pwm_al_o [ create_bd_port -dir O pwm_al_o] - set pwm_ah_o [ create_bd_port -dir O pwm_ah_o] - set pwm_cl_o [ create_bd_port -dir O pwm_cl_o] - set pwm_ch_o [ create_bd_port -dir O pwm_ch_o] - set pwm_bl_o [ create_bd_port -dir O pwm_bl_o] - set pwm_bh_o [ create_bd_port -dir O pwm_bh_o] - - # gpo interface - - set gpo_o [ create_bd_port -dir O -from 7 -to 0 gpo_o ] - - # interrupts - - set motcon1_c_m_1_irq [create_bd_port -dir O motcon1_c_m_1_irq] - set motcon1_c_m_2_irq [create_bd_port -dir O motcon1_c_m_2_irq] - set motcon1_s_d_irq [create_bd_port -dir O motcon1_s_d_irq] - set motcon1_ctrl_irq [create_bd_port -dir O motcon1_ctrl_irq] - - # xadc interface - - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vp_Vn - - #set muxaddr_out [ create_bd_port -dir O -from 4 -to 0 muxaddr_out ] - - # additions to default configuration - - set_property -dict [list CONFIG.NUM_MI {17}] $axi_cpu_interconnect - set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1} ] $sys_ps7 - set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1} ] $sys_ps7 - - # current monitor 1 peripherals - - set axi_mc_current_monitor_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_1 ] - - set axi_current_monitor_1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_1_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_1_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_1_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_1_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_1_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_1_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_1_dma - - # current monitor 2 peripherals - - set axi_mc_current_monitor_2 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_current_monitor:1.0 axi_mc_current_monitor_2 ] - - set axi_current_monitor_2_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_current_monitor_2_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_current_monitor_2_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_current_monitor_2_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_current_monitor_2_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_current_monitor_2_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_current_monitor_2_dma - set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_current_monitor_2_dma - - # speed detector - - set axi_mc_speed_1 [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_speed:1.0 axi_mc_speed_1 ] - - set axi_speed_detector_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_speed_detector_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_speed_detector_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_speed_detector_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_speed_detector_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_speed_detector_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_speed_detector_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {32}] $axi_speed_detector_dma - - # controller - - set axi_mc_controller [ create_bd_cell -type ip -vlnv analog.com:user:axi_mc_controller:1.0 axi_mc_controller ] - - set foc_controller [ create_bd_cell -type ip -vlnv analog.com:user:controllerperipheralhdladi_pcore:1.0 foc_controller ] - - set axi_controller_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_controller_dma] - set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_controller_dma - set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_controller_dma - set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_controller_dma - set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_controller_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_controller_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {256}] $axi_controller_dma - - # controller ILA - set ila_controller [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:4.0 ila_controller ] - set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_controller - set_property -dict [ list CONFIG.C_ADV_TRIGGER {true} ] $ila_controller - set_property -dict [ list CONFIG.C_DATA_DEPTH {8192} ] $ila_controller - set_property -dict [ list CONFIG.C_EN_STRG_QUAL {1} ] $ila_controller - set_property -dict [ list CONFIG.C_NUM_OF_PROBES {10} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE0_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE1_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE2_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE3_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE4_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE5_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE6_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE7_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE8_WIDTH {32} ] $ila_controller - set_property -dict [ list CONFIG.C_PROBE9_WIDTH {1} ] $ila_controller - set_property -dict [ list CONFIG.C_TRIGIN_EN {false} ] $ila_controller - - #adc_pack - set util_adc_pack_0 [ create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack_0 ] - set_property -dict [ list CONFIG.DATA_WIDTH {32} ] $util_adc_pack_0 - - # slice0 - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - set_property -dict [ list CONFIG.DIN_FROM {1} CONFIG.DIN_TO {1} CONFIG.DIN_WIDTH {3} ] $xlslice_0 - - # slice1 - set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] - set_property -dict [ list CONFIG.DIN_FROM {2} CONFIG.DIN_TO {2} CONFIG.DIN_WIDTH {3} ] $xlslice_1 - - # slice2 - set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] - set_property -dict [ list CONFIG.DIN_FROM {0} CONFIG.DIN_TO {0} CONFIG.DIN_WIDTH {3} ] $xlslice_2 - - # xadc - -# set xadc_wiz_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_wiz_1 ] -# set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_wiz_1 -# set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_wiz_1 -# set_property -dict [list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0}] $xadc_wiz_1 - - # additional interconnect - - set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ] - set_property -dict [ list CONFIG.NUM_SI {4} CONFIG.NUM_MI {1} ] $axi_mem_interconnect - - # connections - - # position - - connect_bd_net -net position_i_1 [get_bd_ports position_i] [get_bd_pins axi_mc_speed_1/position_i] - connect_bd_net -net position_i_1 [get_bd_pins axi_mc_speed_1/bemf_i] - - # current monitor 1 - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/ref_clk] $sys_100m_clk_source - - connect_bd_net -net adc_ia_dat_i_1 [get_bd_ports adc_ia_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ia_dat_i] - connect_bd_net -net adc_ib_dat_i_1 [get_bd_ports adc_ib_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_ib_dat_i] - connect_bd_net -net adc_it_dat_i_1 [get_bd_ports adc_it_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_it_dat_i] - connect_bd_net -net adc_vbus_dat_i_1 [get_bd_ports adc_vbus_dat_i] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_dat_i] - - connect_bd_net -net axi_mc_current_monitor_1_adc_ia_clk_o [get_bd_ports adc_ia_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ia_clk_o] - connect_bd_net -net axi_mc_current_monitor_1_adc_ib_clk_o [get_bd_ports adc_ib_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_ib_clk_o] - connect_bd_net -net axi_mc_current_monitor_1_adc_it_clk_o [get_bd_ports adc_it_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_it_clk_o] - connect_bd_net -net axi_mc_current_monitor_1_adc_vbus_clk_o [get_bd_ports adc_vbus_clk_o] [get_bd_pins axi_mc_current_monitor_1/adc_vbus_clk_o] - - connect_bd_net -net axi_mc_current_monitor_1_adc_clk [get_bd_pins axi_mc_current_monitor_1/adc_clk_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_clk] - connect_bd_net -net axi_mc_current_monitor_1_adc_dwr [get_bd_pins axi_mc_current_monitor_1/adc_dwr_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_en] - connect_bd_net -net axi_mc_current_monitor_1_adc_ddata [get_bd_pins axi_mc_current_monitor_1/adc_ddata_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_din] - connect_bd_net -net axi_mc_current_monitor_1_adc_dsync [get_bd_pins axi_mc_current_monitor_1/adc_dsync_o] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_sync] - connect_bd_net -net axi_mc_current_monitor_1_adc_dovf [get_bd_pins axi_mc_current_monitor_1/adc_dovf_i] [get_bd_pins axi_current_monitor_1_dma/fifo_wr_overflow] - - connect_bd_net -net axi_mc_current_monitor_1_ia_o [get_bd_pins axi_mc_current_monitor_1/ia_o] [get_bd_pins foc_controller/adc_current1] - connect_bd_net -net axi_mc_current_monitor_1_ib_o [get_bd_pins axi_mc_current_monitor_1/ib_o] [get_bd_pins foc_controller/adc_current2] - connect_bd_net -net axi_mc_current_monitor_1_i_ready_o [get_bd_pins axi_mc_controller/ctrl_data_valid_i] [get_bd_pins axi_mc_current_monitor_1/i_ready_o] - - # interrupt - - connect_bd_net -net axi_current_monitor_1_dma_irq [get_bd_pins axi_current_monitor_1_dma/irq] [get_bd_ports motcon1_c_m_1_irq] - - # current monitor 2 - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/ref_clk] $sys_100m_clk_source - - connect_bd_net -net adc_ia_dat_d_i [get_bd_ports adc_ia_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_ia_dat_i] - connect_bd_net -net axi_mc_current_monitor_2_adc_ia_clk_o [get_bd_ports adc_ia_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_ia_clk_o] - connect_bd_net -net adc_ib_dat_d_i [get_bd_ports adc_ib_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_ib_dat_i] - connect_bd_net -net axi_mc_current_monitor_2_adc_ib_clk_o [get_bd_ports adc_ib_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_ib_clk_o] - connect_bd_net -net adc_it_dat_d_i [get_bd_ports adc_it_dat_d_i] [get_bd_pins axi_mc_current_monitor_2/adc_it_dat_i] - connect_bd_net -net axi_mc_current_monitor_2_adc_it_clk_o [get_bd_ports adc_it_clk_d_o] [get_bd_pins axi_mc_current_monitor_2/adc_it_clk_o] - - connect_bd_net -net axi_mc_current_monitor_2_adc_clk [get_bd_pins axi_mc_current_monitor_2/adc_clk_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_clk] - connect_bd_net -net axi_mc_current_monitor_2_adc_dwr [get_bd_pins axi_mc_current_monitor_2/adc_dwr_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_en] - connect_bd_net -net axi_mc_current_monitor_2_adc_ddata [get_bd_pins axi_mc_current_monitor_2/adc_ddata_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_din] - connect_bd_net -net axi_mc_current_monitor_2_adc_dsync [get_bd_pins axi_mc_current_monitor_2/adc_dsync_o] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_sync] - connect_bd_net -net axi_mc_current_monitor_2_adc_dovf [get_bd_pins axi_mc_current_monitor_2/adc_dovf_i] [get_bd_pins axi_current_monitor_2_dma/fifo_wr_overflow] - - #interrupt - - connect_bd_net -net axi_current_monitor_2_dma_irq [get_bd_pins axi_current_monitor_2_dma/irq] [get_bd_ports motcon1_c_m_2_irq] - - # speed detector - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/ref_clk] $sys_100m_clk_source - - connect_bd_net -net axi_mc_speed_1_position_o [get_bd_pins axi_mc_speed_1/position_o] [get_bd_pins axi_mc_controller/position_i] - - connect_bd_net -net speed_detector_adc_clk [get_bd_pins axi_mc_speed_1/adc_clk_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_clk] - connect_bd_net -net speed_detector_adc_dwr [get_bd_pins axi_mc_speed_1/adc_dwr_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_en] - connect_bd_net -net speed_detector_adc_ddata [get_bd_pins axi_mc_speed_1/adc_ddata_o] [get_bd_pins axi_speed_detector_dma/fifo_wr_din] - connect_bd_net -net speed_detector_adc_dovf [get_bd_pins axi_mc_speed_1/adc_dovf_i] [get_bd_pins axi_speed_detector_dma/fifo_wr_overflow] - - # interrupt - - connect_bd_net -net axi_speed_detector_dma_irq [get_bd_pins axi_speed_detector_dma/irq] [get_bd_ports motcon1_s_d_irq] - - # controller - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/ref_clk] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/ctrl_data_clk] $sys_100m_clk_source - - connect_bd_net -net axi_mc_controller_fmc_m1_en_o [get_bd_ports fmc_m1_en_o] [get_bd_pins axi_mc_controller/fmc_m1_en_o] - connect_bd_net -net axi_mc_controller_pwm_al_o [get_bd_ports pwm_al_o] [get_bd_pins axi_mc_controller/pwm_al_o] - connect_bd_net -net axi_mc_controller_pwm_ah_o [get_bd_ports pwm_ah_o] [get_bd_pins axi_mc_controller/pwm_ah_o] - connect_bd_net -net axi_mc_controller_pwm_cl_o [get_bd_ports pwm_cl_o] [get_bd_pins axi_mc_controller/pwm_cl_o] - connect_bd_net -net axi_mc_controller_pwm_ch_o [get_bd_ports pwm_ch_o] [get_bd_pins axi_mc_controller/pwm_ch_o] - connect_bd_net -net axi_mc_controller_pwm_bl_o [get_bd_ports pwm_bl_o] [get_bd_pins axi_mc_controller/pwm_bl_o] - connect_bd_net -net axi_mc_controller_pwm_bh_o [get_bd_ports pwm_bh_o] [get_bd_pins axi_mc_controller/pwm_bh_o] - connect_bd_net -net axi_mc_controller_gpo_o [get_bd_ports gpo_o] [get_bd_pins axi_mc_controller/gpo_o] - connect_bd_net -net axi_mc_controller_sensors_o [get_bd_pins axi_mc_controller/sensors_o] [get_bd_pins axi_mc_speed_1/hall_bemf_i] - connect_bd_net -net axi_mc_controller_fault [get_bd_pins /axi_mc_controller/fmc_m1_fault_i] [get_bd_ports /fmc_m1_fault_i] - - connect_bd_net -net axi_mc_controller_adc_clk_o [get_bd_pins axi_mc_controller/adc_clk_o] [get_bd_pins util_adc_pack_0/clk] - connect_bd_net -net axi_mc_controller_adc_data_c0 [get_bd_pins axi_mc_controller/adc_data_c0] [get_bd_pins util_adc_pack_0/chan_data_0] - connect_bd_net -net axi_mc_controller_adc_data_c1 [get_bd_pins axi_mc_controller/adc_data_c1] [get_bd_pins util_adc_pack_0/chan_data_1] - connect_bd_net -net axi_mc_controller_adc_data_c2 [get_bd_pins axi_mc_controller/adc_data_c2] [get_bd_pins util_adc_pack_0/chan_data_2] - connect_bd_net -net axi_mc_controller_adc_data_c3 [get_bd_pins axi_mc_controller/adc_data_c3] [get_bd_pins util_adc_pack_0/chan_data_3] - connect_bd_net -net axi_mc_controller_adc_data_c4 [get_bd_pins axi_mc_controller/adc_data_c4] [get_bd_pins util_adc_pack_0/chan_data_4] - connect_bd_net -net axi_mc_controller_adc_data_c5 [get_bd_pins axi_mc_controller/adc_data_c5] [get_bd_pins util_adc_pack_0/chan_data_5] - connect_bd_net -net axi_mc_controller_adc_data_c6 [get_bd_pins axi_mc_controller/adc_data_c6] [get_bd_pins util_adc_pack_0/chan_data_6] - connect_bd_net -net axi_mc_controller_adc_data_c7 [get_bd_pins axi_mc_controller/adc_data_c7] [get_bd_pins util_adc_pack_0/chan_data_7] - connect_bd_net -net axi_mc_controller_adc_enable_c0 [get_bd_pins axi_mc_controller/adc_enable_c0] [get_bd_pins util_adc_pack_0/chan_enable_0] - connect_bd_net -net axi_mc_controller_adc_enable_c1 [get_bd_pins axi_mc_controller/adc_enable_c1] [get_bd_pins util_adc_pack_0/chan_enable_1] - connect_bd_net -net axi_mc_controller_adc_enable_c2 [get_bd_pins axi_mc_controller/adc_enable_c2] [get_bd_pins util_adc_pack_0/chan_enable_2] - connect_bd_net -net axi_mc_controller_adc_enable_c3 [get_bd_pins axi_mc_controller/adc_enable_c3] [get_bd_pins util_adc_pack_0/chan_enable_3] - connect_bd_net -net axi_mc_controller_adc_enable_c4 [get_bd_pins axi_mc_controller/adc_enable_c4] [get_bd_pins util_adc_pack_0/chan_enable_4] - connect_bd_net -net axi_mc_controller_adc_enable_c5 [get_bd_pins axi_mc_controller/adc_enable_c5] [get_bd_pins util_adc_pack_0/chan_enable_5] - connect_bd_net -net axi_mc_controller_adc_enable_c6 [get_bd_pins axi_mc_controller/adc_enable_c6] [get_bd_pins util_adc_pack_0/chan_enable_6] - connect_bd_net -net axi_mc_controller_adc_enable_c7 [get_bd_pins axi_mc_controller/adc_enable_c7] [get_bd_pins util_adc_pack_0/chan_enable_7] - connect_bd_net -net axi_mc_controller_adc_valid_c0 [get_bd_pins axi_mc_controller/adc_valid_c0] [get_bd_pins util_adc_pack_0/chan_valid_0] - connect_bd_net -net axi_mc_controller_adc_valid_c1 [get_bd_pins axi_mc_controller/adc_valid_c1] [get_bd_pins util_adc_pack_0/chan_valid_1] - connect_bd_net -net axi_mc_controller_adc_valid_c2 [get_bd_pins axi_mc_controller/adc_valid_c2] [get_bd_pins util_adc_pack_0/chan_valid_2] - connect_bd_net -net axi_mc_controller_adc_valid_c3 [get_bd_pins axi_mc_controller/adc_valid_c3] [get_bd_pins util_adc_pack_0/chan_valid_3] - connect_bd_net -net axi_mc_controller_adc_valid_c4 [get_bd_pins axi_mc_controller/adc_valid_c4] [get_bd_pins util_adc_pack_0/chan_valid_4] - connect_bd_net -net axi_mc_controller_adc_valid_c5 [get_bd_pins axi_mc_controller/adc_valid_c5] [get_bd_pins util_adc_pack_0/chan_valid_5] - connect_bd_net -net axi_mc_controller_adc_valid_c6 [get_bd_pins axi_mc_controller/adc_valid_c6] [get_bd_pins util_adc_pack_0/chan_valid_6] - connect_bd_net -net axi_mc_controller_adc_valid_c7 [get_bd_pins axi_mc_controller/adc_valid_c7] [get_bd_pins util_adc_pack_0/chan_valid_7] - - connect_bd_net -net axi_mc_controller_adc_clk_o [get_bd_pins axi_controller_dma/fifo_wr_clk] - connect_bd_net -net axi_mc_controller_adc_ddata [get_bd_pins axi_controller_dma/fifo_wr_din] [get_bd_pins util_adc_pack_0/ddata] - connect_bd_net -net axi_mc_controller_adc_dovf [get_bd_pins axi_controller_dma/fifo_wr_overflow] [get_bd_pins axi_mc_controller/adc_dovf_i] - connect_bd_net -net axi_mc_controller_adc_dwr [get_bd_pins axi_controller_dma/fifo_wr_en] [get_bd_pins util_adc_pack_0/dvalid] - connect_bd_net -net util_adc_pack_0_dsync [get_bd_pins axi_controller_dma/fifo_wr_sync] [get_bd_pins util_adc_pack_0/dsync] - - #foc_controller - connect_bd_net -net sys_100m_clk [get_bd_pins foc_controller/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_ps7_FCLK_CLK2 [get_bd_pins foc_controller/IPCORE_CLK] [get_bd_pins sys_ps7/FCLK_CLK2] - - connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/s_axi_aresetn] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins foc_controller/IPCORE_RESETN] $sys_100m_resetn_source - - connect_bd_net -net foc_controller_mon_d_current [get_bd_pins axi_mc_controller/ctrl_data6_i] - connect_bd_net -net foc_controller_mon_d_current [get_bd_pins foc_controller/mon_d_current] - - connect_bd_net -net foc_controller_pwm_a [get_bd_pins axi_mc_controller/pwm_a_i] [get_bd_pins foc_controller/pwm_a] - connect_bd_net -net foc_controller_pwm_b [get_bd_pins axi_mc_controller/pwm_b_i] [get_bd_pins foc_controller/pwm_b] - connect_bd_net -net foc_controller_pwm_c [get_bd_pins axi_mc_controller/pwm_c_i] [get_bd_pins foc_controller/pwm_c] - connect_bd_net -net xlslice_0_Dout [get_bd_pins foc_controller/encoder_a] [get_bd_pins xlslice_0/Dout] - connect_bd_net -net xlslice_1_Dout [get_bd_pins foc_controller/encoder_b] [get_bd_pins xlslice_1/Dout] - connect_bd_net -net xlslice_2_Dout [get_bd_pins foc_controller/encoder_index] [get_bd_pins xlslice_2/Dout] - connect_bd_net -net position_i_1 [get_bd_pins xlslice_1/Din] - connect_bd_net -net position_i_1 [get_bd_pins xlslice_0/Din] - connect_bd_net -net position_i_1 [get_bd_pins xlslice_2/Din] - - #ILA - connect_bd_net -net sys_100m_clk [get_bd_pins ila_controller/clk] $sys_100m_clk_source - connect_bd_net -net foc_controller_mon_phase_voltage_a [get_bd_pins axi_mc_controller/ctrl_data0_i] [get_bd_pins foc_controller/mon_phase_voltage_a] [get_bd_pins ila_controller/probe0] - connect_bd_net -net foc_controller_mon_phase_voltage_b [get_bd_pins axi_mc_controller/ctrl_data1_i] [get_bd_pins foc_controller/mon_phase_voltage_b] [get_bd_pins ila_controller/probe1] - connect_bd_net -net foc_controller_mon_phase_current_a [get_bd_pins axi_mc_controller/ctrl_data2_i] [get_bd_pins foc_controller/mon_phase_current_a] [get_bd_pins ila_controller/probe2] - connect_bd_net -net foc_controller_mon_phase_current_b [get_bd_pins axi_mc_controller/ctrl_data3_i] [get_bd_pins foc_controller/mon_phase_current_b] [get_bd_pins ila_controller/probe3] - connect_bd_net -net foc_controller_mon_rotor_position [get_bd_pins foc_controller/mon_rotor_position] [get_bd_pins ila_controller/probe4] - connect_bd_net -net foc_controller_mon_electrical_position [get_bd_pins axi_mc_controller/ctrl_data4_i] [get_bd_pins foc_controller/mon_electrical_position] [get_bd_pins ila_controller/probe5] - connect_bd_net -net foc_controller_mon_rotor_velocity [get_bd_pins axi_mc_controller/ctrl_data5_i] [get_bd_pins foc_controller/mon_rotor_velocity] [get_bd_pins ila_controller/probe6] - connect_bd_net -net foc_controller_mon_d_current [get_bd_pins ila_controller/probe7] - connect_bd_net -net foc_controller_mon_q_current [get_bd_pins axi_mc_controller/ctrl_data7_i] [get_bd_pins foc_controller/mon_q_current] [get_bd_pins ila_controller/probe8] - connect_bd_net -net axi_mc_current_monitor_1_i_ready_o [get_bd_pins ila_controller/probe9] - - # interrupt - - connect_bd_net -net axi_controller_dma_irq [get_bd_pins axi_controller_dma/irq] [get_bd_ports motcon1_ctrl_irq] - - # xadc - -# connect_bd_net -net sys_100m_clk [get_bd_pins xadc_wiz_1/s_axi_aclk] $sys_100m_clk_source -# connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_wiz_1/s_axi_aresetn] $sys_100m_resetn_source - -# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vp_Vn] [get_bd_intf_ports Vp_Vn] -# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux0] [get_bd_intf_ports Vaux0] -# connect_bd_intf_net [get_bd_intf_pins xadc_wiz_1/Vaux8] [get_bd_intf_ports Vaux8] -# connect_bd_net -net xadc_wiz_1_muxaddr_out [get_bd_ports muxaddr_out] [get_bd_pins xadc_wiz_1/muxaddr_out] - - # interconnect (cpu) - - connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_mc_current_monitor_1/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins axi_mc_speed_1/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins axi_mc_controller/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins axi_mc_current_monitor_2/s_axi] -# connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins xadc_wiz_1/s_axi_lite] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m12_axi [get_bd_intf_pins axi_cpu_interconnect/M12_AXI] [get_bd_intf_pins axi_speed_detector_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m13_axi [get_bd_intf_pins axi_cpu_interconnect/M13_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m14_axi [get_bd_intf_pins axi_cpu_interconnect/M14_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m15_axi [get_bd_intf_pins axi_cpu_interconnect/M15_AXI] [get_bd_intf_pins axi_controller_dma/s_axi] - connect_bd_intf_net -intf_net axi_cpu_interconnect_m16_axi [get_bd_intf_pins axi_cpu_interconnect/M16_AXI] [get_bd_intf_pins foc_controller/s_axi] - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M09_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M10_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M11_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M12_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M13_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M14_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M15_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M16_ACLK] $sys_100m_clk_source - - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M07_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M08_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M10_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M11_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M12_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M13_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M16_ARESETN] $sys_100m_resetn_source - - #inteconnects (current monitor 1) - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_1/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_1/s_axi_aresetn] $sys_100m_resetn_source - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/s_axi_aresetn] $sys_100m_resetn_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_1_dma/m_dest_axi_aresetn] $sys_100m_resetn_source - - connect_bd_intf_net -intf_net axi_mem_interconnect_s01_axi [get_bd_intf_pins axi_mem_interconnect/S01_AXI] [get_bd_intf_pins axi_current_monitor_1_dma/m_dest_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S01_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S01_ARESETN] $sys_100m_resetn_source - - #interconnect (current monitor 2) - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_current_monitor_2/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_current_monitor_2/s_axi_aresetn] $sys_100m_resetn_source - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/s_axi_aresetn] $sys_100m_resetn_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_current_monitor_2_dma/m_dest_axi_aresetn] $sys_100m_resetn_source - - connect_bd_intf_net -intf_net axi_mem_interconnect_s02_axi [get_bd_intf_pins axi_mem_interconnect/S02_AXI] [get_bd_intf_pins axi_current_monitor_2_dma/m_dest_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S02_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S02_ARESETN] $sys_100m_resetn_source - - # interconnect (speed detector) - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_speed_1/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_speed_1/s_axi_aresetn] $sys_100m_resetn_source - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/m_dest_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/s_axi_aresetn] $sys_100m_resetn_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_speed_detector_dma/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_speed_detector_dma/m_dest_axi_aresetn] $sys_100m_resetn_source - - connect_bd_intf_net -intf_net axi_mem_interconnect_s00_axi [get_bd_intf_pins axi_mem_interconnect/S00_AXI] [get_bd_intf_pins axi_speed_detector_dma/m_dest_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S00_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S00_ARESETN] $sys_100m_resetn_source - - # interconnect (controller) - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mc_controller/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mc_controller/s_axi_aresetn] $sys_100m_resetn_source - - connect_bd_net -net sys_100m_clk [get_bd_pins axi_controller_dma/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_controller_dma/s_axi_aresetn] $sys_100m_resetn_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_controller_dma/m_dest_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_controller_dma/m_dest_axi_aresetn] $sys_100m_resetn_source - - connect_bd_intf_net -intf_net axi_mem_interconnect_s03_axi [get_bd_intf_pins axi_mem_interconnect/S03_AXI] [get_bd_intf_pins axi_controller_dma/m_dest_axi] - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/S03_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/S03_ARESETN] $sys_100m_resetn_source - - # interconnect (dmas) - - connect_bd_net -net sys_100m_clk [get_bd_pins sys_ps7/S_AXI_HP1_ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/ACLK] $sys_100m_clk_source - connect_bd_net -net sys_100m_clk [get_bd_pins axi_mem_interconnect/M00_ACLK] $sys_100m_clk_source - - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/ARESETN] $sys_100m_resetn_source - connect_bd_net -net sys_100m_resetn [get_bd_pins axi_mem_interconnect/M00_ARESETN] $sys_100m_resetn_source - - connect_bd_intf_net -intf_net axi_mem_interconnect_m00_axi [get_bd_intf_pins axi_mem_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP1] - - # address map - - create_bd_addr_seg -range 0x10000 -offset 0x40400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_1_dma/s_axi/axi_lite] SEG_data_c_m_1_dma - create_bd_addr_seg -range 0x10000 -offset 0x40410000 $sys_addr_cntrl_space [get_bd_addr_segs axi_speed_detector_dma/s_axi/axi_lite] SEG_data_s_d_dma - create_bd_addr_seg -range 0x10000 -offset 0x40420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_controller_dma/s_axi/axi_lite] SEG_data_t_c_dma - create_bd_addr_seg -range 0x10000 -offset 0x40430000 $sys_addr_cntrl_space [get_bd_addr_segs axi_current_monitor_2_dma/s_axi/axi_lite] SEG_data_c_m_2_dma - create_bd_addr_seg -range 0x10000 -offset 0x40500000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_1/s_axi/axi_lite] SEG_data_c_m_1 - create_bd_addr_seg -range 0x10000 -offset 0x40510000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_speed_1/s_axi/axi_lite] SEG_data_s_d - create_bd_addr_seg -range 0x10000 -offset 0x40520000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_controller/s_axi/axi_lite] SEG_data_t_c - create_bd_addr_seg -range 0x10000 -offset 0x40530000 $sys_addr_cntrl_space [get_bd_addr_segs axi_mc_current_monitor_2/s_axi/axi_lite] SEG_data_c_m_2 -# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_wiz_1/s_axi_lite/Reg] SEG_data_xadc - create_bd_addr_seg -range 0x4000000 -offset 0x7C000000 $sys_addr_cntrl_space [get_bd_addr_segs foc_controller/s_axi/axi_lite] SEG_foc_controller_f_c - - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_speed_detector_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_controller_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm - create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_current_monitor_2_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm diff --git a/projects/motcon1_fmc/zed/system_bd.tcl b/projects/motcon1_fmc/zed/system_bd.tcl deleted file mode 100644 index 5aa5d84ab..000000000 --- a/projects/motcon1_fmc/zed/system_bd.tcl +++ /dev/null @@ -1,5 +0,0 @@ - - - source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl - source ../common/motcon1_fmc_bd.tcl - diff --git a/projects/motcon1_fmc/zed/system_constr.xdc b/projects/motcon1_fmc/zed/system_constr.xdc deleted file mode 100644 index 131902b29..000000000 --- a/projects/motcon1_fmc/zed/system_constr.xdc +++ /dev/null @@ -1,86 +0,0 @@ -# Motor Control - -set_property PACKAGE_PIN J16 [get_ports {position_i[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {position_i[0]}] -set_property PACKAGE_PIN J17 [get_ports {position_i[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {position_i[1]}] -set_property PACKAGE_PIN G15 [get_ports {position_i[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {position_i[2]}] - -set_property PACKAGE_PIN A16 [get_ports pwm_ah_o] -set_property IOSTANDARD LVCMOS25 [get_ports pwm_ah_o] -set_property PACKAGE_PIN A17 [get_ports pwm_al_o] -set_property IOSTANDARD LVCMOS25 [get_ports pwm_al_o] -set_property PACKAGE_PIN C15 [get_ports pwm_bh_o] -set_property IOSTANDARD LVCMOS25 [get_ports pwm_bh_o] -set_property PACKAGE_PIN B15 [get_ports pwm_bl_o] -set_property IOSTANDARD LVCMOS25 [get_ports pwm_bl_o] -set_property PACKAGE_PIN A21 [get_ports pwm_ch_o] -set_property IOSTANDARD LVCMOS25 [get_ports pwm_ch_o] -set_property PACKAGE_PIN A22 [get_ports pwm_cl_o] -set_property IOSTANDARD LVCMOS25 [get_ports pwm_cl_o] -set_property PACKAGE_PIN L21 [get_ports fmc_m1_en_o] -set_property IOSTANDARD LVCMOS25 [get_ports fmc_m1_en_o] -set_property PACKAGE_PIN L22 [get_ports fmc_m1_fault_i] -set_property IOSTANDARD LVCMOS25 [get_ports fmc_m1_fault_i] - -set_property PACKAGE_PIN T16 [get_ports adc_ia_dat_i] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_dat_i] -set_property PACKAGE_PIN T17 [get_ports adc_ib_dat_i] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_dat_i] -set_property PACKAGE_PIN N17 [get_ports adc_it_dat_i] -set_property IOSTANDARD LVCMOS25 [get_ports adc_it_dat_i] -set_property PACKAGE_PIN N18 [get_ports adc_vbus_dat_i] -set_property IOSTANDARD LVCMOS25 [get_ports adc_vbus_dat_i] - -set_property PACKAGE_PIN P17 [get_ports adc_ia_clk_o] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_clk_o] -set_property PACKAGE_PIN P18 [get_ports adc_ib_clk_o] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_clk_o] -set_property PACKAGE_PIN M21 [get_ports adc_it_clk_o] -set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_o] -set_property PACKAGE_PIN M22 [get_ports adc_vbus_clk_o] -set_property IOSTANDARD LVCMOS25 [get_ports adc_vbus_clk_o] - -set_property PACKAGE_PIN A18 [get_ports {gpo_o[0]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[0]}] -set_property PACKAGE_PIN A19 [get_ports {gpo_o[1]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[1]}] -set_property PACKAGE_PIN R19 [get_ports {gpo_o[2]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[2]}] -set_property PACKAGE_PIN T19 [get_ports {gpo_o[3]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[3]}] -set_property PACKAGE_PIN D21 [get_ports {gpo_o[4]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[4]}] -set_property PACKAGE_PIN J22 [get_ports {gpo_o[5]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[5]}] -set_property PACKAGE_PIN G16 [get_ports {gpo_o[6]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[6]}] -set_property PACKAGE_PIN M19 [get_ports {gpo_o[7]}] -set_property IOSTANDARD LVCMOS25 [get_ports {gpo_o[7]}] - -set_property PACKAGE_PIN B17 [get_ports adc_ia_dat_d_i] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_dat_d_i] -set_property PACKAGE_PIN B21 [get_ports adc_ib_dat_d_i] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_dat_d_i] -set_property PACKAGE_PIN B22 [get_ports adc_it_dat_d_i] -set_property IOSTANDARD LVCMOS25 [get_ports adc_it_dat_d_i] - -set_property PACKAGE_PIN D20 [get_ports adc_ia_clk_d_o] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ia_clk_d_o] -set_property PACKAGE_PIN C20 [get_ports adc_ib_clk_d_o] -set_property IOSTANDARD LVCMOS25 [get_ports adc_ib_clk_d_o] -set_property PACKAGE_PIN E21 [get_ports adc_it_clk_d_o] -set_property IOSTANDARD LVCMOS25 [get_ports adc_it_clk_d_o] - - -#set_property PACKAGE_PIN H15 [get_ports {muxaddr_out[0]}] -#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[0]}] -#set_property PACKAGE_PIN R15 [get_ports {muxaddr_out[1]}] -#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[1]}] -#set_property PACKAGE_PIN K15 [get_ports {muxaddr_out[2]}] -#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[2]}] -#set_property PACKAGE_PIN J15 [get_ports {muxaddr_out[3]}] -#set_property IOSTANDARD LVCMOS25 [get_ports {muxaddr_out[3]}] - -set_false_path -through [get_pins {i_system_wrapper/system_i/foc_controller/inst*/*/*/*}] diff --git a/projects/motcon1_fmc/zed/system_project.tcl b/projects/motcon1_fmc/zed/system_project.tcl deleted file mode 100644 index dcbbc9420..000000000 --- a/projects/motcon1_fmc/zed/system_project.tcl +++ /dev/null @@ -1,14 +0,0 @@ - -source ../../scripts/adi_env.tcl -source $ad_hdl_dir/projects/scripts/adi_project.tcl - -adi_project_create motcon1_fmc_zed -adi_project_files motcon1_fmc_zed [list \ - "system_top.v" \ - "system_constr.xdc" \ - "$ad_hdl_dir/library/common/ad_iobuf.v" \ - "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] - -adi_project_run motcon1_fmc_zed - - diff --git a/projects/motcon1_fmc/zed/system_top.v b/projects/motcon1_fmc/zed/system_top.v deleted file mode 100644 index 5d38ff5ae..000000000 --- a/projects/motcon1_fmc/zed/system_top.v +++ /dev/null @@ -1,341 +0,0 @@ -// *************************************************************************** -// *************************************************************************** -// Copyright 2014(c) Analog Devices, Inc. -// -// All rights reserved. -// -// Redistribution and use in source and binary forms, with or without modification, -// are permitted provided that the following conditions are met: -// - Redistributions of source code must retain the above copyright -// notice, this list of conditions and the following disclaimer. -// - Redistributions in binary form must reproduce the above copyright -// notice, this list of conditions and the following disclaimer in -// the documentation and/or other materials provided with the -// distribution. -// - Neither the name of Analog Devices, Inc. nor the names of its -// contributors may be used to endorse or promote products derived -// from this software without specific prior written permission. -// - The use of this software may or may not infringe the patent rights -// of one or more patent holders. This license does not release you -// from the requirement that you obtain separate licenses from these -// patent holders to use this software. -// - Use of the software either in source or binary form, must be run -// on or directly connected to an Analog Devices Inc. component. -// -// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, -// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A -// PARTICULAR PURPOSE ARE DISCLAIMED. -// -// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY -// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR -// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, -// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF -// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** -// *************************************************************************** - -`timescale 1ns/100ps - -module system_top ( - - DDR_addr, - DDR_ba, - DDR_cas_n, - DDR_ck_n, - DDR_ck_p, - DDR_cke, - DDR_cs_n, - DDR_dm, - DDR_dq, - DDR_dqs_n, - DDR_dqs_p, - DDR_odt, - DDR_ras_n, - DDR_reset_n, - DDR_we_n, - - FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp, - FIXED_IO_mio, - FIXED_IO_ps_clk, - FIXED_IO_ps_porb, - FIXED_IO_ps_srstb, - - gpio_bd, - - hdmi_out_clk, - hdmi_vsync, - hdmi_hsync, - hdmi_data_e, - hdmi_data, - - adc_ia_clk_d_o, - adc_ia_clk_o, - adc_ia_dat_d_i, - adc_ia_dat_i, - adc_ib_clk_d_o, - adc_ib_clk_o, - adc_ib_dat_d_i, - adc_ib_dat_i, - adc_it_clk_d_o, - adc_it_clk_o, - adc_it_dat_d_i, - adc_it_dat_i, - adc_vbus_clk_o, - adc_vbus_dat_i, - fmc_m1_en_o, - fmc_m1_fault_i, - gpo_o, - position_i, - pwm_ah_o, - pwm_al_o, - pwm_bh_o, - pwm_bl_o, - pwm_ch_o, - pwm_cl_o, - - //vauxn0, - //vauxn8, - //vauxp0, - //vauxp8, - //vn_in, - //vp_in, - //muxaddr_out, - - i2s_mclk, - i2s_bclk, - i2s_lrclk, - i2s_sdata_out, - i2s_sdata_in, - - spdif, - - iic_scl, - iic_sda, - iic_mux_scl, - iic_mux_sda, - - otg_vbusoc); - - inout [14:0] DDR_addr; - inout [ 2:0] DDR_ba; - inout DDR_cas_n; - inout DDR_ck_n; - inout DDR_ck_p; - inout DDR_cke; - inout DDR_cs_n; - inout [ 3:0] DDR_dm; - inout [31:0] DDR_dq; - inout [ 3:0] DDR_dqs_n; - inout [ 3:0] DDR_dqs_p; - inout DDR_odt; - inout DDR_ras_n; - inout DDR_reset_n; - inout DDR_we_n; - - inout FIXED_IO_ddr_vrn; - inout FIXED_IO_ddr_vrp; - inout [53:0] FIXED_IO_mio; - inout FIXED_IO_ps_clk; - inout FIXED_IO_ps_porb; - inout FIXED_IO_ps_srstb; - - inout [31:0] gpio_bd; - - output hdmi_out_clk; - output hdmi_vsync; - output hdmi_hsync; - output hdmi_data_e; - output [15:0] hdmi_data; - - output adc_ia_clk_d_o; - output adc_ia_clk_o; - input adc_ia_dat_d_i; - input adc_ia_dat_i; - output adc_ib_clk_d_o; - output adc_ib_clk_o; - input adc_ib_dat_d_i; - input adc_ib_dat_i; - output adc_it_clk_d_o; - output adc_it_clk_o; - input adc_it_dat_d_i; - input adc_it_dat_i; - output adc_vbus_clk_o; - input adc_vbus_dat_i; - output fmc_m1_en_o; - input fmc_m1_fault_i; - output [7:0] gpo_o; - input [2:0] position_i; - output pwm_ah_o; - output pwm_al_o; - output pwm_bh_o; - output pwm_bl_o; - output pwm_ch_o; - output pwm_cl_o; - - //input vauxn0; - //input vauxn8; - //input vauxp0; - //input vauxp8; - //input vn_in; - //input vp_in; - //output [3:0] muxaddr_out; - - output spdif; - - output i2s_mclk; - output i2s_bclk; - output i2s_lrclk; - output i2s_sdata_out; - input i2s_sdata_in; - - - inout iic_scl; - inout iic_sda; - inout [ 1:0] iic_mux_scl; - inout [ 1:0] iic_mux_sda; - - input otg_vbusoc; - - // internal signals - - wire [31:0] gpio_i; - wire [31:0] gpio_o; - wire [31:0] gpio_t; - wire [ 1:0] iic_mux_scl_i_s; - wire [ 1:0] iic_mux_scl_o_s; - wire iic_mux_scl_t_s; - wire [ 1:0] iic_mux_sda_i_s; - wire [ 1:0] iic_mux_sda_o_s; - wire iic_mux_sda_t_s; - wire [15:0] ps_intrs; - - // instantiations - - ad_iobuf #( - .DATA_WIDTH(32)) - i_gpio_bd ( - .dt(gpio_t), - .di(gpio_o), - .do(gpio_i), - .dio(gpio_bd)); - - ad_iobuf #( - .DATA_WIDTH(2)) - i_iic_mux_scl ( - .dt({iic_mux_scl_t_s, iic_mux_scl_t_s}), - .di(iic_mux_scl_o_s), - .do(iic_mux_scl_i_s), - .dio(iic_mux_scl)); - - ad_iobuf #( - .DATA_WIDTH(2)) - i_iic_mux_sda ( - .dt({iic_mux_sda_t_s, iic_mux_sda_t_s}), - .di(iic_mux_sda_o_s), - .do(iic_mux_sda_i_s), - .dio(iic_mux_sda)); - - system_wrapper i_system_wrapper ( - .DDR_addr (DDR_addr), - .DDR_ba (DDR_ba), - .DDR_cas_n (DDR_cas_n), - .DDR_ck_n (DDR_ck_n), - .DDR_ck_p (DDR_ck_p), - .DDR_cke (DDR_cke), - .DDR_cs_n (DDR_cs_n), - .DDR_dm (DDR_dm), - .DDR_dq (DDR_dq), - .DDR_dqs_n (DDR_dqs_n), - .DDR_dqs_p (DDR_dqs_p), - .DDR_odt (DDR_odt), - .DDR_ras_n (DDR_ras_n), - .DDR_reset_n (DDR_reset_n), - .DDR_we_n (DDR_we_n), - .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), - .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), - .FIXED_IO_mio (FIXED_IO_mio), - .FIXED_IO_ps_clk (FIXED_IO_ps_clk), - .FIXED_IO_ps_porb (FIXED_IO_ps_porb), - .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), - .GPIO_I (gpio_i), - .GPIO_O (gpio_o), - .GPIO_T (gpio_t), - .hdmi_data (hdmi_data), - .hdmi_data_e (hdmi_data_e), - .hdmi_hsync (hdmi_hsync), - .hdmi_out_clk (hdmi_out_clk), - .hdmi_vsync (hdmi_vsync), - .adc_ia_clk_d_o(adc_ia_clk_d_o), - .adc_ia_clk_o(adc_ia_clk_o), - .adc_ia_dat_d_i(adc_ia_dat_d_i), - .adc_ia_dat_i(adc_ia_dat_i), - .adc_ib_clk_d_o(adc_ib_clk_d_o), - .adc_ib_clk_o(adc_ib_clk_o), - .adc_ib_dat_d_i(adc_ib_dat_d_i), - .adc_ib_dat_i(adc_ib_dat_i), - .adc_it_clk_d_o(adc_it_clk_d_o), - .adc_it_clk_o(adc_it_clk_o), - .adc_it_dat_d_i(adc_it_dat_d_i), - .adc_it_dat_i(adc_it_dat_i), - .adc_vbus_clk_o(adc_vbus_clk_o), - .adc_vbus_dat_i(adc_vbus_dat_i), - .fmc_m1_en_o(fmc_m1_en_o), - .fmc_m1_fault_i(fmc_m1_fault_i), - .gpo_o(gpo_o), - .position_i(position_i), - .pwm_ah_o(pwm_ah_o), - .pwm_al_o(pwm_al_o), - .pwm_bh_o(pwm_bh_o), - .pwm_bl_o(pwm_bl_o), - .pwm_ch_o(pwm_ch_o), - .pwm_cl_o(pwm_cl_o), - //.Vaux0_v_n(vauxn0), - //.Vaux0_v_p(vauxp0), - //.vauxn8(vauxn8), - //.vauxp8(vauxp8), - //.Vp_Vn_v_n(vn_in), - //.Vp_Vn_v_p(vp_in), - //.muxaddr_out(muxaddr_out), - .i2s_bclk (i2s_bclk), - .i2s_lrclk (i2s_lrclk), - .i2s_mclk (i2s_mclk), - .i2s_sdata_in (i2s_sdata_in), - .i2s_sdata_out (i2s_sdata_out), - .iic_fmc_scl_io (iic_scl), - .iic_fmc_sda_io (iic_sda), - .iic_mux_scl_I (iic_mux_scl_i_s), - .iic_mux_scl_O (iic_mux_scl_o_s), - .iic_mux_scl_T (iic_mux_scl_t_s), - .iic_mux_sda_I (iic_mux_sda_i_s), - .iic_mux_sda_O (iic_mux_sda_o_s), - .iic_mux_sda_T (iic_mux_sda_t_s), - .ps_intr_0 (ps_intrs[0]), - .ps_intr_1 (ps_intrs[1]), - .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), - .ps_intr_2 (ps_intrs[2]), - .ps_intr_3 (ps_intrs[3]), - .ps_intr_4 (ps_intrs[4]), - .ps_intr_5 (ps_intrs[5]), - .ps_intr_6 (ps_intrs[6]), - .ps_intr_7 (ps_intrs[7]), - .ps_intr_8 (ps_intrs[8]), - .ps_intr_9 (ps_intrs[9]), - .iic_fmc_intr(ps_intrs[11]), - .motcon1_c_m_1_irq(ps_intrs[13]), - .motcon1_c_m_2_irq(ps_intrs[9]), - .motcon1_s_d_irq(ps_intrs[12]), - .motcon1_ctrl_irq(ps_intrs[10]), - .otg_vbusoc (otg_vbusoc), - .spdif (spdif)); - -endmodule - -// *************************************************************************** -// *************************************************************************** From 0be3364dc20840ca729b5577bc7ea71ffe643d6a Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 20 Feb 2015 16:34:58 +0200 Subject: [PATCH 13/91] motcon2_fmc: Added system_project.tcl to the project --- projects/motcon2_fmc/zed/system_project.tcl | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 projects/motcon2_fmc/zed/system_project.tcl diff --git a/projects/motcon2_fmc/zed/system_project.tcl b/projects/motcon2_fmc/zed/system_project.tcl new file mode 100644 index 000000000..4eaaf96de --- /dev/null +++ b/projects/motcon2_fmc/zed/system_project.tcl @@ -0,0 +1,12 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl + +adi_project_create motcon2_fmc_zed +adi_project_files motcon2_fmc_zed [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ] + +adi_project_run motcon2_fmc_zed From 9c04491e1bb585196cc69330d3b68eb0e7f0f813 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 20 Feb 2015 15:09:09 +0100 Subject: [PATCH 14/91] fmcomms1: Add extra AXI slice on ADC DMA path Add a extra AXI slice on the ADC DMA data path to the HP interconnect to improve the timing. Signed-off-by: Lars-Peter Clausen --- projects/fmcomms1/zed/system_bd.tcl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/projects/fmcomms1/zed/system_bd.tcl b/projects/fmcomms1/zed/system_bd.tcl index 219ae0b2b..58b9dfc27 100644 --- a/projects/fmcomms1/zed/system_bd.tcl +++ b/projects/fmcomms1/zed/system_bd.tcl @@ -2,4 +2,12 @@ source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source ../common/fmcomms1_bd.tcl - + # Add extra register slice between ADC DMA and HP1 to meet timing + delete_bd_objs [get_bd_intf_nets axi_ad9643_dma_axi] + create_bd_cell -type ip -vlnv xilinx.com:ip:axi_register_slice:2.1 axi_register_slice_0 + set_property -dict [list CONFIG.REG_AW {0} CONFIG.REG_AR {0} CONFIG.REG_W {1} CONFIG.REG_R {0} CONFIG.REG_B {0}] [get_bd_cells axi_register_slice_0] + connect_bd_intf_net [get_bd_intf_pins axi_register_slice_0/S_AXI] [get_bd_intf_pins axi_ad9643_dma/m_dest_axi] + connect_bd_intf_net [get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins axi_register_slice_0/M_AXI] + connect_bd_net -net [get_bd_nets sys_200m_clk] [get_bd_pins axi_register_slice_0/aclk] [get_bd_pins sys_ps7/FCLK_CLK1] + connect_bd_net -net [get_bd_nets sys_100m_resetn] [get_bd_pins axi_register_slice_0/aresetn] [get_bd_pins sys_rstgen/peripheral_aresetn] + assign_bd_address [get_bd_addr_segs {sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM }] From 12d8461159bb6d38fdb1c422ed5c4e4861e5bc8e Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 24 Feb 2015 12:14:04 +0200 Subject: [PATCH 15/91] motcon2_fmc: Updated constraint files and fixed reset connection --- projects/motcon2_fmc/common/motcon2_fmc_bd.tcl | 8 +++++--- projects/motcon2_fmc/zed/system_constr.xdc | 8 ++++---- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index f871dba8f..5e8be1a6b 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -555,8 +555,9 @@ # ethernet + connect_bd_net -net sys_200m_clk [get_bd_ports refclk] [get_bd_pins sys_ps7/FCLK_CLK1] - connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_ports refclk_rst] + connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_ports refclk_rst] [get_bd_pins sys_rstgen/peripheral_reset] connect_bd_net -net sys_100m_resetn [get_bd_ports eth_phy_rst_n] connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_MDC] [get_bd_ports eth_mdio_mdc] connect_bd_net [get_bd_pins /sys_ps7/ENET0_MDIO_O] [get_bd_ports eth_mdio_o] @@ -565,7 +566,8 @@ # phy 1 connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_1 [get_bd_intf_pins gmii_to_rgmii_eth1/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_0] connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii] - connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] + connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] [get_bd_pins sys_rstgen/peripheral_reset] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] @@ -575,7 +577,7 @@ # phy 2 connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii] - connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] + connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] [get_bd_pins sys_rstgen/peripheral_reset] connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index 04547ea1a..5b41ab5c8 100644 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -136,9 +136,9 @@ create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] create_clock -name eth1_rx_clk_vir -period 8 set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}] +set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] -set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rxd*}] +set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] @@ -170,9 +170,9 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmi set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}] +set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] -set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rxd*}] +set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] From 46271a76208f31ad40e990df6f5e28985e7fab83 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 2 Mar 2015 16:44:42 +0200 Subject: [PATCH 16/91] motcon2_fmc: added xadc, added constraints for several IP internal clocks --- .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 32 ++--- projects/motcon2_fmc/zed/system_constr.xdc | 128 ++++++++++-------- projects/motcon2_fmc/zed/system_top.v | 15 +- 3 files changed, 98 insertions(+), 77 deletions(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index 5e8be1a6b..e3ffa0597 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -83,8 +83,8 @@ set spi_miso_i [create_bd_port -dir I spi_miso_i] # xadc interface - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 - #create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux0 + create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 Vaux8 #create_bd_port -dir O -from 4 -to 0 muxaddr_out @@ -217,14 +217,14 @@ set iic_ee2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 iic_ee2 ] # xadc - #set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ] - #set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core - #set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {true} ] $xadc_core - #set_property -dict [ list CONFIG.EXTERNAL_MUX_CHANNEL {VAUXP0_VAUXN0} ] $xadc_core - #set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core - #set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core - #set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core - #set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core + set xadc_core [ create_bd_cell -type ip -vlnv xilinx.com:ip:xadc_wiz:3.0 xadc_core ] + set_property -dict [ list CONFIG.XADC_STARUP_SELECTION {simultaneous_sampling} ] $xadc_core + set_property -dict [ list CONFIG.ENABLE_EXTERNAL_MUX {false} ] $xadc_core + set_property -dict [ list CONFIG.CHANNEL_ENABLE_VAUXP0_VAUXN0 {true} ] $xadc_core + set_property -dict [ list CONFIG.OT_ALARM {false} ] $xadc_core + set_property -dict [ list CONFIG.USER_TEMP_ALARM {false} ] $xadc_core + set_property -dict [ list CONFIG.VCCAUX_ALARM {false} ] $xadc_core + set_property -dict [ list CONFIG.VCCINT_ALARM {false} ] $xadc_core # additional interconnect set axi_mem_interconnect [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_interconnect ] @@ -587,10 +587,10 @@ connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_r] # xadc - #connect_bd_net -net sys_100m_clk [get_bd_pins xadc_core/s_axi_aclk] $sys_100m_clk_source - #connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_core/s_axi_aresetn] $sys_100m_resetn_source - #connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_core/Vaux0] [get_bd_intf_ports Vaux0] - #connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_core/Vaux8] [get_bd_intf_ports Vaux8] + connect_bd_net -net sys_100m_clk [get_bd_pins xadc_core/s_axi_aclk] $sys_100m_clk_source + connect_bd_net -net sys_100m_resetn [get_bd_pins xadc_core/s_axi_aresetn] $sys_100m_resetn_source + connect_bd_intf_net -intf_net Vaux0_1 [get_bd_intf_pins xadc_core/Vaux0] [get_bd_intf_ports Vaux0] + connect_bd_intf_net -intf_net Vaux8_1 [get_bd_intf_pins xadc_core/Vaux8] [get_bd_intf_ports Vaux8] #connect_bd_net -net xadc_muxout [get_bd_pins /xadc_core/muxaddr_out] [get_bd_ports muxaddr_out] # iic @@ -640,7 +640,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M20_ARESETN] $sys_100m_resetn_source connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins iic_ee2/S_AXI] -boundary_type upper [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] -# connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins xadc_core/s_axi_lite] + connect_bd_intf_net -intf_net axi_cpu_interconnect_m08_axi [get_bd_intf_pins axi_cpu_interconnect/M08_AXI] [get_bd_intf_pins xadc_core/s_axi_lite] connect_bd_intf_net -intf_net axi_cpu_interconnect_m09_axi [get_bd_intf_pins axi_cpu_interconnect/M09_AXI] [get_bd_intf_pins speed_detector_m1/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m10_axi [get_bd_intf_pins axi_cpu_interconnect/M10_AXI] [get_bd_intf_pins speed_detector_m1_dma/s_axi] connect_bd_intf_net -intf_net axi_cpu_interconnect_m11_axi [get_bd_intf_pins axi_cpu_interconnect/M11_AXI] [get_bd_intf_pins speed_detector_m2/s_axi] @@ -695,7 +695,7 @@ create_bd_addr_seg -range 0x10000 -offset 0x40540000 $sys_addr_cntrl_space [get_bd_addr_segs speed_detector_m2_dma/s_axi/axi_lite] SEG_data_s_d2_dma create_bd_addr_seg -range 0x10000 -offset 0x40550000 $sys_addr_cntrl_space [get_bd_addr_segs current_monitor_m2_dma/s_axi/axi_lite] SEG_data_c_m2_dma create_bd_addr_seg -range 0x10000 -offset 0x40560000 $sys_addr_cntrl_space [get_bd_addr_segs controller_m2_dma/s_axi/axi_lite] SEG_data_c2_dma -# create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_core/s_axi_lite/Reg] SEG_data_xadc + create_bd_addr_seg -range 0x10000 -offset 0x43200000 $sys_addr_cntrl_space [get_bd_addr_segs xadc_core/s_axi_lite/Reg] SEG_data_xadc create_bd_addr_seg -range 0x10000 -offset 0x41510000 $sys_addr_cntrl_space [get_bd_addr_segs iic_ee2/S_AXI/Reg] SEG_iic_ee2_Reg create_bd_addr_seg -range $sys_mem_size -offset 0x0 [get_bd_addr_spaces speed_detector_m1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] SEG_sys_ps7_hp1_ddr_lowocm diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index 5b41ab5c8..d4546f3f6 100644 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -1,11 +1,5 @@ -#DEBUG - # Motor Control -#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 -#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 -#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 -#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[0]}] set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVCMOS25 } [get_ports {position_m1_i[1]}] @@ -55,15 +49,19 @@ set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}] set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}] +#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 +#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 +#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 +#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 #set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}] #set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}] #set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}] #set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}] -#set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] -#set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] -#set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] -#set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8] +set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] +set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] +set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] +set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVCMOS25} [get_ports vauxp8] # SPI set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVCMOS25} [get_ports fmc_spi1_sel1_rdc ] @@ -111,20 +109,51 @@ set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_ set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}] set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}] +create_generated_clock -name pwm_ctrl_1 -source [get_pins i_system_wrapper/system_i/controller_m1/inst/ref_clk] \ +-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m1/inst/pwm_gen_clk_reg/Q] +create_generated_clock -name pwm_ctrl_2 -source [get_pins i_system_wrapper/system_i/controller_m2/inst/ref_clk] \ +-divide_by 2 [get_pins i_system_wrapper/system_i/controller_m2/inst/pwm_gen_clk_reg/Q] +set_clock_groups -asynchronous \ + -group [get_clocks {pwm_ctrl_1}] \ + -group [get_clocks {pwm_ctrl_2}] + +create_generated_clock -name cm1_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ia_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm1_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ib_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm1_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/vbus_if/filter/word_count_reg[7]/Q] + +set_clock_groups -asynchronous \ + -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] + +create_generated_clock -name cm2_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ia_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ib_if/filter/word_count_reg[7]/Q] +create_generated_clock -name cm2_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ +-divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/vbus_if/filter/word_count_reg[7]/Q] + +set_clock_groups -asynchronous \ + -group [get_clocks {cm2_ia cm2_ib cm2_vbus }] + # Ethernet common set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] -set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2] -set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_2] -set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_2_5m_2] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3] -set_false_path -from [get_clocks clk_out3_system_sys_audio_clkgen_0_1] -to [get_clocks clk_2_5m_3] -set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -set_false_path -from [get_clocks clk_2_5m_3] -to [get_clocks clk_out3_system_sys_audio_clkgen_0_1] +create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] + +set_clock_groups -logically_exclusive \ + -group [get_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks {clk_out4_system_sys_audio_clkgen_0_1 }] + +set_clock_groups -asynchronous \ + -group [get_clocks {mdio_mdc}] \ + -group [get_clocks -include_generated_clocks {clk_out1_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks -include_generated_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks -include_generated_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ + -group [get_clocks -include_generated_clocks {clk_out4_system_sys_audio_clkgen_0_1}] # Ethernet 1 @@ -140,27 +169,22 @@ set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_et set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -2.8 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max 1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to rgmii_rxc1 -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to rgmii_rxc1 -hold +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -setup +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -setup +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -hold +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -hold -set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -setup 0 -set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to rgmii_rxc1 -hold -1 +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -setup +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -setup +set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -hold +set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -hold -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth1_rgmii_td[*] eth1_rgmii_tx_ctl}] -clock_fall -add_delay - -# Ethernet 2 - -# Clock Period Constraints +set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to [get_clocks rgmii_rx_ctl_clk_s] -setup 0 create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] #set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] #set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] @@ -169,28 +193,26 @@ create_clock -name eth2_rx_clk_vir -period 8 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps] set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] + set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max -1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -2.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max -1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -2.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max 1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -0.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] +set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -0.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to rgmii_rxc2 -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to rgmii_rxc2 -hold +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold -set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -setup 0 -set_multicycle_path -from [get_clocks eth2_rx_clk_vir] -to rgmii_rxc2 -hold -1 - -set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup -set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -setup -set_false_path -rise_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -rise_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold -set_false_path -fall_from [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -fall_to [get_clocks clk_out2_system_sys_audio_clkgen_0_1] -hold +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -setup +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -setup +set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -hold +set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -hold set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] diff --git a/projects/motcon2_fmc/zed/system_top.v b/projects/motcon2_fmc/zed/system_top.v index 2d5db19bc..e4801d956 100644 --- a/projects/motcon2_fmc/zed/system_top.v +++ b/projects/motcon2_fmc/zed/system_top.v @@ -118,11 +118,11 @@ module system_top ( pwm_m2_dh_o, pwm_m2_dl_o, vt_enable, -/* vauxn0, + vauxn0, vauxn8, vauxp0, vauxp8, - muxaddr_out,*/ +/* muxaddr_out,*/ i2s_mclk, i2s_bclk, @@ -226,14 +226,14 @@ module system_top ( output pwm_m2_cl_o; output pwm_m2_dh_o; output pwm_m2_dl_o; - + output vt_enable; -/* input vauxn0; + input vauxn0; input vauxn8; input vauxp0; input vauxp8; - output [ 3:0] muxaddr_out;*/ +/* output [ 3:0] muxaddr_out;*/ output spdif; @@ -243,7 +243,6 @@ module system_top ( output i2s_sdata_out; input i2s_sdata_in; - inout iic_scl; inout iic_sda; inout [ 1:0] iic_mux_scl; @@ -437,11 +436,11 @@ module system_top ( .pwm_m2_bl_o(pwm_m2_bl_o), .pwm_m2_ch_o(pwm_m2_ch_o), .pwm_m2_cl_o(pwm_m2_cl_o), -/* .Vaux0_v_n(vauxn0), + .Vaux0_v_n(vauxn0), .Vaux0_v_p(vauxp0), .Vaux8_v_n(vauxn8), .Vaux8_v_p(vauxp8), - .muxaddr_out(muxaddr_out),*/ + /*.muxaddr_out(muxaddr_out),*/ .i2s_bclk (i2s_bclk), .i2s_lrclk (i2s_lrclk), .i2s_mclk (i2s_mclk), From c92446cee0cb7e041f28b690b878d757b6887b6c Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 11 Mar 2015 12:54:12 +0200 Subject: [PATCH 17/91] ad9467_fmc: Fix port names at ILA logic In the version 2014.2 the output port of a constant module was changed from 'const' to 'dout'. This commit fix the non working ILA. --- projects/ad9467_fmc/common/ad9467_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index d8069bac5..471a63eff 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -208,7 +208,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins ila_fifo/din] [get_bd_pins axi_ad9467/adc_ddata] connect_bd_net -net adc_250m_clk [get_bd_pins axi_ad9467/adc_clk] [get_bd_pins ila_fifo/wr_clk] connect_bd_net -net sys_ila_clk [get_bd_pins ila_fifo/rd_clk] [get_bd_pins ila_ad9467_mon/clk] - connect_bd_net -net xlconstant_0_const [get_bd_pins ila_fifo/rd_en] [get_bd_pins ila_fifo/wr_en] [get_bd_pins ila_constant_1/const] + connect_bd_net -net xlconstant_0_const [get_bd_pins ila_fifo/rd_en] [get_bd_pins ila_fifo/wr_en] [get_bd_pins ila_constant_1/dout] connect_bd_net -net ila_fifo_dout [get_bd_pins ila_fifo/dout] [get_bd_pins ila_ad9467_mon/probe0] From ad105b9c5424951de906275fece616d83f846d84 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 11 Mar 2015 15:03:35 -0400 Subject: [PATCH 18/91] kc705/vc707: intr sensitivity fix --- projects/common/kc705/kc705_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 8f5901ae4..386fa19d2 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -330,7 +330,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_hdmi_dma/mm2s connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2intc_irpt] for {set intc_index 10} {$intc_index < 32} {incr intc_index} { - set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] + set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } From 21f884e34634f8411e4b277ab2a84107150cb3ec Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Wed, 11 Mar 2015 15:03:43 -0400 Subject: [PATCH 19/91] kc705/vc707: intr sensitivity fix --- projects/common/vc707/vc707_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 91bd4df9e..36d339c54 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -353,7 +353,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In8] [get_bd_pins axi_hdmi_dma/mm2s connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2intc_irpt] for {set intc_index 10} {$intc_index < 32} {incr intc_index} { - set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] + set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } From c8b56253d7b95d997946ab88c30435b73ca7f679 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:49:46 +0200 Subject: [PATCH 20/91] axi_i2s_adi: Fixed pins directions --- library/axi_i2s_adi/axi_i2s_adi.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd index 9d3bd5a6a..b1728d22b 100644 --- a/library/axi_i2s_adi/axi_i2s_adi.vhd +++ b/library/axi_i2s_adi/axi_i2s_adi.vhd @@ -99,10 +99,10 @@ entity axi_i2s_adi is S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; - S_AXI_WREADY : inout std_logic; + S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); - S_AXI_BVALID : inout std_logic; - S_AXI_AWREADY : inout std_logic + S_AXI_BVALID : out std_logic; + S_AXI_AWREADY : out std_logic ); end entity axi_i2s_adi; From 1c0d5fbb5158845db542a00e20786807bca4e429 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:51:31 +0200 Subject: [PATCH 21/91] utiil_gmii_to_rgmii: registerd Rx/ Tx paths. Changed RX clock buffers to a single BUFG --- .../util_gmii_to_rgmii/util_gmii_to_rgmii.v | 89 ++++++++----------- 1 file changed, 37 insertions(+), 52 deletions(-) diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v index 5c165cc67..3ad00a845 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -103,13 +103,8 @@ module util_gmii_to_rgmii ( wire clk_100msps; wire [ 3:0] rgmii_rd_delay; wire [ 7:0] gmii_rxd_s; - wire [ 3:0] gmii_txd_low; wire rgmii_rx_ctl_delay; - wire gmii_rx_er_s; - wire rgmii_rxc_s; - wire rgmii_rx_ctl_clk_s; wire rgmii_rx_ctl_s; - wire rgmii_rxc_bufmr; wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps wire duplex_mode; // 1 full, 0 half @@ -118,30 +113,45 @@ module util_gmii_to_rgmii ( reg tx_reset_d1; reg tx_reset_sync; reg rx_reset_d1; - reg rx_reset_sync; reg [ 7:0] gmii_txd_r; reg gmii_tx_en_r; reg gmii_tx_er_r; + reg [ 7:0] gmii_txd_r_d1; + reg gmii_tx_en_r_d1; + reg gmii_tx_er_r_d1; + + reg rgmii_tx_ctl_r; + reg [ 3:0] gmii_txd_low; + reg gmii_col; + reg gmii_crs; + + reg [ 7:0] gmii_rxd; + reg gmii_rx_dv; + reg gmii_rx_er; - // assignments assign gigabit = speed_selection [1]; - assign gmii_tx_clk = gmii_tx_clk_s; - assign rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; - assign gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; - assign gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r) & ( gmii_rx_dv_s | gmii_rx_er_s) ; - assign gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r | gmii_rx_dv_s | gmii_rx_er_s); - assign gmii_rxd = gmii_rxd_s; - assign gmii_rx_dv = gmii_rx_dv_s; - assign gmii_rx_er = gmii_rx_er_s; - assign gmii_rx_er_s = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + always @(posedge gmii_rx_clk) + begin + gmii_rxd = gmii_rxd_s; + gmii_rx_dv = gmii_rx_dv_s; + gmii_rx_er = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + end always @(posedge gmii_tx_clk_s) begin tx_reset_d1 <= reset; tx_reset_sync <= tx_reset_d1; end + always @(posedge gmii_tx_clk_s) + begin + rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; + gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; + gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r) & ( gmii_rx_dv | gmii_rx_er) ; + gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r| gmii_rx_dv | gmii_rx_er); + end + always @(posedge gmii_tx_clk_s) begin if (tx_reset_sync == 1'b1) begin gmii_txd_r <= 8'h0; @@ -153,6 +163,9 @@ module util_gmii_to_rgmii ( gmii_txd_r <= gmii_txd; gmii_tx_en_r <= gmii_tx_en; gmii_tx_er_r <= gmii_tx_er; + gmii_txd_r_d1 <= gmii_txd_r; + gmii_tx_en_r_d1 <= gmii_tx_en_r; + gmii_tx_er_r_d1 <= gmii_tx_er_r; end end @@ -201,7 +214,7 @@ module util_gmii_to_rgmii ( .Q (rgmii_td[i]), .C (gmii_tx_clk_s), .CE(1), - .D1(gmii_txd_r[i]), + .D1(gmii_txd_r_d1[i]), .D2(gmii_txd_low[i]), .R(tx_reset_sync), .S(0)); @@ -214,41 +227,13 @@ module util_gmii_to_rgmii ( .Q (rgmii_tx_ctl), .C (gmii_tx_clk_s), .CE(1), - .D1(gmii_tx_en_r), + .D1(gmii_tx_en_r_d1), .D2(rgmii_tx_ctl_r), .R(tx_reset_sync), .S(0)); - - always @(posedge rgmii_rxc_s) begin - rx_reset_d1 <= reset; - rx_reset_sync <= rx_reset_d1; - end - - BUFMR bufmr_rgmii_rxc( + BUFG bufmr_rgmii_rxc( .I(rgmii_rxc), - .O(rgmii_rxc_bufmr)); - - BUFR #( - .SIM_DEVICE("7SERIES"), - .BUFR_DIVIDE(1) - ) bufr_rgmii_rx_clk ( - .I(rgmii_rxc_bufmr), - .CE(1), - .CLR(0), - .O(rgmii_rxc_s)); - - BUFR #( - .SIM_DEVICE("7SERIES"), - .BUFR_DIVIDE(1) - ) bufr_rgmii_rx_ctl_clk ( - .I(rgmii_rxc_bufmr), - .CE(1), - .CLR(0), - .O(rgmii_rx_ctl_clk_s)); - - BUFG bufg_rgmii_rx_clk ( - .I(rgmii_rxc_s), .O(gmii_rx_clk)); IDELAYE2 #( @@ -275,9 +260,9 @@ module util_gmii_to_rgmii ( for (i = 0; i < 4; i = i + 1) begin IDELAYE2 #( .IDELAY_TYPE("FIXED"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA"), .DELAY_SRC("IDATAIN") ) delay_rgmii_rd ( .IDATAIN(rgmii_rd[i]), @@ -298,7 +283,7 @@ module util_gmii_to_rgmii ( ) rgmii_rx_iddr ( .Q1(gmii_rxd_s[i]), .Q2(gmii_rxd_s[i+4]), - .C(rgmii_rxc_s), + .C(gmii_rx_clk), .CE(1), .D(rgmii_rd_delay[i]), .R(0), @@ -311,7 +296,7 @@ module util_gmii_to_rgmii ( ) rgmii_rx_ctl_iddr ( .Q1(gmii_rx_dv_s), .Q2(rgmii_rx_ctl_s), - .C(rgmii_rx_ctl_clk_s), + .C(gmii_rx_clk), .CE(1), .D(rgmii_rx_ctl_delay), .R(0), From f62bc5cc9a737c8bd69de8e64cffb67659a5b444 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:55:36 +0200 Subject: [PATCH 22/91] motcon2_fmc: Updated design - separated clocks for ethernet and other cores in the design - removed constraints that were not needed --- .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 21 +-- projects/motcon2_fmc/zed/system_constr.xdc | 134 +++++------------- 2 files changed, 48 insertions(+), 107 deletions(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index e3ffa0597..e557b6f6a 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -107,9 +107,14 @@ set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT5_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT2_DRIVES {No_buffer} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT3_DRIVES {No_buffer} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT4_DRIVES {No_buffer} ] $sys_audio_clkgen # speed detectors # speed detector core motor 1 @@ -281,7 +286,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/m_dest_axi_aresetn] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins current_monitor_m1/adc_ia_dat_i] connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins current_monitor_m1/adc_ib_dat_i] connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins current_monitor_m1/adc_vbus_dat_i] @@ -330,7 +335,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/m_dest_axi_aresetn] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net adc_m2_ia_dat_i_1 [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins current_monitor_m2/adc_ia_dat_i] connect_bd_net -net adc_m2_ib_dat_i_1 [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins current_monitor_m2/adc_ib_dat_i] connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins current_monitor_m2/adc_vbus_dat_i] @@ -375,7 +380,7 @@ # motor 1 connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1/s_axi_aresetn] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/s_axi_aclk] $sys_100m_clk_source @@ -464,7 +469,7 @@ # motor 2 connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/s_axi_aclk] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/ref_clk] $sys_100m_clk_source - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2/s_axi_aresetn] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/s_axi_aclk] $sys_100m_clk_source @@ -568,9 +573,9 @@ connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] [get_bd_pins sys_rstgen/peripheral_reset] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] - connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth1/mdio_mdc] connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_w] connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_r] @@ -578,9 +583,9 @@ connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] [get_bd_pins sys_rstgen/peripheral_reset] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] - connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth2/mdio_mdc] connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_w] diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index d4546f3f6..271018fdb 100644 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -48,16 +48,6 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}] set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}] set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}] - -#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 -#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 -#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 -#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 -#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}] -#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}] -#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}] -#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}] - set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] @@ -88,12 +78,12 @@ set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_ set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}] set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}] set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}] -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc] -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl] -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}] -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}] -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}] -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_txc] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[3]}] # Ethernet 2 set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc] @@ -102,20 +92,26 @@ set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_ set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}] set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}] set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}] -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc] -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}] -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}] -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}] -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}] +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_txc] +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[3]}] + + +#create clocks +# Clock Period Constraints +create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] + +create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] + +create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] create_generated_clock -name pwm_ctrl_1 -source [get_pins i_system_wrapper/system_i/controller_m1/inst/ref_clk] \ -divide_by 2 [get_pins i_system_wrapper/system_i/controller_m1/inst/pwm_gen_clk_reg/Q] create_generated_clock -name pwm_ctrl_2 -source [get_pins i_system_wrapper/system_i/controller_m2/inst/ref_clk] \ -divide_by 2 [get_pins i_system_wrapper/system_i/controller_m2/inst/pwm_gen_clk_reg/Q] -set_clock_groups -asynchronous \ - -group [get_clocks {pwm_ctrl_1}] \ - -group [get_clocks {pwm_ctrl_2}] create_generated_clock -name cm1_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ia_if/filter/word_count_reg[7]/Q] @@ -124,9 +120,6 @@ create_generated_clock -name cm1_ib -source [get_pins i_system_wrapper/system_i/ create_generated_clock -name cm1_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/vbus_if/filter/word_count_reg[7]/Q] -set_clock_groups -asynchronous \ - -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] - create_generated_clock -name cm2_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ia_if/filter/word_count_reg[7]/Q] create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ @@ -134,87 +127,30 @@ create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/ create_generated_clock -name cm2_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/vbus_if/filter/word_count_reg[7]/Q] +set_clock_groups -asynchronous \ + -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] + set_clock_groups -asynchronous \ -group [get_clocks {cm2_ia cm2_ib cm2_vbus }] +set_clock_groups -asynchronous \ + -group [get_clocks {pwm_ctrl_1 }] \ + -group [get_clocks {pwm_ctrl_2 }] + # Ethernet common set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] -create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] - -set_clock_groups -logically_exclusive \ - -group [get_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks {clk_out4_system_sys_audio_clkgen_0_1 }] - -set_clock_groups -asynchronous \ - -group [get_clocks {mdio_mdc}] \ - -group [get_clocks -include_generated_clocks {clk_out1_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out4_system_sys_audio_clkgen_0_1}] - # Ethernet 1 - -# Clock Period Constraints -create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] -#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] -#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] - -create_clock -name eth1_rx_clk_vir -period 8 - -set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] +#IDELAY +set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max 1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] - -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -hold - -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -hold - -set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to [get_clocks rgmii_rx_ctl_clk_s] -setup 0 -create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] -#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] -#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] - -create_clock -name eth2_rx_clk_vir -period 8 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] - - -set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] +# Ethernet 2 +#IDELAY +set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] - -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max 1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -0.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -0.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] - -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold - -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -hold - -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay From 49f50829fac9455db647e7fff662ba8ddecbfda1 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:49:46 +0200 Subject: [PATCH 23/91] axi_i2s_adi: Fixed pins directions --- library/axi_i2s_adi/axi_i2s_adi.vhd | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/library/axi_i2s_adi/axi_i2s_adi.vhd b/library/axi_i2s_adi/axi_i2s_adi.vhd index 9d3bd5a6a..b1728d22b 100644 --- a/library/axi_i2s_adi/axi_i2s_adi.vhd +++ b/library/axi_i2s_adi/axi_i2s_adi.vhd @@ -99,10 +99,10 @@ entity axi_i2s_adi is S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; - S_AXI_WREADY : inout std_logic; + S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); - S_AXI_BVALID : inout std_logic; - S_AXI_AWREADY : inout std_logic + S_AXI_BVALID : out std_logic; + S_AXI_AWREADY : out std_logic ); end entity axi_i2s_adi; From 27afec5f9e0b9b260a8da6b9d21a9aaf46eb56f1 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:51:31 +0200 Subject: [PATCH 24/91] utiil_gmii_to_rgmii: registerd Rx/ Tx paths. Changed RX clock buffers to a single BUFG --- .../util_gmii_to_rgmii/util_gmii_to_rgmii.v | 89 ++++++++----------- 1 file changed, 37 insertions(+), 52 deletions(-) diff --git a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v index 5c165cc67..3ad00a845 100644 --- a/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v +++ b/library/util_gmii_to_rgmii/util_gmii_to_rgmii.v @@ -103,13 +103,8 @@ module util_gmii_to_rgmii ( wire clk_100msps; wire [ 3:0] rgmii_rd_delay; wire [ 7:0] gmii_rxd_s; - wire [ 3:0] gmii_txd_low; wire rgmii_rx_ctl_delay; - wire gmii_rx_er_s; - wire rgmii_rxc_s; - wire rgmii_rx_ctl_clk_s; wire rgmii_rx_ctl_s; - wire rgmii_rxc_bufmr; wire [ 1:0] speed_selection; // 1x gigabit, 01 100Mbps, 00 10mbps wire duplex_mode; // 1 full, 0 half @@ -118,30 +113,45 @@ module util_gmii_to_rgmii ( reg tx_reset_d1; reg tx_reset_sync; reg rx_reset_d1; - reg rx_reset_sync; reg [ 7:0] gmii_txd_r; reg gmii_tx_en_r; reg gmii_tx_er_r; + reg [ 7:0] gmii_txd_r_d1; + reg gmii_tx_en_r_d1; + reg gmii_tx_er_r_d1; + + reg rgmii_tx_ctl_r; + reg [ 3:0] gmii_txd_low; + reg gmii_col; + reg gmii_crs; + + reg [ 7:0] gmii_rxd; + reg gmii_rx_dv; + reg gmii_rx_er; - // assignments assign gigabit = speed_selection [1]; - assign gmii_tx_clk = gmii_tx_clk_s; - assign rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; - assign gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; - assign gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r) & ( gmii_rx_dv_s | gmii_rx_er_s) ; - assign gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r | gmii_tx_er_r | gmii_rx_dv_s | gmii_rx_er_s); - assign gmii_rxd = gmii_rxd_s; - assign gmii_rx_dv = gmii_rx_dv_s; - assign gmii_rx_er = gmii_rx_er_s; - assign gmii_rx_er_s = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + always @(posedge gmii_rx_clk) + begin + gmii_rxd = gmii_rxd_s; + gmii_rx_dv = gmii_rx_dv_s; + gmii_rx_er = gmii_rx_dv_s ^ rgmii_rx_ctl_s; + end always @(posedge gmii_tx_clk_s) begin tx_reset_d1 <= reset; tx_reset_sync <= tx_reset_d1; end + always @(posedge gmii_tx_clk_s) + begin + rgmii_tx_ctl_r = gmii_tx_en_r ^ gmii_tx_er_r; + gmii_txd_low = gigabit ? gmii_txd_r[7:4] : gmii_txd_r[3:0]; + gmii_col = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r) & ( gmii_rx_dv | gmii_rx_er) ; + gmii_crs = duplex_mode ? 1'b0 : (gmii_tx_en_r| gmii_tx_er_r| gmii_rx_dv | gmii_rx_er); + end + always @(posedge gmii_tx_clk_s) begin if (tx_reset_sync == 1'b1) begin gmii_txd_r <= 8'h0; @@ -153,6 +163,9 @@ module util_gmii_to_rgmii ( gmii_txd_r <= gmii_txd; gmii_tx_en_r <= gmii_tx_en; gmii_tx_er_r <= gmii_tx_er; + gmii_txd_r_d1 <= gmii_txd_r; + gmii_tx_en_r_d1 <= gmii_tx_en_r; + gmii_tx_er_r_d1 <= gmii_tx_er_r; end end @@ -201,7 +214,7 @@ module util_gmii_to_rgmii ( .Q (rgmii_td[i]), .C (gmii_tx_clk_s), .CE(1), - .D1(gmii_txd_r[i]), + .D1(gmii_txd_r_d1[i]), .D2(gmii_txd_low[i]), .R(tx_reset_sync), .S(0)); @@ -214,41 +227,13 @@ module util_gmii_to_rgmii ( .Q (rgmii_tx_ctl), .C (gmii_tx_clk_s), .CE(1), - .D1(gmii_tx_en_r), + .D1(gmii_tx_en_r_d1), .D2(rgmii_tx_ctl_r), .R(tx_reset_sync), .S(0)); - - always @(posedge rgmii_rxc_s) begin - rx_reset_d1 <= reset; - rx_reset_sync <= rx_reset_d1; - end - - BUFMR bufmr_rgmii_rxc( + BUFG bufmr_rgmii_rxc( .I(rgmii_rxc), - .O(rgmii_rxc_bufmr)); - - BUFR #( - .SIM_DEVICE("7SERIES"), - .BUFR_DIVIDE(1) - ) bufr_rgmii_rx_clk ( - .I(rgmii_rxc_bufmr), - .CE(1), - .CLR(0), - .O(rgmii_rxc_s)); - - BUFR #( - .SIM_DEVICE("7SERIES"), - .BUFR_DIVIDE(1) - ) bufr_rgmii_rx_ctl_clk ( - .I(rgmii_rxc_bufmr), - .CE(1), - .CLR(0), - .O(rgmii_rx_ctl_clk_s)); - - BUFG bufg_rgmii_rx_clk ( - .I(rgmii_rxc_s), .O(gmii_rx_clk)); IDELAYE2 #( @@ -275,9 +260,9 @@ module util_gmii_to_rgmii ( for (i = 0; i < 4; i = i + 1) begin IDELAYE2 #( .IDELAY_TYPE("FIXED"), - .HIGH_PERFORMANCE_MODE("TRUE"), - .REFCLK_FREQUENCY(200.0), - .SIGNAL_PATTERN("DATA"), + .HIGH_PERFORMANCE_MODE("TRUE"), + .REFCLK_FREQUENCY(200.0), + .SIGNAL_PATTERN("DATA"), .DELAY_SRC("IDATAIN") ) delay_rgmii_rd ( .IDATAIN(rgmii_rd[i]), @@ -298,7 +283,7 @@ module util_gmii_to_rgmii ( ) rgmii_rx_iddr ( .Q1(gmii_rxd_s[i]), .Q2(gmii_rxd_s[i+4]), - .C(rgmii_rxc_s), + .C(gmii_rx_clk), .CE(1), .D(rgmii_rd_delay[i]), .R(0), @@ -311,7 +296,7 @@ module util_gmii_to_rgmii ( ) rgmii_rx_ctl_iddr ( .Q1(gmii_rx_dv_s), .Q2(rgmii_rx_ctl_s), - .C(rgmii_rx_ctl_clk_s), + .C(gmii_rx_clk), .CE(1), .D(rgmii_rx_ctl_delay), .R(0), From 68224f82defdd3895afb0773cd2c743d41e5269e Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Thu, 12 Mar 2015 16:55:36 +0200 Subject: [PATCH 25/91] motcon2_fmc: Updated design - separated clocks for ethernet and other cores in the design - removed constraints that were not needed --- .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 21 +-- projects/motcon2_fmc/zed/system_constr.xdc | 134 +++++------------- 2 files changed, 48 insertions(+), 107 deletions(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index e3ffa0597..e557b6f6a 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -107,9 +107,14 @@ set_property -dict [ list CONFIG.CLKOUT2_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT3_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT4_USED {true} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT5_USED {true} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {25} ] $sys_audio_clkgen set_property -dict [ list CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {20} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT2_DRIVES {No_buffer} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT3_DRIVES {No_buffer} ] $sys_audio_clkgen + set_property -dict [ list CONFIG.CLKOUT4_DRIVES {No_buffer} ] $sys_audio_clkgen # speed detectors # speed detector core motor 1 @@ -281,7 +286,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m1_dma/m_dest_axi_aresetn] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m1/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net adc_m1_ia_dat_i_1 [get_bd_ports adc_m1_ia_dat_i] [get_bd_pins current_monitor_m1/adc_ia_dat_i] connect_bd_net -net adc_m1_ib_dat_i_1 [get_bd_ports adc_m1_ib_dat_i] [get_bd_pins current_monitor_m1/adc_ib_dat_i] connect_bd_net -net adc_m1_vbus_dat_i_1 [get_bd_ports adc_m1_vbus_dat_i] [get_bd_pins current_monitor_m1/adc_vbus_dat_i] @@ -330,7 +335,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins current_monitor_m2_dma/m_dest_axi_aresetn] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins current_monitor_m2/adc_clk_i] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net adc_m2_ia_dat_i_1 [get_bd_ports adc_m2_ia_dat_i] [get_bd_pins current_monitor_m2/adc_ia_dat_i] connect_bd_net -net adc_m2_ib_dat_i_1 [get_bd_ports adc_m2_ib_dat_i] [get_bd_pins current_monitor_m2/adc_ib_dat_i] connect_bd_net -net adc_m2_vbus_dat_i_1 [get_bd_ports adc_m2_vbus_dat_i] [get_bd_pins current_monitor_m2/adc_vbus_dat_i] @@ -375,7 +380,7 @@ # motor 1 connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/s_axi_aclk] $sys_100m_clk_source - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m1/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m1/s_axi_aresetn] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1_dma/s_axi_aclk] $sys_100m_clk_source @@ -464,7 +469,7 @@ # motor 2 connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/s_axi_aclk] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2/ref_clk] $sys_100m_clk_source - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out5 [get_bd_pins controller_m2/ctrl_data_clk] [get_bd_pins sys_audio_clkgen/clk_out5] connect_bd_net -net sys_100m_resetn [get_bd_pins controller_m2/s_axi_aresetn] $sys_100m_resetn_source connect_bd_net -net sys_100m_clk [get_bd_pins controller_m2_dma/s_axi_aclk] $sys_100m_clk_source @@ -568,9 +573,9 @@ connect_bd_intf_net -intf_net gmii_to_rgmii_eth1_rgmii [get_bd_intf_ports eth1_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth1/rgmii] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth1/reset] [get_bd_pins sys_rstgen/peripheral_reset] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth1/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] - connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth1/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth1/mdio_mdc] connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_w] connect_bd_net [get_bd_ports eth_mdio_i] [get_bd_pins gmii_to_rgmii_eth1/mdio_in_r] @@ -578,9 +583,9 @@ connect_bd_intf_net -intf_net sys_ps7_GMII_ETHERNET_2 [get_bd_intf_pins gmii_to_rgmii_eth2/gmii] [get_bd_intf_pins sys_ps7/GMII_ETHERNET_1] connect_bd_intf_net -intf_net gmii_to_rgmii_eth2_rgmii [get_bd_intf_ports eth2_rgmii] [get_bd_intf_pins gmii_to_rgmii_eth2/rgmii] connect_bd_net -net sys_rstgen_peripheral_reset [get_bd_pins gmii_to_rgmii_eth2/reset] [get_bd_pins sys_rstgen/peripheral_reset] - connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] + connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_20m] [get_bd_pins sys_audio_clkgen/clk_out4] connect_bd_net -net sys_audio_clkgen_clk_out3 [get_bd_pins gmii_to_rgmii_eth2/clk_25m] [get_bd_pins sys_audio_clkgen/clk_out3] - connect_bd_net -net sys_audio_clkgen_clk_out4 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] + connect_bd_net -net sys_audio_clkgen_clk_out2 [get_bd_pins gmii_to_rgmii_eth2/clk_125m] [get_bd_pins sys_audio_clkgen/clk_out2] connect_bd_net [get_bd_ports eth_mdio_mdc] [get_bd_pins gmii_to_rgmii_eth2/mdio_mdc] connect_bd_net [get_bd_ports eth_mdio_o] [get_bd_pins gmii_to_rgmii_eth2/mdio_in_w] diff --git a/projects/motcon2_fmc/zed/system_constr.xdc b/projects/motcon2_fmc/zed/system_constr.xdc index d4546f3f6..271018fdb 100644 --- a/projects/motcon2_fmc/zed/system_constr.xdc +++ b/projects/motcon2_fmc/zed/system_constr.xdc @@ -48,16 +48,6 @@ set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS25 } [get_ports {gpo[3]}] set_property -dict {PACKAGE_PIN A21 IOSTANDARD LVCMOS25} [get_ports {gpi[0]}] set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVCMOS25} [get_ports {gpi[1]}] - -#set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS33} [get_ports gpio_bd[27]] ; ## XADC-GIO0 -#set_property -dict {PACKAGE_PIN Y20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[28]] ; ## XADC-GIO1 -#set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports gpio_bd[29]] ; ## XADC-GIO2 -#set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS33} [get_ports gpio_bd[30]] ; ## XADC-GIO3 -#set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[0]}] -#set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[1]}] -#set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[2]}] -#set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS25} [get_ports {muxaddr_out[3]}] - set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVCMOS25} [get_ports vauxn0] set_property -dict {PACKAGE_PIN D17 IOSTANDARD LVCMOS25} [get_ports vauxn8] set_property -dict {PACKAGE_PIN F16 IOSTANDARD LVCMOS25} [get_ports vauxp0] @@ -88,12 +78,12 @@ set_property -dict {PACKAGE_PIN N22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_ set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[1]}] set_property -dict {PACKAGE_PIN J21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[2]}] set_property -dict {PACKAGE_PIN J22 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_rd[3]}] -set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_txc] -set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25} [get_ports eth1_rgmii_tx_ctl] -set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[0]}] -set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[1]}] -set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[2]}] -set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25} [get_ports {eth1_rgmii_td[3]}] +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_txc] +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth1_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN K21 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth1_rgmii_td[3]}] # Ethernet 2 set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_rxc] @@ -102,20 +92,26 @@ set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_ set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[1]}] set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[2]}] set_property -dict {PACKAGE_PIN R21 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_rd[3]}] -set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_txc] -set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports eth2_rgmii_tx_ctl] -set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[0]}] -set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[1]}] -set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[2]}] -set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25} [get_ports {eth2_rgmii_td[3]}] +set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_txc] +set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports eth2_rgmii_tx_ctl] +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[0]}] +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[1]}] +set_property -dict {PACKAGE_PIN E15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[2]}] +set_property -dict {PACKAGE_PIN D15 IOSTANDARD LVCMOS25 SLEW FAST} [get_ports {eth2_rgmii_td[3]}] + + +#create clocks +# Clock Period Constraints +create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] + +create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] + +create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] create_generated_clock -name pwm_ctrl_1 -source [get_pins i_system_wrapper/system_i/controller_m1/inst/ref_clk] \ -divide_by 2 [get_pins i_system_wrapper/system_i/controller_m1/inst/pwm_gen_clk_reg/Q] create_generated_clock -name pwm_ctrl_2 -source [get_pins i_system_wrapper/system_i/controller_m2/inst/ref_clk] \ -divide_by 2 [get_pins i_system_wrapper/system_i/controller_m2/inst/pwm_gen_clk_reg/Q] -set_clock_groups -asynchronous \ - -group [get_clocks {pwm_ctrl_1}] \ - -group [get_clocks {pwm_ctrl_2}] create_generated_clock -name cm1_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/ia_if/filter/word_count_reg[7]/Q] @@ -124,9 +120,6 @@ create_generated_clock -name cm1_ib -source [get_pins i_system_wrapper/system_i/ create_generated_clock -name cm1_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m1/inst/vbus_if/filter/word_count_reg[7]/Q] -set_clock_groups -asynchronous \ - -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] - create_generated_clock -name cm2_ia -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/ia_if/filter/word_count_reg[7]/Q] create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ @@ -134,87 +127,30 @@ create_generated_clock -name cm2_ib -source [get_pins i_system_wrapper/system_i/ create_generated_clock -name cm2_vbus -source [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/adc_clk_i] \ -divide_by 256 [get_pins i_system_wrapper/system_i/current_monitor_m2/inst/vbus_if/filter/word_count_reg[7]/Q] +set_clock_groups -asynchronous \ + -group [get_clocks {cm1_ia cm1_ib cm1_vbus }] + set_clock_groups -asynchronous \ -group [get_clocks {cm2_ia cm2_ib cm2_vbus }] +set_clock_groups -asynchronous \ + -group [get_clocks {pwm_ctrl_1 }] \ + -group [get_clocks {pwm_ctrl_2 }] + # Ethernet common set_property IODELAY_GROUP eth_idelay_grp [get_cells dlyctrl] -create_clock -name mdio_mdc -period 400 [get_pins i_system_wrapper/system_i/sys_ps7/inst/PS7_i/EMIOENET0MDIOMDC] - -set_clock_groups -logically_exclusive \ - -group [get_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks {clk_out4_system_sys_audio_clkgen_0_1 }] - -set_clock_groups -asynchronous \ - -group [get_clocks {mdio_mdc}] \ - -group [get_clocks -include_generated_clocks {clk_out1_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out2_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out3_system_sys_audio_clkgen_0_1 }] \ - -group [get_clocks -include_generated_clocks {clk_out4_system_sys_audio_clkgen_0_1}] - # Ethernet 1 - -# Clock Period Constraints -create_clock -period 8.000 -name rgmii_rxc1 [get_ports eth1_rgmii_rxc] -#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] -#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] - -create_clock -name eth1_rx_clk_vir -period 8 - -set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] +#IDELAY +set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth1/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth1*/*delay_rgmii_rd*}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -max 1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -min -1.2 [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth1_rx_clk_vir] -clock_fall -min -1.2 -add_delay [get_ports {eth1_rgmii_rd[*] eth1_rgmii_rx_ctl}] - -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s] -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s] -hold - -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -setup -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -setup -set_false_path -rise_from [get_clocks eth1_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s] -hold -set_false_path -fall_from [get_clocks eth1_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s] -hold - -set_multicycle_path -from [get_clocks eth1_rx_clk_vir] -to [get_clocks rgmii_rx_ctl_clk_s] -setup 0 -create_clock -period 8.000 -name rgmii_rxc2 [get_ports eth2_rgmii_rxc] -#set_clock_latency -source -early 0.5 [get_clocks rgmii_rxc1] -#set_clock_latency -source -late 0.5 [get_clocks rgmii_rxc1] - -create_clock -name eth2_rx_clk_vir -period 8 -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/gmii_to_rgmii_eth2/inst/clk_100msps] -set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets i_system_wrapper/system_i/sys_audio_clkgen/inst/clk_out3] - - -set_property IDELAY_VALUE 18 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] -set_property IDELAY_VALUE 18 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] +# Ethernet 2 +#IDELAY +set_property IDELAY_VALUE 16 [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] +set_property IDELAY_VALUE 16 [get_cells -hier -filter {name =~ *gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] set_property IODELAY_GROUP eth_idelay_grp [get_cells */*/gmii_to_rgmii_eth2/inst/*delay_rgmii_rx_ctl] set_property IODELAY_GROUP eth_idelay_grp [get_cells -hier -filter {name =~*gmii_to_rgmii_eth2*/*delay_rgmii_rd*}] - -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -max 1.2 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -min -0.8 [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -max 1.2 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] -set_input_delay -clock [get_clocks eth2_rx_clk_vir] -clock_fall -min -0.8 -add_delay [get_ports {eth2_rgmii_rd[*] eth2_rgmii_rx_ctl}] - -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rx_ctl_clk_s_1] -hold - -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -setup -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -setup -set_false_path -rise_from [get_clocks eth2_rx_clk_vir] -rise_to [get_clocks rgmii_rxc_s_1] -hold -set_false_path -fall_from [get_clocks eth2_rx_clk_vir] -fall_to [get_clocks rgmii_rxc_s_1] -hold - -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -set_output_delay -max -0.9 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay -set_output_delay -min 2.7 -clock clk_out2_system_sys_audio_clkgen_0_1 [get_ports {eth2_rgmii_td[*] eth2_rgmii_tx_ctl}] -clock_fall -add_delay From 845652308437816e5dd323fbb5dce077e7ff7ded Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:41 -0400 Subject: [PATCH 26/91] common-base-designs: add intr net names --- projects/common/ac701/ac701_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 3be137cb8..243f7bcce 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -342,7 +342,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From f3c41cd9aacc2bb5cf2927814a3084f64bea391c Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:50 -0400 Subject: [PATCH 27/91] common-base-designs: add intr net names --- projects/common/kc705/kc705_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 386fa19d2..f93085a81 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -331,7 +331,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From 63a390af49b2cc5fd0563c5f4fa0c0485bb090d0 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:59 -0400 Subject: [PATCH 28/91] common-base-designs: add intr net names --- projects/common/mitx045/mitx045_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index e8cf2d339..b38b19cec 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -237,7 +237,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From 91c87b8438af97096262875ad2fa9ed4cedcd916 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:06 -0400 Subject: [PATCH 29/91] common-base-designs: add intr net names --- projects/common/vc707/vc707_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 36d339c54..da1544056 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -354,7 +354,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From c1dc93e2c7fe3586a984f31807dea1805149d704 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:15 -0400 Subject: [PATCH 30/91] common-base-designs: add intr net names --- projects/common/zc702/zc702_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 694c13417..462ab6f12 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -198,7 +198,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From 3654be4766d8f3422d4e8f8e6ad55f0baa061368 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:25 -0400 Subject: [PATCH 31/91] common-base-designs: add intr net names --- projects/common/zc706/zc706_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index f1f9c2d33..81561c413 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -201,7 +201,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From f3188b917b348ada46d04cafca682f51b8e60d9d Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:31 -0400 Subject: [PATCH 32/91] common-base-designs: add intr net names --- projects/common/zed/zed_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 83080b1a0..008895515 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -285,7 +285,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From 28be02406cac1fbfd8f0ee9fafc72d935bda5334 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:57:35 -0400 Subject: [PATCH 33/91] fmcomms2: intrs within ipi --- projects/fmcomms2/common/fmcomms2_bd.tcl | 29 ++++++++++++------------ 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index c9814c302..7ee03021a 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -42,16 +42,6 @@ if {$sys_zynq == 1} { set spi_udc_miso_i [create_bd_port -dir I spi_udc_miso_i] } - # interrupts - - set ad9361_adc_dma_irq [create_bd_port -dir O ad9361_adc_dma_irq] - set ad9361_dac_dma_irq [create_bd_port -dir O ad9361_dac_dma_irq] - -if {$sys_zynq == 0} { - set fmcomms2_gpio_irq [create_bd_port -dir O fmcomms2_gpio_irq] - set fmcomms2_spi_irq [create_bd_port -dir O fmcomms2_spi_irq] -} - # ad9361 core set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] @@ -161,7 +151,6 @@ if {$sys_zynq == 0} { connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins axi_fmcomms2_spi/io0_i] connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins axi_fmcomms2_spi/io0_o] connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins axi_fmcomms2_spi/io1_i] - connect_bd_net -net axi_fmcomms2_spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_ports fmcomms2_spi_irq] } else { connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O] @@ -178,7 +167,6 @@ if {$sys_zynq == 0} { connect_bd_net -net gpio_fmcomms2_i [get_bd_ports gpio_fmcomms2_i] [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] connect_bd_net -net gpio_fmcomms2_o [get_bd_ports gpio_fmcomms2_o] [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] connect_bd_net -net gpio_fmcomms2_t [get_bd_ports gpio_fmcomms2_t] [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] - connect_bd_net -net axi_fmcomms2_gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_ports fmcomms2_gpio_irq] } # connections (up/down converter spi) @@ -251,8 +239,21 @@ if {$sys_zynq == 1} { connect_bd_net -net axi_ad9361_dac_drd [get_bd_pins util_dac_unpack/dma_rd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] connect_bd_net -net axi_ad9361_dac_dunf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins ad9361_adc_dma_irq] - connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins ad9361_dac_dma_irq] + if {$sys_zynq == 0} { + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_fmcomms2_spi_irq [get_bd_pins sys_concat_intc/In10] [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] + connect_bd_net -net axi_fmcomms2_gpio_irq [get_bd_pins sys_concat_intc/In11] [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9361_adc_dma/irq] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins sys_concat_intc/In13] [get_bd_pins axi_ad9361_dac_dma/irq] + } else { + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9361_dac_dma/irq] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins sys_concat_intc/In13] [get_bd_pins axi_ad9361_adc_dma/irq] + } # interconnect (cpu) From dcce7f8c75c466fd1a444f451dcfb3d2d16222e3 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:37 -0400 Subject: [PATCH 34/91] fmcomms2: intrs within ipi --- projects/fmcomms2/ac701/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/ac701/system_top.v b/projects/fmcomms2/ac701/system_top.v index 78d581ad7..41bddcb8c 100644 --- a/projects/fmcomms2/ac701/system_top.v +++ b/projects/fmcomms2/ac701/system_top.v @@ -249,10 +249,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -271,10 +267,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_io (phy_mdio), .mdio_mdc (phy_mdc), .phy_rst_n (phy_reset_n), From 06f6c58e8b488ee87365bb8e847e52daffa57210 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:44 -0400 Subject: [PATCH 35/91] fmcomms2: intrs within ipi --- projects/fmcomms2/kc705/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/kc705/system_top.v b/projects/fmcomms2/kc705/system_top.v index 6b6dd4372..40155f0b1 100644 --- a/projects/fmcomms2/kc705/system_top.v +++ b/projects/fmcomms2/kc705/system_top.v @@ -275,10 +275,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -297,10 +293,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), From 6e5186aa2d96d679ce1ff96b0d0b6eda7f8d99ef Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:49 -0400 Subject: [PATCH 36/91] fmcomms2: intrs within ipi --- projects/fmcomms2/mitx045/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/mitx045/system_top.v b/projects/fmcomms2/mitx045/system_top.v index 6139f4045..90c11a6f2 100644 --- a/projects/fmcomms2/mitx045/system_top.v +++ b/projects/fmcomms2/mitx045/system_top.v @@ -242,8 +242,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -252,8 +250,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From 1c32894333cff47197ea7586063265355aece05f Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:55 -0400 Subject: [PATCH 37/91] fmcomms2: intrs within ipi --- projects/fmcomms2/vc707/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v index 4058a3237..5a682959c 100644 --- a/projects/fmcomms2/vc707/system_top.v +++ b/projects/fmcomms2/vc707/system_top.v @@ -272,10 +272,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -294,10 +290,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mgt_clk_clk_n (mgt_clk_n), From 93328518e8dcecfcd20ae21ad7b41849b1277f74 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:03 -0400 Subject: [PATCH 38/91] fmcomms2: intrs within ipi --- projects/fmcomms2/zc702/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v index 5eba2dd0d..a4055aae7 100644 --- a/projects/fmcomms2/zc702/system_top.v +++ b/projects/fmcomms2/zc702/system_top.v @@ -236,8 +236,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -246,8 +244,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From 2a2e3366e70ba553dd752441afd77f8ea0505ecd Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:10 -0400 Subject: [PATCH 39/91] fmcomms2: intrs within ipi --- projects/fmcomms2/zc706/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index 5e95536b5..84f2a95d5 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -233,8 +233,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -243,8 +241,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From d9a1fea90ad5415f0ca798969d122f769f129876 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:16 -0400 Subject: [PATCH 40/91] fmcomms2: intrs within ipi --- projects/fmcomms2/zed/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 1f08eb0bb..9cef3446c 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -282,8 +282,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -292,8 +290,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .iic_fmc_intr(ps_intrs[11]), .otg_vbusoc (otg_vbusoc), .rx_clk_in_n (rx_clk_in_n), From bc68a4e9390fb98075b5aa686bf9d9be2ed74fcf Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:41 -0400 Subject: [PATCH 41/91] common-base-designs: add intr net names --- projects/common/ac701/ac701_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/ac701/ac701_system_bd.tcl b/projects/common/ac701/ac701_system_bd.tcl index 3be137cb8..243f7bcce 100644 --- a/projects/common/ac701/ac701_system_bd.tcl +++ b/projects/common/ac701/ac701_system_bd.tcl @@ -342,7 +342,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From 19c79e685b4b8adc508e2e857d400890ae89e9ae Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:50 -0400 Subject: [PATCH 42/91] common-base-designs: add intr net names --- projects/common/kc705/kc705_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/kc705/kc705_system_bd.tcl b/projects/common/kc705/kc705_system_bd.tcl index 386fa19d2..f93085a81 100644 --- a/projects/common/kc705/kc705_system_bd.tcl +++ b/projects/common/kc705/kc705_system_bd.tcl @@ -331,7 +331,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From bc837a67f03e7dde85d49303fdd13c588d6b5a1d Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:55:59 -0400 Subject: [PATCH 43/91] common-base-designs: add intr net names --- projects/common/mitx045/mitx045_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/mitx045/mitx045_system_bd.tcl b/projects/common/mitx045/mitx045_system_bd.tcl index e8cf2d339..b38b19cec 100755 --- a/projects/common/mitx045/mitx045_system_bd.tcl +++ b/projects/common/mitx045/mitx045_system_bd.tcl @@ -237,7 +237,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From 4931bca1f7a73537adcf0b89c92d72e40542492b Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:06 -0400 Subject: [PATCH 44/91] common-base-designs: add intr net names --- projects/common/vc707/vc707_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/vc707/vc707_system_bd.tcl b/projects/common/vc707/vc707_system_bd.tcl index 36d339c54..da1544056 100644 --- a/projects/common/vc707/vc707_system_bd.tcl +++ b/projects/common/vc707/vc707_system_bd.tcl @@ -354,7 +354,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2 for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I -type intr mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (external interface) From d767e590e8cfbb9eab1f55f9ee127f9b29b0650c Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:15 -0400 Subject: [PATCH 45/91] common-base-designs: add intr net names --- projects/common/zc702/zc702_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc702/zc702_system_bd.tcl b/projects/common/zc702/zc702_system_bd.tcl index 694c13417..462ab6f12 100644 --- a/projects/common/zc702/zc702_system_bd.tcl +++ b/projects/common/zc702/zc702_system_bd.tcl @@ -198,7 +198,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From e689471ee60b52630477b71de289fa6144e92df8 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:25 -0400 Subject: [PATCH 46/91] common-base-designs: add intr net names --- projects/common/zc706/zc706_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zc706/zc706_system_bd.tcl b/projects/common/zc706/zc706_system_bd.tcl index f1f9c2d33..81561c413 100644 --- a/projects/common/zc706/zc706_system_bd.tcl +++ b/projects/common/zc706/zc706_system_bd.tcl @@ -201,7 +201,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From e4494efc91b36018e8ba731cf51952f5b2e35dab Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:56:31 -0400 Subject: [PATCH 47/91] common-base-designs: add intr net names --- projects/common/zed/zed_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 83080b1a0..008895515 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -285,7 +285,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In14] [get_bd_pins axi_iic_main/iic2 for {set intc_index 0} {$intc_index < 14} {incr intc_index} { set ps_intr_${intc_index} [create_bd_port -dir I ps_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] + connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } # address map From 6ee02f7ade992ae03eb9b026b38eae05f7022e86 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:57:35 -0400 Subject: [PATCH 48/91] fmcomms2: intrs within ipi --- projects/fmcomms2/common/fmcomms2_bd.tcl | 29 ++++++++++++------------ 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index c9814c302..7ee03021a 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -42,16 +42,6 @@ if {$sys_zynq == 1} { set spi_udc_miso_i [create_bd_port -dir I spi_udc_miso_i] } - # interrupts - - set ad9361_adc_dma_irq [create_bd_port -dir O ad9361_adc_dma_irq] - set ad9361_dac_dma_irq [create_bd_port -dir O ad9361_dac_dma_irq] - -if {$sys_zynq == 0} { - set fmcomms2_gpio_irq [create_bd_port -dir O fmcomms2_gpio_irq] - set fmcomms2_spi_irq [create_bd_port -dir O fmcomms2_spi_irq] -} - # ad9361 core set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361] @@ -161,7 +151,6 @@ if {$sys_zynq == 0} { connect_bd_net -net spi_mosi_i [get_bd_ports spi_mosi_i] [get_bd_pins axi_fmcomms2_spi/io0_i] connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins axi_fmcomms2_spi/io0_o] connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins axi_fmcomms2_spi/io1_i] - connect_bd_net -net axi_fmcomms2_spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_ports fmcomms2_spi_irq] } else { connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] connect_bd_net -net spi_csn_o [get_bd_ports spi_csn_o] [get_bd_pins sys_ps7/SPI0_SS_O] @@ -178,7 +167,6 @@ if {$sys_zynq == 0} { connect_bd_net -net gpio_fmcomms2_i [get_bd_ports gpio_fmcomms2_i] [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] connect_bd_net -net gpio_fmcomms2_o [get_bd_ports gpio_fmcomms2_o] [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] connect_bd_net -net gpio_fmcomms2_t [get_bd_ports gpio_fmcomms2_t] [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] - connect_bd_net -net axi_fmcomms2_gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_ports fmcomms2_gpio_irq] } # connections (up/down converter spi) @@ -251,8 +239,21 @@ if {$sys_zynq == 1} { connect_bd_net -net axi_ad9361_dac_drd [get_bd_pins util_dac_unpack/dma_rd] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] connect_bd_net -net axi_ad9361_dac_dunf [get_bd_pins axi_ad9361/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins ad9361_adc_dma_irq] - connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins ad9361_dac_dma_irq] + if {$sys_zynq == 0} { + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_fmcomms2_spi_irq [get_bd_pins sys_concat_intc/In10] [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] + connect_bd_net -net axi_fmcomms2_gpio_irq [get_bd_pins sys_concat_intc/In11] [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9361_adc_dma/irq] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins sys_concat_intc/In13] [get_bd_pins axi_ad9361_dac_dma/irq] + } else { + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9361_dac_dma/irq] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins sys_concat_intc/In13] [get_bd_pins axi_ad9361_adc_dma/irq] + } # interconnect (cpu) From 15a0de80a933d687cca2552898f422bf0d0c2024 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:37 -0400 Subject: [PATCH 49/91] fmcomms2: intrs within ipi --- projects/fmcomms2/ac701/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/ac701/system_top.v b/projects/fmcomms2/ac701/system_top.v index 78d581ad7..41bddcb8c 100644 --- a/projects/fmcomms2/ac701/system_top.v +++ b/projects/fmcomms2/ac701/system_top.v @@ -249,10 +249,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -271,10 +267,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_io (phy_mdio), .mdio_mdc (phy_mdc), .phy_rst_n (phy_reset_n), From 0fcd47f5ea8b7a2823eb27463dc4d04e40ecdf45 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:44 -0400 Subject: [PATCH 50/91] fmcomms2: intrs within ipi --- projects/fmcomms2/kc705/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/kc705/system_top.v b/projects/fmcomms2/kc705/system_top.v index 6b6dd4372..40155f0b1 100644 --- a/projects/fmcomms2/kc705/system_top.v +++ b/projects/fmcomms2/kc705/system_top.v @@ -275,10 +275,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -297,10 +293,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), From 5faced7eaa13e76bb33d8a6bcc8e226a0d033c13 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:49 -0400 Subject: [PATCH 51/91] fmcomms2: intrs within ipi --- projects/fmcomms2/mitx045/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/mitx045/system_top.v b/projects/fmcomms2/mitx045/system_top.v index 6139f4045..90c11a6f2 100644 --- a/projects/fmcomms2/mitx045/system_top.v +++ b/projects/fmcomms2/mitx045/system_top.v @@ -242,8 +242,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -252,8 +250,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From 70e5d5c13970af3976956a3bc2de0d3c27dc0b12 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:58:55 -0400 Subject: [PATCH 52/91] fmcomms2: intrs within ipi --- projects/fmcomms2/vc707/system_top.v | 8 -------- 1 file changed, 8 deletions(-) diff --git a/projects/fmcomms2/vc707/system_top.v b/projects/fmcomms2/vc707/system_top.v index 4058a3237..5a682959c 100644 --- a/projects/fmcomms2/vc707/system_top.v +++ b/projects/fmcomms2/vc707/system_top.v @@ -272,10 +272,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -294,10 +290,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .fmcomms2_spi_irq(mb_intrs[10]), - .fmcomms2_gpio_irq(mb_intrs[11]), - .ad9361_adc_dma_irq (mb_intrs[12]), - .ad9361_dac_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mgt_clk_clk_n (mgt_clk_n), From a9b5e07e76e65858df287d0e3b3147158357126d Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:03 -0400 Subject: [PATCH 53/91] fmcomms2: intrs within ipi --- projects/fmcomms2/zc702/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zc702/system_top.v b/projects/fmcomms2/zc702/system_top.v index 5eba2dd0d..a4055aae7 100644 --- a/projects/fmcomms2/zc702/system_top.v +++ b/projects/fmcomms2/zc702/system_top.v @@ -236,8 +236,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -246,8 +244,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From c5fcec1f2f326c487a2228f59ef932dd95207c22 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:10 -0400 Subject: [PATCH 54/91] fmcomms2: intrs within ipi --- projects/fmcomms2/zc706/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zc706/system_top.v b/projects/fmcomms2/zc706/system_top.v index 5e95536b5..84f2a95d5 100644 --- a/projects/fmcomms2/zc706/system_top.v +++ b/projects/fmcomms2/zc706/system_top.v @@ -233,8 +233,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -243,8 +241,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From fac1434dccf6969f34b61498000cada26f72e5ac Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 12 Mar 2015 15:59:16 -0400 Subject: [PATCH 55/91] fmcomms2: intrs within ipi --- projects/fmcomms2/zed/system_top.v | 4 ---- 1 file changed, 4 deletions(-) diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 1f08eb0bb..9cef3446c 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -282,8 +282,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -292,8 +290,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .iic_fmc_intr(ps_intrs[11]), .otg_vbusoc (otg_vbusoc), .rx_clk_in_n (rx_clk_in_n), From c99d7a2da3475539d8b23bc8d5391cb4e15c80ab Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:35:15 +0200 Subject: [PATCH 56/91] ad6676evb: Updated project with interrupts in IPI to work correctly in Linux --- projects/ad6676evb/common/ad6676evb_bd.tcl | 26 ++++++++++++++++------ projects/ad6676evb/vc707/system_top.v | 6 ----- projects/ad6676evb/zc706/system_top.v | 4 ---- 3 files changed, 19 insertions(+), 17 deletions(-) diff --git a/projects/ad6676evb/common/ad6676evb_bd.tcl b/projects/ad6676evb/common/ad6676evb_bd.tcl index 1fa016a4b..f39b0d173 100644 --- a/projects/ad6676evb/common/ad6676evb_bd.tcl +++ b/projects/ad6676evb/common/ad6676evb_bd.tcl @@ -26,10 +26,6 @@ set dma_wr [create_bd_port -dir I dma_wr] set dma_sync [create_bd_port -dir I dma_sync] set dma_data [create_bd_port -dir I -from 63 -to 0 dma_data] -set ad6676_spi_intr [create_bd_port -dir O ad6676_spi_intr] -set ad6676_gpio_intr [create_bd_port -dir O ad6676_gpio_intr] -set ad6676_dma_intr [create_bd_port -dir O ad6676_dma_intr] - if {$sys_zynq == 0} { set gpio_ctl_i [create_bd_port -dir I -from 4 -to 0 gpio_ctl_i] @@ -187,7 +183,25 @@ connect_bd_net -net axi_ad6676_dma_wr [get_bd_pins axi_ad6676_dma/ connect_bd_net -net axi_ad6676_dma_sync [get_bd_pins axi_ad6676_dma/fifo_wr_sync] [get_bd_ports dma_sync] connect_bd_net -net axi_ad6676_dma_data [get_bd_pins axi_ad6676_dma/fifo_wr_din] [get_bd_ports dma_data] connect_bd_net -net axi_ad6676_adc_dovf [get_bd_pins axi_ad6676_core/adc_dovf] [get_bd_pins axi_ad6676_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad6676_dma_intr [get_bd_pins axi_ad6676_dma/irq] [get_bd_ports ad6676_dma_intr] + +# interrupts + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + delete_bd_objs [get_bd_nets mb_intr_14_s] [get_bd_ports mb_intr_14] + connect_bd_net -net axi_ad6676_dma_intr [get_bd_pins axi_ad6676_dma/irq] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_ad6676_spi_intr [get_bd_pins axi_ad6676_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In13] + connect_bd_net -net axi_ad6676_gpio_intr [get_bd_pins axi_ad6676_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In14] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad6676_dma_intr [get_bd_pins axi_ad6676_dma/irq] [get_bd_pins sys_concat_intc/In13] + +} + # interconnect (cpu) @@ -226,8 +240,6 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_spi/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad6676_gpio/s_axi_aresetn] - connect_bd_net -net axi_ad6676_spi_intr [get_bd_pins axi_ad6676_spi/ip2intc_irpt] [get_bd_pins ad6676_spi_intr] - connect_bd_net -net axi_ad6676_gpio_intr [get_bd_pins axi_ad6676_gpio/ip2intc_irpt] [get_bd_pins ad6676_gpio_intr] } # gt uses hp3, and 100MHz clock for both DRP and AXI4 diff --git a/projects/ad6676evb/vc707/system_top.v b/projects/ad6676evb/vc707/system_top.v index 76f146059..54f5caa82 100644 --- a/projects/ad6676evb/vc707/system_top.v +++ b/projects/ad6676evb/vc707/system_top.v @@ -296,11 +296,8 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), .mb_intr_11 (mb_intrs[11]), .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), - .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), .mb_intr_17 (mb_intrs[17]), @@ -318,9 +315,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad6676_spi_intr (mb_intrs[13]), - .ad6676_gpio_intr (mb_intrs[14]), - .ad6676_dma_intr (mb_intrs[10]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mgt_clk_clk_n (mgt_clk_n), diff --git a/projects/ad6676evb/zc706/system_top.v b/projects/ad6676evb/zc706/system_top.v index a7a1e04a8..7f687ffda 100644 --- a/projects/ad6676evb/zc706/system_top.v +++ b/projects/ad6676evb/zc706/system_top.v @@ -278,9 +278,6 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), - .ad6676_dma_intr (ps_intrs[13]), - .ad6676_gpio_intr (), - .ad6676_spi_intr (), .adc_clk (adc_clk), .adc_data_a (adc_data_a), .adc_data_b (adc_data_b), @@ -303,7 +300,6 @@ module system_top ( .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), From f7c2c3818fa79c1c69ccaf09b56f57d7f31d69c1 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:37:17 +0200 Subject: [PATCH 57/91] ad9265_fmc: Updated project with interrupts in IPI to work correctly in Linux --- projects/ad9265_fmc/common/ad9265_bd.tcl | 18 +++++++++++------- projects/ad9265_fmc/zc706/system_top.v | 5 +---- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl index 777bd7a1a..ad14b6da3 100644 --- a/projects/ad9265_fmc/common/ad9265_bd.tcl +++ b/projects/ad9265_fmc/common/ad9265_bd.tcl @@ -19,11 +19,6 @@ set spi_sdo_o [create_bd_port -dir O spi_sdo_o] set spi_sdo_i [create_bd_port -dir I spi_sdo_i] set spi_sdi_i [create_bd_port -dir I spi_sdi_i] -# interrupts - -set ad9265_spi [create_bd_port -dir O ad9265_spi] -set ad9265_dma_irq [create_bd_port -dir O ad9265_dma_irq] - # adc peripheral set axi_ad9265 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9265:1.0 axi_ad9265] @@ -139,7 +134,6 @@ connect_bd_net -net axi_ad9265_dma_valid [get_bd_pins axi_ad9265/adc_valid connect_bd_net -net axi_ad9265_dma_data [get_bd_pins axi_ad9265/adc_data] [get_bd_pins axi_ad9265_dma/fifo_wr_din] connect_bd_net -net axi_ad9265_dma_dovf [get_bd_pins axi_ad9265/adc_dovf] [get_bd_pins axi_ad9265_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports ad9265_dma_irq] # interconnect (cpu) @@ -164,8 +158,18 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9265_spi/ext_spi_clk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9265_spi/s_axi_aresetn] +} - connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_ports ad9265_spi] +# interrupts + +if {$sys_zynq == 0} { + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_ports sys_concat_intc/In10] + connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports sys_concat_intc/In12] +} else { + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports sys_concat_intc/In12] } # interconnect (mem/adc) diff --git a/projects/ad9265_fmc/zc706/system_top.v b/projects/ad9265_fmc/zc706/system_top.v index 4b01ddea5..aa06ad7d4 100644 --- a/projects/ad9265_fmc/zc706/system_top.v +++ b/projects/ad9265_fmc/zc706/system_top.v @@ -198,11 +198,10 @@ system_wrapper i_system_wrapper ( .iic_main_sda_io (iic_sda), .ps_intr_0 (ps_intrs[0]), .ps_intr_1 (ps_intrs[1]), + .ps_intr_2 (ps_intrs[2]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), .ps_intr_13 (ps_intrs[13]), - .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), .ps_intr_5 (ps_intrs[5]), @@ -210,8 +209,6 @@ system_wrapper i_system_wrapper ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9265_spi (ps_intrs[2]), - .ad9265_dma_irq (ps_intrs[12]), .spdif (spdif), .adc_clk_in_n(adc_clk_in_n), .adc_clk_in_p(adc_clk_in_p), From 7b3e8d33db05d04d4bb315ca0c147cd33245a93f Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:38:21 +0200 Subject: [PATCH 58/91] ad9436_fmc: Updated project with interrupts in IPI to work correctly in Linux --- projects/ad9434_fmc/common/ad9434_bd.tcl | 8 ++++---- projects/ad9434_fmc/zc706/system_top.v | 2 -- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/projects/ad9434_fmc/common/ad9434_bd.tcl b/projects/ad9434_fmc/common/ad9434_bd.tcl index 74e89b8d8..84223ba34 100644 --- a/projects/ad9434_fmc/common/ad9434_bd.tcl +++ b/projects/ad9434_fmc/common/ad9434_bd.tcl @@ -18,9 +18,6 @@ set spi_mosi_i [create_bd_port -dir I spi_mosi_i] set spi_mosi_o [create_bd_port -dir O spi_mosi_o] set spi_miso_i [create_bd_port -dir I spi_miso_i] -# interrupts -set ad9434_dma_intr [create_bd_port -dir O ad9434_dma_intr] - # ad9434 set axi_ad9434 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9434:1.0 axi_ad9434] @@ -89,7 +86,10 @@ connect_bd_net -net axi_ad9434_denable [get_bd_pins axi_ad9434/adc_valid] [g connect_bd_net -net axi_ad9434_data [get_bd_pins axi_ad9434/adc_data] [get_bd_pins axi_ad9434_dma/fifo_wr_din] connect_bd_net -net axi_ad9434_ovf [get_bd_pins axi_ad9434/adc_dovf] [get_bd_pins axi_ad9434_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9434_dma_irq [get_bd_pins axi_ad9434_dma/irq] [get_bd_ports ad9434_dma_intr] +# interrupts + +delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] +connect_bd_net -net axi_ad9434_dma_irq [get_bd_pins axi_ad9434_dma/irq] [get_bd_pins sys_concat_intc/In13] # cpu interconnect diff --git a/projects/ad9434_fmc/zc706/system_top.v b/projects/ad9434_fmc/zc706/system_top.v index a3f8cf397..5365e21d3 100644 --- a/projects/ad9434_fmc/zc706/system_top.v +++ b/projects/ad9434_fmc/zc706/system_top.v @@ -216,8 +216,6 @@ module system_top ( .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), - .ad9434_dma_intr (ps_intrs[13]), .spdif (spdif), .adc_clk_p(adc_clk_p), .adc_clk_n(adc_clk_n), From 5fbb929d5b75edb281d2f4ada110644cb8cc3603 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:39:28 +0200 Subject: [PATCH 59/91] ad9671_fmc: Updated project with interrupts in IPI to work correctly in Linux --- projects/ad9671_fmc/common/ad9671_fmc_bd.tcl | 10 +++++----- projects/ad9671_fmc/zc706/system_top.v | 2 -- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl index d542e1db9..26574b649 100755 --- a/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl +++ b/projects/ad9671_fmc/common/ad9671_fmc_bd.tcl @@ -28,10 +28,6 @@ set dma_wr [create_bd_port -dir I dma_wr] set dma_sync [create_bd_port -dir I dma_sync] set dma_data [create_bd_port -dir I -from 127 -to 0 dma_data] -# interrupts - -set ad9671_dma_irq [create_bd_port -dir O ad9671_dma_irq] - # adc peripherals set axi_ad9671_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core] @@ -138,7 +134,11 @@ connect_bd_net -net axi_ad9671_core_adc_dwr [get_bd_ports dma_wr] connect_bd_net -net axi_ad9671_core_adc_dsync [get_bd_ports dma_sync] [get_bd_pins axi_ad9671_dma/fifo_wr_sync] connect_bd_net -net axi_ad9671_core_adc_ddata [get_bd_ports dma_data] [get_bd_pins axi_ad9671_dma/fifo_wr_din] connect_bd_net -net axi_ad9671_core_adc_dovf [get_bd_pins axi_ad9671_core/adc_dovf] [get_bd_pins axi_ad9671_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_ports ad9671_dma_irq] + +# interrupt + +delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] +connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_ad9671_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/ad9671_fmc/zc706/system_top.v b/projects/ad9671_fmc/zc706/system_top.v index 02983d9dd..cddb3996e 100644 --- a/projects/ad9671_fmc/zc706/system_top.v +++ b/projects/ad9671_fmc/zc706/system_top.v @@ -315,8 +315,6 @@ module system_top ( .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), - .ad9671_dma_irq (ps_intrs[13]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From cdd89650358273421a2c5e78e5a292c523eed8e9 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:40:52 +0200 Subject: [PATCH 60/91] ad9739a_fmc: Updated project with interrupts in IPI to work correctly in Linux --- projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl | 10 +++++----- projects/ad9739a_fmc/zc706/system_top.v | 2 -- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl index f4a198b42..c4f5ca311 100644 --- a/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl +++ b/projects/ad9739a_fmc/common/ad9739a_fmc_bd.tcl @@ -19,10 +19,6 @@ set spi_sdo_o [create_bd_port -dir O spi_sdo_o] set spi_sdi_i [create_bd_port -dir I spi_sdi_i] - # interrupts - - set ad9739a_dma_irq [create_bd_port -dir O ad9739a_dma_irq] - # dac peripherals set axi_ad9739a [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9739a:1.0 axi_ad9739a] @@ -60,7 +56,11 @@ connect_bd_net -net axi_ad9739a_dac_valid [get_bd_pins axi_ad9739a/dac_valid] [get_bd_pins axi_ad9739a_dma/fifo_rd_en] connect_bd_net -net axi_ad9739a_dac_ddata [get_bd_pins axi_ad9739a/dac_ddata] [get_bd_pins axi_ad9739a_dma/fifo_rd_dout] connect_bd_net -net axi_ad9739a_dac_dunf [get_bd_pins axi_ad9739a/dac_dunf] [get_bd_pins axi_ad9739a_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9739a_dma_irq [get_bd_pins axi_ad9739a_dma/irq] [get_bd_ports ad9739a_dma_irq] + + #interrupt + + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + connect_bd_net -net axi_ad9739a_dma_irq [get_bd_pins axi_ad9739a_dma/irq] [get_bd_pins sys_concat_intc/In12] # interconnect (cpu) diff --git a/projects/ad9739a_fmc/zc706/system_top.v b/projects/ad9739a_fmc/zc706/system_top.v index 2047fbdb9..f70182ff0 100644 --- a/projects/ad9739a_fmc/zc706/system_top.v +++ b/projects/ad9739a_fmc/zc706/system_top.v @@ -183,7 +183,6 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), - .ad9739a_dma_irq (ps_intrs[12]), .dac_clk_in_n (dac_clk_in_n), .dac_clk_in_p (dac_clk_in_p), .dac_clk_out_n (dac_clk_out_n), @@ -203,7 +202,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), From 1edec41cf8f5fea26b7eb432f12f3863204f48d4 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:41:51 +0200 Subject: [PATCH 61/91] daq1: Updated project with interrupts in IPI to work correctly in Linux --- projects/daq1/common/daq1_bd.tcl | 10 +++++++--- projects/daq1/zc706/system_top.v | 4 ---- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index aeb2325fd..249258dad 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -50,7 +50,6 @@ set tx_data_n [create_bd_port -dir O -from 15 -to 0 tx_data_n] # interrupts -set ad9250_dma_irq [create_bd_port -dir O ad9250_dma_irq] set ad9122_dma_irq [create_bd_port -dir O ad9122_dma_irq] # dac peripherals @@ -181,7 +180,6 @@ connect_bd_net -net axi_ad9250_adc_dovf [get_bd_pins axi_ad9250_core/a connect_bd_net -net axi_ad9250_dma_wr [get_bd_pins axi_ad9250_dma/fifo_wr_en] [get_bd_ports adc_dwr] connect_bd_net -net axi_ad9250_dma_sync [get_bd_pins axi_ad9250_dma/fifo_wr_sync] [get_bd_ports adc_dsync] connect_bd_net -net axi_ad9250_dma_data [get_bd_pins axi_ad9250_dma/fifo_wr_din] [get_bd_ports adc_ddata] -connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_ports ad9250_dma_irq] connect_bd_net -net axi_ad9250_adc_clk [get_bd_ports adc_clk] @@ -205,10 +203,16 @@ connect_bd_net -net axi_ad9122_dac_ddata_1 [get_bd_pins axi_ad9122_core/d connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_drd] connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_ddata] connect_bd_net -net axi_ad9122_dac_dunf [get_bd_pins axi_ad9122_core/dac_dunf] [get_bd_pins axi_ad9122_dma/fifo_rd_underflow] -connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_ports ad9122_dma_irq] connect_bd_net -net axi_ad9122_dac_div_clk [get_bd_ports dac_clk] +# interrupts + +delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] +delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] +connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12] +connect_bd_net -net axi_ad9250_dma_irq [get_bd_pins axi_ad9250_dma/irq] [get_bd_pins sys_concat_intc/In13] + # interconnect (cpu) connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_ad9122_dma/s_axi] diff --git a/projects/daq1/zc706/system_top.v b/projects/daq1/zc706/system_top.v index fe4965690..6991ab9da 100644 --- a/projects/daq1/zc706/system_top.v +++ b/projects/daq1/zc706/system_top.v @@ -373,8 +373,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -383,8 +381,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9250_dma_irq (ps_intrs[13]), - .ad9122_dma_irq (ps_intrs[12]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From 7dfdbe4e054fa8d88b40d968c178139b245115c8 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:42:34 +0200 Subject: [PATCH 62/91] daq3: Updated project with interrupts in IPI to work correctly in Linux --- projects/daq3/common/daq3_bd.tcl | 28 +++++++++++++++++++--------- projects/daq3/zc706/system_top.v | 4 ---- 2 files changed, 19 insertions(+), 13 deletions(-) diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index 59347bd53..1e55dea89 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -63,11 +63,6 @@ if {$sys_zynq == 0} { set adc_dsync [create_bd_port -dir I adc_dsync] set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] - set axi_ad9152_dma_intr [create_bd_port -dir O axi_ad9152_dma_intr] - set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr] - set axi_daq3_spi_intr [create_bd_port -dir O axi_daq3_spi_intr ] - set axi_daq3_gpio_intr [create_bd_port -dir O axi_daq3_gpio_intr ] - # dac peripherals set axi_ad9152_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9152:1.0 axi_ad9152_core] @@ -262,7 +257,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9152_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9152_dma/fifo_rd_en] connect_bd_net -net axi_ad9152_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9152_dma/fifo_rd_dout] connect_bd_net -net axi_ad9152_dac_dunf [get_bd_pins axi_ad9152_core/dac_dunf] [get_bd_pins axi_ad9152_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9152_dma_intr [get_bd_pins axi_ad9152_dma/irq] [get_bd_ports axi_ad9152_dma_intr] # connections (adc) @@ -302,7 +296,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data] connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready] connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_fifo/dma_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req] - connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr] # dac/adc clocks @@ -360,9 +353,26 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M15_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_spi/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq3_gpio/s_axi_aresetn] +} + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_daq3_spi_intr [get_bd_pins axi_daq3_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_daq3_gpio_intr [get_bd_pins axi_daq3_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net axi_ad9152_dma_intr [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9152_dma_intr [get_bd_pins axi_ad9152_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] - connect_bd_net -net axi_daq3_spi_intr [get_bd_pins axi_daq3_spi/ip2intc_irpt] [get_bd_ports axi_daq3_spi_intr] - connect_bd_net -net axi_daq3_gpio_intr [get_bd_pins axi_daq3_gpio/ip2intc_irpt] [get_bd_ports axi_daq3_gpio_intr] } # gt uses hp3, and 100MHz clock for both DRP and AXI4 diff --git a/projects/daq3/zc706/system_top.v b/projects/daq3/zc706/system_top.v index 03262dac8..b3d0de231 100644 --- a/projects/daq3/zc706/system_top.v +++ b/projects/daq3/zc706/system_top.v @@ -512,8 +512,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -522,8 +520,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .axi_ad9152_dma_intr (ps_intrs[12]), - .axi_ad9680_dma_intr (ps_intrs[13]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From 78b0ed0de6c424444a6a5f9810bcd195e846c6b3 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:43:16 +0200 Subject: [PATCH 63/91] fmcadc2: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcadc2/common/fmcadc2_bd.tcl | 25 ++++++++++++++++++------- projects/fmcadc2/vc707/system_top.v | 6 ------ projects/fmcadc2/zc706/system_top.v | 4 ---- 3 files changed, 18 insertions(+), 17 deletions(-) diff --git a/projects/fmcadc2/common/fmcadc2_bd.tcl b/projects/fmcadc2/common/fmcadc2_bd.tcl index e3333370d..b7ae3a713 100644 --- a/projects/fmcadc2/common/fmcadc2_bd.tcl +++ b/projects/fmcadc2/common/fmcadc2_bd.tcl @@ -25,10 +25,6 @@ set rx_sysref [create_bd_port -dir O rx_sysref] set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] -set ad9625_spi_intr [create_bd_port -dir O ad9625_spi_intr] -set ad9625_gpio_intr [create_bd_port -dir O ad9625_gpio_intr] -set ad9625_dma_intr [create_bd_port -dir O ad9625_dma_intr] - if {$sys_zynq == 0} { set gpio_ad9625_i [create_bd_port -dir I -from 2 -to 0 gpio_ad9625_i] @@ -143,8 +139,24 @@ if {$sys_zynq == 1 } { connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o] connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t] - connect_bd_net -net axi_ad9625_spi_intr [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_ports ad9625_spi_intr] - connect_bd_net -net axi_ad9625_gpio_intr [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_ports ad9625_gpio_intr] +} + +# interrupts + +if {$sys_zynq == 0 } { + + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + delete_bd_objs [get_bd_nets mb_intr_14_s] [get_bd_ports mb_intr_14] + connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_ad9625_spi_intr [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In13] + connect_bd_net -net axi_ad9625_gpio_intr [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In14] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13] + } # connections (gt) @@ -187,7 +199,6 @@ connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fifo connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data] connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready] connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_fifo/dma_xfer_req] [get_bd_pins axi_ad9625_dma/s_axis_xfer_req] -connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_ports ad9625_dma_intr] # interconnect (cpu) diff --git a/projects/fmcadc2/vc707/system_top.v b/projects/fmcadc2/vc707/system_top.v index b06c5771d..4e7708620 100644 --- a/projects/fmcadc2/vc707/system_top.v +++ b/projects/fmcadc2/vc707/system_top.v @@ -254,9 +254,6 @@ module system_top ( assign fan_pwm = 1'b1; system_wrapper i_system_wrapper ( - .ad9625_dma_intr (mb_intrs[10]), - .ad9625_gpio_intr (mb_intrs[14]), - .ad9625_spi_intr (mb_intrs[13]), .ddr3_addr (ddr3_addr), .ddr3_ba (ddr3_ba), .ddr3_cas_n (ddr3_cas_n), @@ -289,11 +286,8 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), .mb_intr_11 (mb_intrs[11]), .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), - .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), .mb_intr_17 (mb_intrs[17]), diff --git a/projects/fmcadc2/zc706/system_top.v b/projects/fmcadc2/zc706/system_top.v index 9b9ae294b..439e23d60 100644 --- a/projects/fmcadc2/zc706/system_top.v +++ b/projects/fmcadc2/zc706/system_top.v @@ -286,9 +286,6 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), - .ad9625_dma_intr (ps_intrs[13]), - .ad9625_gpio_intr (), - .ad9625_spi_intr (), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), @@ -301,7 +298,6 @@ module system_top ( .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), From f9da2f31a6087a1305675753a9142cdf2cb8c719 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 17 Mar 2015 17:44:01 +0200 Subject: [PATCH 64/91] fmcadc4: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcadc4/common/fmcadc4_bd.tcl | 25 ++++++++++++++++++------- projects/fmcadc4/zc706/system_top.v | 2 -- 2 files changed, 18 insertions(+), 9 deletions(-) diff --git a/projects/fmcadc4/common/fmcadc4_bd.tcl b/projects/fmcadc4/common/fmcadc4_bd.tcl index 2b1aa1eef..ad0de54f5 100644 --- a/projects/fmcadc4/common/fmcadc4_bd.tcl +++ b/projects/fmcadc4/common/fmcadc4_bd.tcl @@ -56,10 +56,6 @@ if {$sys_zynq == 0} { set adc_dsync [create_bd_port -dir I adc_dsync] set adc_ddata [create_bd_port -dir I -from 255 -to 0 adc_ddata] - set fmcadc4_dma_intr [create_bd_port -dir O fmcadc4_dma_intr] - set fmcadc4_spi_intr [create_bd_port -dir O fmcadc4_spi_intr] - set fmcadc4_gpio_intr [create_bd_port -dir O fmcadc4_gpio_intr] - # adc peripherals set axi_ad9234_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9234:1.0 axi_ad9234_core_0] @@ -239,7 +235,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9234_dma_ddata [get_bd_pins axi_ad9234_fifo/dma_wdata] [get_bd_pins axi_ad9234_dma/s_axis_data] connect_bd_net -net axi_ad9234_dma_dready [get_bd_pins axi_ad9234_fifo/dma_wready] [get_bd_pins axi_ad9234_dma/s_axis_ready] connect_bd_net -net axi_ad9234_dma_xfer_req [get_bd_pins axi_ad9234_fifo/dma_xfer_req] [get_bd_pins axi_ad9234_dma/s_axis_xfer_req] - connect_bd_net -net fmcadc4_dma_intr [get_bd_pins axi_ad9234_dma/irq] [get_bd_ports fmcadc4_dma_intr] # dac/adc clocks @@ -287,8 +282,24 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_spi/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcadc4_gpio/s_axi_aresetn] - connect_bd_net -net axi_fmcadc4_spi_irq [get_bd_pins axi_fmcadc4_spi/ip2intc_irpt] [get_bd_ports fmcadc4_spi_intr] - connect_bd_net -net axi_fmcadc4_gpio_irq [get_bd_pins axi_fmcadc4_gpio/ip2intc_irpt] [get_bd_ports fmcadc4_gpio_intr] +} + + # interrupts + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + connect_bd_net -net axi_fmcadc4_spi_irq [get_bd_pins axi_fmcadc4_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_fmcadc4_gpio_irq [get_bd_pins axi_fmcadc4_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net fmcadc4_dma_intr [get_bd_pins axi_ad9234_dma/irq] [get_bd_pins sys_concat_intc/In12] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + connect_bd_net -net fmcadc4_dma_intr [get_bd_pins axi_ad9234_dma/irq] [get_bd_pins sys_concat_intc/In12] + } # gt uses hp3, and 100MHz clock for both DRP and AXI4 diff --git a/projects/fmcadc4/zc706/system_top.v b/projects/fmcadc4/zc706/system_top.v index eb35c5767..2e826f80a 100644 --- a/projects/fmcadc4/zc706/system_top.v +++ b/projects/fmcadc4/zc706/system_top.v @@ -525,7 +525,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), @@ -535,7 +534,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .fmcadc4_dma_intr (ps_intrs[12]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From d20934b7aec875f3752b36caf1432f6eb893c107 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 12:58:11 +0200 Subject: [PATCH 65/91] ad9467_fmc: Updated project with interrupts in IPI to work correctly in Linux --- projects/ad9467_fmc/common/ad9467_bd.tcl | 19 +++++++++++-------- projects/ad9467_fmc/kc705/system_top.v | 4 ---- projects/ad9467_fmc/zed/system_top.v | 3 --- 3 files changed, 11 insertions(+), 15 deletions(-) diff --git a/projects/ad9467_fmc/common/ad9467_bd.tcl b/projects/ad9467_fmc/common/ad9467_bd.tcl index 471a63eff..a52d831ba 100644 --- a/projects/ad9467_fmc/common/ad9467_bd.tcl +++ b/projects/ad9467_fmc/common/ad9467_bd.tcl @@ -21,12 +21,6 @@ if {$sys_zynq == 0} { set spi_sdo_i [create_bd_port -dir I spi_sdo_i] set spi_sdi_i [create_bd_port -dir I spi_sdi_i] - # interrupts - set ad9467_dma_irq [create_bd_port -dir O ad9467_dma_irq] -if {$sys_zynq == 0} { - set ad9467_spi_irq [create_bd_port -dir O ad9467_spi_irq] -} - # adc peripheral set axi_ad9467 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9467:1.0 axi_ad9467] @@ -143,7 +137,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9467_dma_ddata [get_bd_pins axi_ad9467/adc_data] [get_bd_pins axi_ad9467_dma/fifo_wr_din] connect_bd_net -net axi_ad9467_dma_dovf [get_bd_pins axi_ad9467/adc_dovf] [get_bd_pins axi_ad9467_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_ports ad9467_dma_irq] # interconnect (cpu) @@ -168,8 +161,18 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_clk [get_bd_pins axi_ad9467_spi/ext_spi_clk] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M09_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_ad9467_spi/s_axi_aresetn] +} - connect_bd_net -net axi_ad9467_spi_irq [get_bd_pins axi_ad9467_spi/ip2intc_irpt] [get_bd_ports ad9467_spi_irq] + # interrupts + +if {$sys_zynq == 0} { + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_ad9467_spi_irq [get_bd_pins axi_ad9467_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In13] +} else { + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9467_dma_irq [get_bd_pins axi_ad9467_dma/irq] [get_bd_pins sys_concat_intc/In13] } # interconnect (mem/adc) diff --git a/projects/ad9467_fmc/kc705/system_top.v b/projects/ad9467_fmc/kc705/system_top.v index c25641b16..3c2612c0c 100644 --- a/projects/ad9467_fmc/kc705/system_top.v +++ b/projects/ad9467_fmc/kc705/system_top.v @@ -236,10 +236,8 @@ system_wrapper i_system_wrapper ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), .mb_intr_11 (mb_intrs[11]), .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -258,8 +256,6 @@ system_wrapper i_system_wrapper ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9467_dma_irq (mb_intrs[10]), - .ad9467_spi_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), diff --git a/projects/ad9467_fmc/zed/system_top.v b/projects/ad9467_fmc/zed/system_top.v index b41f45859..9d69251d1 100644 --- a/projects/ad9467_fmc/zed/system_top.v +++ b/projects/ad9467_fmc/zed/system_top.v @@ -250,9 +250,7 @@ system_wrapper i_system_wrapper ( .ps_intr_0 (ps_intrs[0]), .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -261,7 +259,6 @@ system_wrapper i_system_wrapper ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9467_dma_irq (ps_intrs[13]), .otg_vbusoc (otg_vbusoc), .spdif (spdif), .adc_clk_in_n(adc_clk_in_n), From ff2dfa7dd301c8f0af4e14e2802c83102942257e Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 12:59:52 +0200 Subject: [PATCH 66/91] fmcadc5: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcadc5/common/fmcadc5_bd.tcl | 17 +++++++++-------- projects/fmcadc5/vc707/system_top.v | 6 ------ 2 files changed, 9 insertions(+), 14 deletions(-) diff --git a/projects/fmcadc5/common/fmcadc5_bd.tcl b/projects/fmcadc5/common/fmcadc5_bd.tcl index 39cb384b1..167d440a0 100644 --- a/projects/fmcadc5/common/fmcadc5_bd.tcl +++ b/projects/fmcadc5/common/fmcadc5_bd.tcl @@ -21,10 +21,6 @@ set rx_sync_1 [create_bd_port -dir O rx_sync_1] set rx_sysref [create_bd_port -dir O rx_sysref] -set ad9625_spi_intr [create_bd_port -dir O ad9625_spi_intr] -set ad9625_gpio_intr [create_bd_port -dir O ad9625_gpio_intr] -set ad9625_dma_intr [create_bd_port -dir O ad9625_dma_intr] - set gpio_ad9625_i [create_bd_port -dir I -from 18 -to 0 gpio_ad9625_i] set gpio_ad9625_o [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_o] set gpio_ad9625_t [create_bd_port -dir O -from 18 -to 0 gpio_ad9625_t] @@ -120,9 +116,6 @@ connect_bd_net -net gpio_ad9625_i [get_bd_ports gpio_ad9625_i] [get_bd_pins connect_bd_net -net gpio_ad9625_o [get_bd_ports gpio_ad9625_o] [get_bd_pins axi_ad9625_gpio/gpio_io_o] connect_bd_net -net gpio_ad9625_t [get_bd_ports gpio_ad9625_t] [get_bd_pins axi_ad9625_gpio/gpio_io_t] -connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_ports ad9625_spi_intr] -connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_ports ad9625_gpio_intr] - # connections (gt) connect_bd_net -net axi_ad9625_0_gt_ref_clk_c [get_bd_pins axi_ad9625_0_gt/ref_clk_c] [get_bd_ports rx_ref_clk_0] @@ -191,7 +184,15 @@ connect_bd_net -net axi_ad9625_dma_dvalid [get_bd_pins axi_ad9625_fi connect_bd_net -net axi_ad9625_dma_dready [get_bd_pins axi_ad9625_fifo/dma_wready] [get_bd_pins axi_ad9625_dma/s_axis_ready] connect_bd_net -net axi_ad9625_dma_ddata [get_bd_pins axi_ad9625_fifo/dma_wdata] [get_bd_pins axi_ad9625_dma/s_axis_data] connect_bd_net -net axi_ad9625_dma_xfer_req [get_bd_pins axi_ad9625_fifo/dma_xfer_req] [get_bd_pins axi_ad9625_dma/s_axis_xfer_req] -connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_ports ad9625_dma_intr] + +# interrupts + +delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] +delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] +delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] +connect_bd_net -net axi_ad9625_spi_irq [get_bd_pins axi_ad9625_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] +connect_bd_net -net axi_ad9625_gpio_irq [get_bd_pins axi_ad9625_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12] +connect_bd_net -net axi_ad9625_dma_intr [get_bd_pins axi_ad9625_dma/irq] [get_bd_pins sys_concat_intc/In13] # interconnect (cpu) diff --git a/projects/fmcadc5/vc707/system_top.v b/projects/fmcadc5/vc707/system_top.v index be403784d..add526744 100644 --- a/projects/fmcadc5/vc707/system_top.v +++ b/projects/fmcadc5/vc707/system_top.v @@ -384,9 +384,6 @@ module system_top ( assign fan_pwm = 1'b1; system_wrapper i_system_wrapper ( - .ad9625_dma_intr (mb_intrs[13]), - .ad9625_gpio_intr (mb_intrs[12]), - .ad9625_spi_intr (mb_intrs[11]), .adc_clk (adc_clk), .adc_data_0 (adc_data_0), .adc_data_1 (adc_data_1), @@ -432,9 +429,6 @@ module system_top ( .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), From 73ad75153e879e5fe964cd419a4fe4cd813029b5 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:01:00 +0200 Subject: [PATCH 67/91] fmcjesdadc1: Updated project with interrupts in IPI to work correctly in Linux --- .../fmcjesdadc1/common/fmcjesdadc1_bd.tcl | 30 ++++++++++++------- projects/fmcjesdadc1/kc705/system_top.v | 6 ---- projects/fmcjesdadc1/vc707/system_top.v | 5 ---- projects/fmcjesdadc1/zc706/system_top.v | 4 --- 4 files changed, 20 insertions(+), 25 deletions(-) diff --git a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl index d8ab40fff..4b1c5eda8 100644 --- a/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl +++ b/projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl @@ -39,13 +39,6 @@ set dma_1_wr [create_bd_port -dir I dma_1_wr] set dma_1_sync [create_bd_port -dir I dma_1_sync] set dma_1_data [create_bd_port -dir I -from 63 -to 0 dma_1_data] -#interrupts -set ad9250_0_dma_intr [create_bd_port -dir O ad9250_0_dma_intr] -set ad9250_1_dma_intr [create_bd_port -dir O ad9250_1_dma_intr] -if { $sys_zynq == 0 } { - set ad9250_spi_intr [create_bd_port -dir O ad9250_spi_intr] -} - # adc peripherals set axi_ad9250_0_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_0_core] @@ -155,7 +148,26 @@ if {$sys_zynq == 1 } { connect_bd_net -net spi_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_ad9250_spi/io0_o] connect_bd_net -net spi_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_ad9250_spi/io1_i] - connect_bd_net -net axi_ad9250_spi_irq [get_bd_pins axi_ad9250_spi/ip2intc_irpt] [get_bd_ports ad9250_spi_intr] +} + +# interrupts + +if {$sys_zynq == 0 } { + + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net axi_ad9250_spi_irq [get_bd_pins axi_ad9250_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In13] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_pins sys_concat_intc/In13] + } # connections (gt) @@ -217,8 +229,6 @@ connect_bd_net -net axi_ad9250_1_dma_data [get_bd_pins axi_ad9250_1_dm connect_bd_net -net axi_ad9250_0_adc_dovf [get_bd_pins axi_ad9250_0_core/adc_dovf] [get_bd_pins axi_ad9250_0_dma/fifo_wr_overflow] connect_bd_net -net axi_ad9250_1_adc_dovf [get_bd_pins axi_ad9250_1_core/adc_dovf] [get_bd_pins axi_ad9250_1_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9250_0_dma_irq [get_bd_pins axi_ad9250_0_dma/irq] [get_bd_ports ad9250_0_dma_intr] -connect_bd_net -net axi_ad9250_1_dma_irq [get_bd_pins axi_ad9250_1_dma/irq] [get_bd_ports ad9250_1_dma_intr] # interconnect (cpu) diff --git a/projects/fmcjesdadc1/kc705/system_top.v b/projects/fmcjesdadc1/kc705/system_top.v index 34ef6f856..f9536004e 100644 --- a/projects/fmcjesdadc1/kc705/system_top.v +++ b/projects/fmcjesdadc1/kc705/system_top.v @@ -361,10 +361,7 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -383,9 +380,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9250_0_dma_intr (mb_intrs[10]), - .ad9250_1_dma_intr (mb_intrs[11]), - .ad9250_spi_intr (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), diff --git a/projects/fmcjesdadc1/vc707/system_top.v b/projects/fmcjesdadc1/vc707/system_top.v index 496587123..2b8b6e4e5 100644 --- a/projects/fmcjesdadc1/vc707/system_top.v +++ b/projects/fmcjesdadc1/vc707/system_top.v @@ -357,10 +357,7 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -379,8 +376,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9250_0_dma_intr (mb_intrs[10]), - .ad9250_1_dma_intr (mb_intrs[11]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mgt_clk_clk_n (mgt_clk_n), diff --git a/projects/fmcjesdadc1/zc706/system_top.v b/projects/fmcjesdadc1/zc706/system_top.v index 24107a5f2..b15cca11d 100644 --- a/projects/fmcjesdadc1/zc706/system_top.v +++ b/projects/fmcjesdadc1/zc706/system_top.v @@ -319,10 +319,6 @@ module system_top ( .ps_intr_9 (ps_intrs[9]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), - .ad9250_0_dma_intr (ps_intrs[13]), - .ad9250_1_dma_intr (ps_intrs[12]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_gt_data (rx_gt_data), From a27c8d3052dff7e140dfc7366f8598fbb376a27a Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:02:45 +0200 Subject: [PATCH 68/91] fmcomm1: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcomms1/ac701/system_top.v | 4 ---- projects/fmcomms1/common/fmcomms1_bd.tcl | 21 ++++++++++++++------- projects/fmcomms1/kc705/system_top.v | 4 ---- projects/fmcomms1/vc707/system_top.v | 4 ---- projects/fmcomms1/zc702/system_top.v | 4 ---- projects/fmcomms1/zc706/system_top.v | 4 ---- projects/fmcomms1/zed/system_top.v | 6 ------ 7 files changed, 14 insertions(+), 33 deletions(-) diff --git a/projects/fmcomms1/ac701/system_top.v b/projects/fmcomms1/ac701/system_top.v index d1a39c5e0..21824bb74 100644 --- a/projects/fmcomms1/ac701/system_top.v +++ b/projects/fmcomms1/ac701/system_top.v @@ -293,8 +293,6 @@ module system_top ( .iic_rstn (iic_rstn), .mb_intr_10 (mb_intrs[10]), .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -313,8 +311,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9122_dma_irq (mb_intrs[12]), - .ad9643_dma_irq (mb_intrs[13]), .adc_clk (adc_clk), .adc_clk_in_n (adc_clk_in_n), .adc_clk_in_p (adc_clk_in_p), diff --git a/projects/fmcomms1/common/fmcomms1_bd.tcl b/projects/fmcomms1/common/fmcomms1_bd.tcl index ae5e796af..c1387a3b7 100644 --- a/projects/fmcomms1/common/fmcomms1_bd.tcl +++ b/projects/fmcomms1/common/fmcomms1_bd.tcl @@ -48,11 +48,6 @@ set adc_dma_sync [create_bd_port -dir I adc_dma_sync] set adc_dma_wdata [create_bd_port -dir I -from 31 -to 0 adc_dma_wdata] - # interrupts - - set ad9122_dma_irq [create_bd_port -dir O ad9122_dma_irq] - set ad9643_dma_irq [create_bd_port -dir O ad9643_dma_irq] - # dac peripherals set axi_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122] @@ -135,7 +130,6 @@ if {$sys_zynq == 1} { connect_bd_net -net axi_ad9122_dma_drd [get_bd_pins axi_ad9122_dma/fifo_rd_en] [get_bd_ports dac_dma_rd] connect_bd_net -net axi_ad9122_dma_ddata [get_bd_pins axi_ad9122_dma/fifo_rd_dout] [get_bd_ports dac_dma_rdata] - connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_ports ad9122_dma_irq] # connections (adc) @@ -167,7 +161,20 @@ if {$sys_zynq == 1} { connect_bd_net -net axi_ad9643_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9643_dma/fifo_wr_sync] connect_bd_net -net axi_ad9643_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9643_dma/fifo_wr_din] connect_bd_net -net axi_ad9643_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9643_dma/fifo_wr_overflow] - connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_ports ad9643_dma_irq] + + # interrupts + +if {$sys_zynq == 0 } { + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In13] +} else { + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9122_dma_irq [get_bd_pins axi_ad9122_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9643_dma_irq [get_bd_pins axi_ad9643_dma/irq] [get_bd_pins sys_concat_intc/In13] +} # interconnect (cpu) diff --git a/projects/fmcomms1/kc705/system_top.v b/projects/fmcomms1/kc705/system_top.v index a2786746a..a919bbf4f 100644 --- a/projects/fmcomms1/kc705/system_top.v +++ b/projects/fmcomms1/kc705/system_top.v @@ -349,8 +349,6 @@ module system_top ( .iic_rstn (iic_rstn), .mb_intr_10 (mb_intrs[10]), .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -369,8 +367,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9122_dma_irq (mb_intrs[12]), - .ad9643_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), .mii_col (mii_col), diff --git a/projects/fmcomms1/vc707/system_top.v b/projects/fmcomms1/vc707/system_top.v index 997bdf75e..5ecd69d80 100644 --- a/projects/fmcomms1/vc707/system_top.v +++ b/projects/fmcomms1/vc707/system_top.v @@ -347,8 +347,6 @@ module system_top ( .iic_rstn (iic_rstn), .mb_intr_10 (mb_intrs[10]), .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -367,8 +365,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .ad9122_dma_irq (mb_intrs[12]), - .ad9643_dma_irq (mb_intrs[13]), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .mgt_clk_clk_n (mgt_clk_n), diff --git a/projects/fmcomms1/zc702/system_top.v b/projects/fmcomms1/zc702/system_top.v index fa815ce93..bfde226ea 100644 --- a/projects/fmcomms1/zc702/system_top.v +++ b/projects/fmcomms1/zc702/system_top.v @@ -309,8 +309,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -319,8 +317,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9122_dma_irq (ps_intrs[12]), - .ad9643_dma_irq (ps_intrs[13]), .ref_clk (ref_clk), .spdif (spdif)); diff --git a/projects/fmcomms1/zc706/system_top.v b/projects/fmcomms1/zc706/system_top.v index a40046a09..bb94928d9 100644 --- a/projects/fmcomms1/zc706/system_top.v +++ b/projects/fmcomms1/zc706/system_top.v @@ -309,8 +309,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -319,8 +317,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9122_dma_irq (ps_intrs[12]), - .ad9643_dma_irq (ps_intrs[13]), .ref_clk (ref_clk), .spdif (spdif)); diff --git a/projects/fmcomms1/zed/system_top.v b/projects/fmcomms1/zed/system_top.v index ae46ed337..68b7e74a6 100644 --- a/projects/fmcomms1/zed/system_top.v +++ b/projects/fmcomms1/zed/system_top.v @@ -362,9 +362,6 @@ module system_top ( .ps_intr_0 (ps_intrs[0]), .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -373,9 +370,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9122_dma_irq (ps_intrs[12]), - .ad9643_dma_irq (ps_intrs[13]), - .iic_fmc_intr(ps_intrs[11]), .ref_clk (ref_clk), .otg_vbusoc (otg_vbusoc), .spdif (spdif)); From 57302820ed1490f3fc434dddcbb637cb3f4b382c Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:03:24 +0200 Subject: [PATCH 69/91] fmcomms5: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcomms5/common/fmcomms5_bd.tcl | 29 +++++++++++++++--------- projects/fmcomms5/zc702/system_top.v | 6 ----- projects/fmcomms5/zc706/system_top.v | 6 ----- 3 files changed, 18 insertions(+), 23 deletions(-) diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl index c34ce4ac8..85620dfae 100644 --- a/projects/fmcomms5/common/fmcomms5_bd.tcl +++ b/projects/fmcomms5/common/fmcomms5_bd.tcl @@ -56,13 +56,6 @@ set spi_mosi_i [create_bd_port -dir I spi_mosi_i] set spi_mosi_o [create_bd_port -dir O spi_mosi_o] set spi_miso_i [create_bd_port -dir I spi_miso_i] -# interrupts - -set fmcomms5_gpio_irq [create_bd_port -dir O fmcomms5_gpio_irq] -set ad9361_adc_dma_irq [create_bd_port -dir O ad9361_adc_dma_irq] -set ad9361_dac_dma_irq [create_bd_port -dir O ad9361_dac_dma_irq] -set fmcomms5_spi_irq [create_bd_port -dir O fmcomms5_spi_irq] - # instances set axi_ad9361_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361_0] @@ -163,7 +156,6 @@ if {$sys_zynq == 0} { connect_bd_net -net spi_mosi_i [get_bd_pins axi_fmcomms2_spi/io0_i] [get_bd_ports spi_mosi_i] connect_bd_net -net spi_mosi_o [get_bd_pins axi_fmcomms2_spi/io0_o] [get_bd_ports spi_mosi_o] connect_bd_net -net spi_miso_i [get_bd_pins axi_fmcomms2_spi/io1_i] [get_bd_ports spi_miso_i] - connect_bd_net -net spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_ports fmcomms5_spi_irq] } else { connect_bd_net -net spi_csn_0_i [get_bd_pins sys_ps7/SPI0_SS_I] [get_bd_ports spi_csn_0_i] connect_bd_net -net spi_csn_0_o [get_bd_pins sys_ps7/SPI0_SS_O] [get_bd_ports spi_csn_0_o] @@ -182,7 +174,6 @@ if {$sys_zynq == 0} { connect_bd_net -net gpio_i [get_bd_pins axi_fmcomms2_gpio/gpio_io_i] [get_bd_ports gpio_i] connect_bd_net -net gpio_o [get_bd_pins axi_fmcomms2_gpio/gpio_io_o] [get_bd_ports gpio_o] connect_bd_net -net gpio_t [get_bd_pins axi_fmcomms2_gpio/gpio_io_t] [get_bd_ports gpio_t] - connect_bd_net -net gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_ports fmcomms5_gpio_irq] } # connections (ad9361) @@ -283,9 +274,25 @@ connect_bd_net -net axi_ad9361_0_dac_drd [get_bd_pins util_dac_unpack_0 connect_bd_net -net axi_ad9361_dac_ddata [get_bd_pins util_dac_unpack_0/dma_data] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] connect_bd_net -net axi_ad9361_fifo_valid [get_bd_pins util_dac_unpack_0/fifo_valid] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_valid] connect_bd_net -net axi_ad9361_0_adc_dovf [get_bd_pins axi_ad9361_0/adc_dovf] [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_ports ad9361_adc_dma_irq] connect_bd_net -net axi_ad9361_0_dac_dunf [get_bd_pins axi_ad9361_0/dac_dunf] [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] -connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_ports ad9361_dac_dma_irq] + +# interrupts + +if {$sys_zynq == 0} { + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net spi_irq [get_bd_pins axi_fmcomms2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net gpio_irq [get_bd_pins axi_fmcomms2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13] +} else { + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9361_dac_dma_irq [get_bd_pins axi_ad9361_dac_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9361_adc_dma_irq [get_bd_pins axi_ad9361_adc_dma/irq] [get_bd_pins sys_concat_intc/In13] +} # interconnect (cpu) diff --git a/projects/fmcomms5/zc702/system_top.v b/projects/fmcomms5/zc702/system_top.v index 0cdd61b48..53ccba265 100644 --- a/projects/fmcomms5/zc702/system_top.v +++ b/projects/fmcomms5/zc702/system_top.v @@ -340,8 +340,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -350,10 +348,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), - .fmcomms5_gpio_irq(), - .fmcomms5_spi_irq(), .rx_clk_in_0_n (rx_clk_in_0_n), .rx_clk_in_0_p (rx_clk_in_0_p), .rx_clk_in_1_n (rx_clk_in_1_n), diff --git a/projects/fmcomms5/zc706/system_top.v b/projects/fmcomms5/zc706/system_top.v index 6851598a6..0104d7788 100644 --- a/projects/fmcomms5/zc706/system_top.v +++ b/projects/fmcomms5/zc706/system_top.v @@ -342,8 +342,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -352,10 +350,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), - .fmcomms5_gpio_irq(), - .fmcomms5_spi_irq(), .rx_clk_in_0_n (rx_clk_in_0_n), .rx_clk_in_0_p (rx_clk_in_0_p), .rx_clk_in_1_n (rx_clk_in_1_n), From 30a869b02a6f144929280ba3f7d321c496eb0c3d Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:04:15 +0200 Subject: [PATCH 70/91] fmcomms6: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcomms6/common/fmcomms6_bd.tcl | 27 ++++++++++++++++-------- projects/fmcomms6/zc706/system_top.v | 2 -- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/projects/fmcomms6/common/fmcomms6_bd.tcl b/projects/fmcomms6/common/fmcomms6_bd.tcl index 5e4c8f61c..63cea7a49 100644 --- a/projects/fmcomms6/common/fmcomms6_bd.tcl +++ b/projects/fmcomms6/common/fmcomms6_bd.tcl @@ -36,12 +36,6 @@ if {$sys_zynq == 0} { set gpio_fmcomms6_t [create_bd_port -dir O gpio_fmcomms6_t] } -# interrupts - -set fmcomms6_dma_irq [create_bd_port -dir O fmcomms6_dma_irq] -set fmcomms6_spi_irq [create_bd_port -dir O fmcomms6_spi_irq] -set fmcomms6_gpio_irq [create_bd_port -dir O fmcomms6_gpio_irq] - # dma interface set adc_clk [create_bd_port -dir O adc_clk] @@ -131,8 +125,6 @@ if {$sys_zynq == 1 } { connect_bd_net -net gpio_fmcomms6_o [get_bd_ports gpio_fmcomms6_o] [get_bd_pins axi_fmcomms6_gpio/gpio_io_o] connect_bd_net -net gpio_fmcomms6_t [get_bd_ports gpio_fmcomms6_t] [get_bd_pins axi_fmcomms6_gpio/gpio_io_t] - connect_bd_net -net axi_fmcomms6_spi_irq [get_bd_pins axi_fmcomms6_spi/ip2intc_irpt] [get_bd_ports fmcomms6_spi_irq] - connect_bd_net -net axi_fmcomms6_gpio_irq [get_bd_pins axi_fmcomms6_gpio/ip2intc_irpt] [get_bd_ports fmcomms6_gpio_irq] } # connections (adc) @@ -165,7 +157,24 @@ connect_bd_net -net axi_ad9652_dma_dwr [get_bd_pins sys_wfifo/s_wr] connect_bd_net -net axi_ad9652_dma_dsync [get_bd_ports adc_dma_sync] [get_bd_pins axi_ad9652_dma/fifo_wr_sync] connect_bd_net -net axi_ad9652_dma_ddata [get_bd_pins sys_wfifo/s_wdata] [get_bd_pins axi_ad9652_dma/fifo_wr_din] connect_bd_net -net axi_ad9652_dma_dovf [get_bd_pins sys_wfifo/s_wovf] [get_bd_pins axi_ad9652_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_ports fmcomms6_dma_irq] + +# interrupts + +if {$sys_zynq == 0 } { + + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_fmcomms6_spi_irq [get_bd_pins axi_fmcomms6_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_fmcomms6_gpio_irq [get_bd_pins axi_fmcomms6_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In13] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9652_dma_irq [get_bd_pins axi_ad9652_dma/irq] [get_bd_pins sys_concat_intc/In13] + +} # interconnect (cpu) diff --git a/projects/fmcomms6/zc706/system_top.v b/projects/fmcomms6/zc706/system_top.v index 5b25a6e03..9e42cdbaa 100644 --- a/projects/fmcomms6/zc706/system_top.v +++ b/projects/fmcomms6/zc706/system_top.v @@ -247,7 +247,6 @@ module system_top ( .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -256,7 +255,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .fmcomms6_dma_irq (ps_intrs[13]), .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), From d30edeb61669ef8ee954a0906a0f8dffe0c07861 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:04:52 +0200 Subject: [PATCH 71/91] fmcomms7: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcomms7/common/fmcomms7_bd.tcl | 42 +++++++++++++++++------- projects/fmcomms7/zc706/system_top.v | 10 ------ 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index fde2b5d42..799041945 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -77,12 +77,6 @@ if {$sys_zynq == 0} { set adc_dsync [create_bd_port -dir I adc_dsync] set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] - set axi_ad9144_dma_intr [create_bd_port -dir O axi_ad9144_dma_intr] - set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr] - set axi_fmcomms7_spi_intr [create_bd_port -dir O axi_fmcomms7_spi_intr ] - set axi_fmcomms7_spi2_intr [create_bd_port -dir O axi_fmcomms7_spi2_intr ] - set axi_fmcomms7_gpio_intr [create_bd_port -dir O axi_fmcomms7_gpio_intr ] - # dac peripherals set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] @@ -301,7 +295,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_ports axi_ad9144_dma_intr] # connections (adc) @@ -339,7 +332,7 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready] connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data] connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_fifo/axi_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req] - connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr] + # dac/adc clocks @@ -391,7 +384,6 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_cpu_interconnect/M14_ARESETN] $sys_100m_resetn_source connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcomms7_spi2/s_axi_aresetn] - connect_bd_net -net axi_fmcomms7_spi_intr [get_bd_pins axi_fmcomms7_spi2/ip2intc_irpt] [get_bd_ports axi_fmcomms7_spi2_intr] if {$sys_zynq == 0} { @@ -408,8 +400,36 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcomms7_spi/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_fmcomms7_gpio/s_axi_aresetn] - connect_bd_net -net axi_fmcomms7_spi_intr [get_bd_pins axi_fmcomms7_spi/ip2intc_irpt] [get_bd_ports axi_fmcomms7_spi_intr] - connect_bd_net -net axi_fmcomms7_gpio_intr [get_bd_pins axi_fmcomms7_gpio/ip2intc_irpt] [get_bd_ports axi_fmcomms7_gpio_intr] +} + + # interrupts + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets mb_intr_9_s] [get_bd_ports mb_intr_9] + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In9] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_fmcomms7_gpio_intr [get_bd_pins axi_fmcomms7_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net axi_fmcomms7_spi2_intr [get_bd_pins axi_fmcomms7_spi2/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_fmcomms7_spi_intr [get_bd_pins axi_fmcomms7_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In13] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_9_s] [get_bd_ports ps_intr_9] + delete_bd_objs [get_bd_nets ps_intr_10_s] [get_bd_ports ps_intr_10] + delete_bd_objs [get_bd_nets ps_intr_11_s] [get_bd_ports ps_intr_11] + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In9] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_fmcomms7_gpio_intr [get_bd_pins axi_fmcomms7_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net axi_fmcomms7_spi2_intr [get_bd_pins axi_fmcomms7_spi2/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_fmcomms7_spi_intr [get_bd_pins axi_fmcomms7_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In13] + } # gt uses hp3, and 100MHz clock for both DRP and AXI4 diff --git a/projects/fmcomms7/zc706/system_top.v b/projects/fmcomms7/zc706/system_top.v index 881b28c1b..e2cd5d5f3 100644 --- a/projects/fmcomms7/zc706/system_top.v +++ b/projects/fmcomms7/zc706/system_top.v @@ -604,11 +604,6 @@ module system_top ( .adc_enable_1 (adc_enable_1), .adc_valid_0 (adc_valid_0), .adc_valid_1 (adc_valid_1), - .axi_ad9144_dma_intr (ps_intrs[9]), - .axi_ad9680_dma_intr (ps_intrs[10]), - .axi_fmcomms7_gpio_intr (ps_intrs[11]), - .axi_fmcomms7_spi2_intr (ps_intrs[12]), - .axi_fmcomms7_spi_intr (ps_intrs[13]), .dac_clk (dac_clk), .dac_ddata (dac_ddata), .dac_ddata_0 (dac_ddata_0), @@ -633,10 +628,6 @@ module system_top ( .iic_main_sda_io (iic_sda), .ps_intr_0 (ps_intrs[0]), .ps_intr_1 (ps_intrs[1]), - .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -644,7 +635,6 @@ module system_top ( .ps_intr_6 (ps_intrs[6]), .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), - .ps_intr_9 (ps_intrs[9]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From 8c9de36f569360acb745cd73f61ad6ce67f860d8 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:05:54 +0200 Subject: [PATCH 72/91] usdrx1: Updated project with interrupts in IPI to work correctly in Linux --- projects/usdrx1/common/usdrx1_bd.tcl | 13 +++++++------ projects/usdrx1/zc706/system_top.v | 4 ---- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 88b0de329..7c6d7a560 100644 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -45,10 +45,6 @@ set adc_data [create_bd_port -dir I -from 511 -to 0 adc_data] set adc_wr_en [create_bd_port -dir I adc_wr_en] set adc_dovf [create_bd_port -dir O adc_dovf] -# interrupts -set usdrx1_dma_irq [create_bd_port -dir O usdrx1_dma_irq] -set usdrx1_spi_irq [create_bd_port -dir O usdrx1_spi_irq] - # adc peripherals set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0] @@ -136,7 +132,6 @@ connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_u connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] -connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_ports usdrx1_spi_irq] # connections (gt) @@ -197,7 +192,6 @@ connect_bd_net -net axi_ad9671_core_adc_dovf_3 [get_bd_pins axi_ad9671_core connect_bd_net -net axi_ad9671_dma_wr_en [get_bd_pins axi_usdrx1_dma/fifo_wr_en] [get_bd_ports adc_wr_en] connect_bd_net -net axi_ad9671_dma_adc_data [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_data] connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf] -connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_ports usdrx1_dma_irq] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_0/adc_raddr_out] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_1/adc_raddr_in] connect_bd_net -net axi_ad9671_adc_raddr [get_bd_pins axi_ad9671_core_2/adc_raddr_in] @@ -207,6 +201,13 @@ connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_2/adc_sync_in] connect_bd_net -net axi_ad9671_adc_sync [get_bd_pins axi_ad9671_core_3/adc_sync_in] +#interrupts + +delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] +delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] +connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In12] +connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In13] + # interconnect (cpu) connect_bd_intf_net -intf_net axi_cpu_interconnect_m07_axi [get_bd_intf_pins axi_cpu_interconnect/M07_AXI] [get_bd_intf_pins axi_usdrx1_gt/s_axi] diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index 662b2bfae..3c3c602f8 100644 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -432,10 +432,6 @@ module system_top ( .ps_intr_9 (ps_intrs[9]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), - .usdrx1_dma_irq (ps_intrs[13]), - .usdrx1_spi_irq (ps_intrs[12]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From 1407bebb11c528e2f21f4623f13272d6e0c40ca0 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:47:37 +0200 Subject: [PATCH 73/91] kcu105: Changed the interrupt net names to be similar to other microblaze based projects --- projects/common/kcu105/kcu105_system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/common/kcu105/kcu105_system_bd.tcl b/projects/common/kcu105/kcu105_system_bd.tcl index 26abee2e3..76ddce9cc 100644 --- a/projects/common/kcu105/kcu105_system_bd.tcl +++ b/projects/common/kcu105/kcu105_system_bd.tcl @@ -349,7 +349,7 @@ connect_bd_net [get_bd_pins sys_concat_intc/In9] [get_bd_pins axi_iic_main/iic2i for {set intc_index 10} {$intc_index < 32} {incr intc_index} { set mb_intr_${intc_index} [create_bd_port -dir I mb_intr_${intc_index}] - connect_bd_net [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] + connect_bd_net -net mb_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports mb_intr_${intc_index}] } # defaults (ddr) From 0b25a337a218e09fd7b4c836f15fc58e555c5155 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:49:11 +0200 Subject: [PATCH 74/91] daq2: Updated project with interrupts in IPI to work correctly in Linux --- projects/daq2/common/daq2_bd.tcl | 31 ++++++++++++++++++++++--------- projects/daq2/kc705/system_top.v | 8 -------- projects/daq2/kcu105/system_top.v | 8 -------- projects/daq2/vc707/system_top.v | 8 -------- projects/daq2/zc706/system_top.v | 4 ---- 5 files changed, 22 insertions(+), 37 deletions(-) diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index a2cb0d5f9..01aa8a5a2 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -69,11 +69,6 @@ if {$sys_zynq == 0} { set adc_dsync [create_bd_port -dir I adc_dsync] set adc_ddata [create_bd_port -dir I -from 127 -to 0 adc_ddata] - set axi_ad9144_dma_intr [create_bd_port -dir O axi_ad9144_dma_intr] - set axi_ad9680_dma_intr [create_bd_port -dir O axi_ad9680_dma_intr] - set axi_daq2_spi_intr [create_bd_port -dir O axi_daq2_spi_intr ] - set axi_daq2_gpio_intr [create_bd_port -dir O axi_daq2_gpio_intr ] - # dac peripherals set axi_ad9144_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9144:1.0 axi_ad9144_core] @@ -275,7 +270,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9144_dac_drd [get_bd_ports dac_drd] [get_bd_pins axi_ad9144_dma/fifo_rd_en] connect_bd_net -net axi_ad9144_dac_ddata [get_bd_ports dac_ddata] [get_bd_pins axi_ad9144_dma/fifo_rd_dout] connect_bd_net -net axi_ad9144_dac_dunf [get_bd_pins axi_ad9144_core/dac_dunf] [get_bd_pins axi_ad9144_dma/fifo_rd_underflow] - connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_ports axi_ad9144_dma_intr] # connections (adc) @@ -315,7 +309,6 @@ if {$sys_zynq == 0} { connect_bd_net -net axi_ad9680_dma_ddata [get_bd_pins axi_ad9680_fifo/dma_wdata] [get_bd_pins axi_ad9680_dma/s_axis_data] connect_bd_net -net axi_ad9680_dma_dready [get_bd_pins axi_ad9680_fifo/dma_wready] [get_bd_pins axi_ad9680_dma/s_axis_ready] connect_bd_net -net axi_ad9680_dma_xfer_req [get_bd_pins axi_ad9680_fifo/dma_xfer_req] [get_bd_pins axi_ad9680_dma/s_axis_xfer_req] - connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_ports axi_ad9680_dma_intr] # dac/adc clocks @@ -374,8 +367,28 @@ if {$sys_zynq == 0} { connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_spi/s_axi_aresetn] connect_bd_net -net sys_100m_resetn [get_bd_pins axi_daq2_gpio/s_axi_aresetn] - connect_bd_net -net axi_daq2_spi_intr [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_ports axi_daq2_spi_intr] - connect_bd_net -net axi_daq2_gpio_intr [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_ports axi_daq2_gpio_intr] +} + + # interrupts + +if {$sys_zynq == 0} { + + delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] + delete_bd_objs [get_bd_nets mb_intr_11_s] [get_bd_ports mb_intr_11] + delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] + delete_bd_objs [get_bd_nets mb_intr_13_s] [get_bd_ports mb_intr_13] + connect_bd_net -net axi_daq2_spi_intr [get_bd_pins axi_daq2_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_daq2_gpio_intr [get_bd_pins axi_daq2_gpio/ip2intc_irpt] [get_bd_pins sys_concat_intc/In11] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In13] + +} else { + + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net axi_ad9144_dma_intr [get_bd_pins axi_ad9144_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net axi_ad9680_dma_intr [get_bd_pins axi_ad9680_dma/irq] [get_bd_pins sys_concat_intc/In13] + } # gt uses hp3, and 100MHz clock for both DRP and AXI4 diff --git a/projects/daq2/kc705/system_top.v b/projects/daq2/kc705/system_top.v index dd23782ee..89920f436 100644 --- a/projects/daq2/kc705/system_top.v +++ b/projects/daq2/kc705/system_top.v @@ -531,10 +531,6 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -553,10 +549,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .axi_ad9144_dma_intr (mb_intrs[13]), - .axi_ad9680_dma_intr (mb_intrs[12]), - .axi_daq2_gpio_intr (mb_intrs[11]), - .axi_daq2_spi_intr (mb_intrs[10]), .iic_rstn (iic_rstn), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio_io), diff --git a/projects/daq2/kcu105/system_top.v b/projects/daq2/kcu105/system_top.v index c26c3c347..411f03a90 100644 --- a/projects/daq2/kcu105/system_top.v +++ b/projects/daq2/kcu105/system_top.v @@ -455,10 +455,6 @@ module system_top ( .adc_enable_1 (adc_enable_1), .adc_valid_0 (adc_valid_0), .adc_valid_1 (adc_valid_1), - .axi_ad9144_dma_intr (mb_intrs[13]), - .axi_ad9680_dma_intr (mb_intrs[12]), - .axi_daq2_gpio_intr (mb_intrs[11]), - .axi_daq2_spi_intr (mb_intrs[10]), .c0_ddr4_act_n (ddr4_act_n), .c0_ddr4_adr (ddr4_addr), .c0_ddr4_ba (ddr4_ba), @@ -505,10 +501,6 @@ module system_top ( .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), diff --git a/projects/daq2/vc707/system_top.v b/projects/daq2/vc707/system_top.v index 8302687fd..a4d178fb9 100644 --- a/projects/daq2/vc707/system_top.v +++ b/projects/daq2/vc707/system_top.v @@ -530,10 +530,6 @@ module system_top ( .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .iic_rstn (iic_rstn), - .mb_intr_10 (mb_intrs[10]), - .mb_intr_11 (mb_intrs[11]), - .mb_intr_12 (mb_intrs[12]), - .mb_intr_13 (mb_intrs[13]), .mb_intr_14 (mb_intrs[14]), .mb_intr_15 (mb_intrs[15]), .mb_intr_16 (mb_intrs[16]), @@ -552,10 +548,6 @@ module system_top ( .mb_intr_29 (mb_intrs[29]), .mb_intr_30 (mb_intrs[30]), .mb_intr_31 (mb_intrs[31]), - .axi_ad9144_dma_intr (mb_intrs[13]), - .axi_ad9680_dma_intr (mb_intrs[12]), - .axi_daq2_gpio_intr (mb_intrs[11]), - .axi_daq2_spi_intr (mb_intrs[10]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), diff --git a/projects/daq2/zc706/system_top.v b/projects/daq2/zc706/system_top.v index 999f6866f..a0f5afdc1 100644 --- a/projects/daq2/zc706/system_top.v +++ b/projects/daq2/zc706/system_top.v @@ -528,8 +528,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -538,8 +536,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .axi_ad9144_dma_intr (ps_intrs[12]), - .axi_ad9680_dma_intr (ps_intrs[13]), .rx_data_n (rx_data_n), .rx_data_p (rx_data_p), .rx_ref_clk (rx_ref_clk), From 0683123349ed4396b15395a02079f0926e34ba46 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:58:05 +0200 Subject: [PATCH 75/91] motcon2_fmc: Updated project with interrupts in IPI to work correctly in Linux --- .../motcon2_fmc/common/motcon2_fmc_bd.tcl | 37 ++++++++----------- projects/motcon2_fmc/zed/system_top.v | 16 -------- 2 files changed, 16 insertions(+), 37 deletions(-) diff --git a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl index e557b6f6a..b8accc54c 100644 --- a/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl +++ b/projects/motcon2_fmc/common/motcon2_fmc_bd.tcl @@ -45,14 +45,6 @@ set pwm_m2_bl_o [ create_bd_port -dir O pwm_m2_bl_o] set pwm_m2_bh_o [ create_bd_port -dir O pwm_m2_bh_o] - # interrupts - set motcon2_c_m1_intr [create_bd_port -dir O motcon2_c_m1_intr] - set motcon2_c_m2_intr [create_bd_port -dir O motcon2_c_m2_intr] - set motcon2_s_d1_intr [create_bd_port -dir O motcon2_s_d1_intr] - set motcon2_s_d2_intr [create_bd_port -dir O motcon2_s_d2_intr] - set motcon2_ctrl_m1_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m1_intr ] - set motcon2_ctrl_m2_intr [ create_bd_port -dir O -type intr motcon2_ctrl_m2_intr ] - # Ethernet # phy 1 set eth1_rgmii [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:rgmii_rtl:1.0 eth1_rgmii ] @@ -71,7 +63,6 @@ # iic create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ee2 - set iic_ee2_intr [create_bd_port -dir O iic_ee2_intr] # spi set spi_csn_i [create_bd_port -dir I spi_csn_i] @@ -269,10 +260,6 @@ connect_bd_net -net speed_detector_adc_new_speed_m2 [get_bd_pins speed_detector_m2/new_speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_en] connect_bd_net -net speed_detector_adc_speed_m2 [get_bd_pins speed_detector_m2/speed_o] [get_bd_pins speed_detector_m2_dma/fifo_wr_din] - # interrupt - connect_bd_net -net speed_detector_m1_dma_intr [get_bd_pins speed_detector_m1_dma/irq] [get_bd_ports motcon2_s_d1_intr] - connect_bd_net -net speed_detector_m2_dma_intr [get_bd_pins speed_detector_m2_dma/irq] [get_bd_ports motcon2_s_d2_intr] - # current monitor connect_bd_net -net current_monitor_m1_adc_clk_o [get_bd_ports adc_clk_o] [get_bd_pins current_monitor_m1/adc_clk_o] # motor 1 @@ -372,10 +359,6 @@ # connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_valid] [get_bd_pins current_monitor_m2_dma/fifo_wr_en] # connect_bd_net [get_bd_pins current_monitor_m2_pack/adc_data] [get_bd_pins current_monitor_m2_dma/fifo_wr_din] - # interrupts - connect_bd_net -net axi_current_monitor_1_dma_intr [get_bd_pins current_monitor_m1_dma/irq] [get_bd_ports motcon2_c_m1_intr] - connect_bd_net -net axi_current_monitor_2_dma_intr [get_bd_pins current_monitor_m2_dma/irq] [get_bd_ports motcon2_c_m2_intr] - #controller # motor 1 connect_bd_net -net sys_100m_clk [get_bd_pins controller_m1/ref_clk] $sys_100m_clk_source @@ -554,9 +537,6 @@ connect_bd_net [get_bd_pins controller_m2_apack/ddata] [get_bd_pins controller_m2_dma/fifo_wr_din] connect_bd_net [get_bd_pins controller_m2_apack/dvalid] [get_bd_pins controller_m2_dma/fifo_wr_en] - # interrupts - connect_bd_net -net controller_m1_dma_intr [get_bd_pins controller_m1_dma/irq] [get_bd_ports motcon2_ctrl_m1_intr] - connect_bd_net -net controller_m2_dma_intr [get_bd_pins controller_m2_dma/irq] [get_bd_ports motcon2_ctrl_m2_intr] # ethernet @@ -602,7 +582,6 @@ connect_bd_net -net sys_100m_clk [get_bd_pins iic_ee2/s_axi_aclk] connect_bd_net -net sys_100m_resetn [get_bd_pins iic_ee2/s_axi_aresetn] connect_bd_intf_net [get_bd_intf_pins iic_ee2/IIC] [get_bd_intf_ports iic_ee2] - connect_bd_net -net iic_ee2_irq [get_bd_pins iic_ee2/iic2intc_irpt] [get_bd_ports iic_ee2_intr] # spi connect_bd_net -net spi_csn_i [get_bd_ports spi_csn_i] [get_bd_pins sys_ps7/SPI0_SS_I] @@ -613,6 +592,22 @@ connect_bd_net -net spi_mosi_o [get_bd_ports spi_mosi_o] [get_bd_pins sys_ps7/SPI0_MOSI_O] connect_bd_net -net spi_miso_i [get_bd_ports spi_miso_i] [get_bd_pins sys_ps7/SPI0_MISO_I] + # interrupts + delete_bd_objs [get_bd_nets ps_intr_6_s] [get_bd_ports ps_intr_6] + delete_bd_objs [get_bd_nets ps_intr_7_s] [get_bd_ports ps_intr_7] + delete_bd_objs [get_bd_nets ps_intr_8_s] [get_bd_ports ps_intr_8] + delete_bd_objs [get_bd_nets ps_intr_9_s] [get_bd_ports ps_intr_9] + delete_bd_objs [get_bd_nets ps_intr_10_s] [get_bd_ports ps_intr_10] + delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] + delete_bd_objs [get_bd_nets ps_intr_13_s] [get_bd_ports ps_intr_13] + connect_bd_net -net controller_m2_dma_intr [get_bd_pins controller_m2_dma/irq] [get_bd_pins sys_concat_intc/In6] + connect_bd_net -net axi_current_monitor_2_dma_intr [get_bd_pins current_monitor_m2_dma/irq] [get_bd_pins sys_concat_intc/In7] + connect_bd_net -net speed_detector_m2_dma_intr [get_bd_pins speed_detector_m2_dma/irq] [get_bd_pins sys_concat_intc/In8] + connect_bd_net -net controller_m1_dma_intr [get_bd_pins controller_m1_dma/irq] [get_bd_pins sys_concat_intc/In9] + connect_bd_net -net axi_current_monitor_1_dma_intr [get_bd_pins current_monitor_m1_dma/irq] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net iic_ee2_irq [get_bd_pins iic_ee2/iic2intc_irpt] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net speed_detector_m1_dma_intr [get_bd_pins speed_detector_m1_dma/irq] [get_bd_pins sys_concat_intc/In13] + # cpu interconnect connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M07_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_cpu_interconnect/M08_ACLK] $sys_100m_clk_source diff --git a/projects/motcon2_fmc/zed/system_top.v b/projects/motcon2_fmc/zed/system_top.v index e4801d956..199cb9e97 100644 --- a/projects/motcon2_fmc/zed/system_top.v +++ b/projects/motcon2_fmc/zed/system_top.v @@ -454,28 +454,12 @@ module system_top ( .iic_mux_sda_I (iic_mux_sda_i_s), .iic_mux_sda_O (iic_mux_sda_o_s), .iic_mux_sda_T (iic_mux_sda_t_s), - .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_0 (ps_intrs[0]), .ps_intr_1 (ps_intrs[1]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), .ps_intr_5 (ps_intrs[5]), - .ps_intr_6 (ps_intrs[6]), - .ps_intr_7 (ps_intrs[7]), - .ps_intr_8 (ps_intrs[8]), - .ps_intr_9 (ps_intrs[9]), - .iic_fmc_intr(ps_intrs[13]), - .iic_ee2_intr(ps_intrs[12]), - .motcon2_s_d1_intr(ps_intrs[11]), - .motcon2_c_m1_intr(ps_intrs[10]), - .motcon2_ctrl_m1_intr(ps_intrs[9]), - .motcon2_s_d2_intr(ps_intrs[8]), - .motcon2_c_m2_intr(ps_intrs[7]), - .motcon2_ctrl_m2_intr(ps_intrs[6]), .iic_ee2_scl_io(iic_ee2_scl_io), .iic_ee2_sda_io(iic_ee2_sda_io), .spi_csn_i (1'b1), From 61e874aa9bc3333da60a46abefe86b99c184f724 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:58:52 +0200 Subject: [PATCH 76/91] zed: Changed based design not to export interrutps to the system_top file --- projects/common/zed/zed_system_bd.tcl | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/projects/common/zed/zed_system_bd.tcl b/projects/common/zed/zed_system_bd.tcl index 008895515..c2cb48a5d 100644 --- a/projects/common/zed/zed_system_bd.tcl +++ b/projects/common/zed/zed_system_bd.tcl @@ -41,8 +41,6 @@ set otg_vbusoc [create_bd_port -dir I otg_vbusoc] set spdif [create_bd_port -dir O spdif] -set iic_fmc_intr [create_bd_port -dir O iic_fmc_intr] - # instance: sys_ps7 set sys_ps7 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.4 sys_ps7] @@ -275,8 +273,6 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_iic_fmc/s_axi_aresetn] connect_bd_intf_net -intf_net axi_iic_fmc_iic [get_bd_intf_ports IIC_FMC] [get_bd_intf_pins axi_iic_fmc/iic] -connect_bd_net -net axi_iic_fmc_intr [get_bd_pins axi_iic_fmc/iic2intc_irpt] [get_bd_ports iic_fmc_intr] - # interrupts connect_bd_net [get_bd_pins sys_concat_intc/dout] [get_bd_pins sys_ps7/IRQ_F2P] @@ -288,6 +284,9 @@ for {set intc_index 0} {$intc_index < 14} {incr intc_index} { connect_bd_net -net ps_intr_${intc_index}_s [get_bd_pins sys_concat_intc/In${intc_index}] [get_bd_ports ps_intr_${intc_index}] } +delete_bd_objs [get_bd_nets ps_intr_11_s] [get_bd_ports ps_intr_11] +connect_bd_net -net axi_iic_fmc_intr [get_bd_pins axi_iic_fmc/iic2intc_irpt] [get_bd_pins sys_concat_intc/In11] + # address map set sys_zynq 1 From 05489568119c3924b7a280a8c4dc9b81766f6eda Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 13:59:58 +0200 Subject: [PATCH 77/91] adv7511_zed: Modified project to be compatible with the new base design --- projects/adv7511/zed/system_top.v | 2 -- 1 file changed, 2 deletions(-) diff --git a/projects/adv7511/zed/system_top.v b/projects/adv7511/zed/system_top.v index 4c3514059..66c2cda63 100644 --- a/projects/adv7511/zed/system_top.v +++ b/projects/adv7511/zed/system_top.v @@ -228,10 +228,8 @@ module system_top ( .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), .ps_intr_12 (ps_intrs[12]), .ps_intr_13 (ps_intrs[13]), - .iic_fmc_intr (ps_intrs[11]), .otg_vbusoc (otg_vbusoc), .spdif (spdif)); From 64c4ff4a4d1fe4769b5679b4173ecf653f08f7b8 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 14:00:36 +0200 Subject: [PATCH 78/91] fmcomms2: Modified zed project to be compatible with the new base design --- projects/fmcomms2/zed/system_top.v | 2 -- 1 file changed, 2 deletions(-) diff --git a/projects/fmcomms2/zed/system_top.v b/projects/fmcomms2/zed/system_top.v index 9cef3446c..02c66c156 100644 --- a/projects/fmcomms2/zed/system_top.v +++ b/projects/fmcomms2/zed/system_top.v @@ -281,7 +281,6 @@ module system_top ( .ps_intr_0 (ps_intrs[0]), .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), - .ps_intr_11 (ps_intrs[11]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -290,7 +289,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .iic_fmc_intr(ps_intrs[11]), .otg_vbusoc (otg_vbusoc), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), From f3600b26a0c9f25ebaa8eaeb5288f81e66f13035 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Wed, 18 Mar 2015 17:04:06 +0200 Subject: [PATCH 79/91] fmcomms2_pr: Updated project with interrupts in IPI to work correctly in Linux --- projects/fmcomms2_pr/mitx045/system_top.v | 4 ---- projects/fmcomms2_pr/zc706/system_top.v | 4 ---- 2 files changed, 8 deletions(-) diff --git a/projects/fmcomms2_pr/mitx045/system_top.v b/projects/fmcomms2_pr/mitx045/system_top.v index 27ec4726c..522468127 100644 --- a/projects/fmcomms2_pr/mitx045/system_top.v +++ b/projects/fmcomms2_pr/mitx045/system_top.v @@ -287,8 +287,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -297,8 +295,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), diff --git a/projects/fmcomms2_pr/zc706/system_top.v b/projects/fmcomms2_pr/zc706/system_top.v index 012ae0e83..ca9103924 100644 --- a/projects/fmcomms2_pr/zc706/system_top.v +++ b/projects/fmcomms2_pr/zc706/system_top.v @@ -276,8 +276,6 @@ module system_top ( .ps_intr_1 (ps_intrs[1]), .ps_intr_10 (ps_intrs[10]), .ps_intr_11 (ps_intrs[11]), - .ps_intr_12 (ps_intrs[12]), - .ps_intr_13 (ps_intrs[13]), .ps_intr_2 (ps_intrs[2]), .ps_intr_3 (ps_intrs[3]), .ps_intr_4 (ps_intrs[4]), @@ -286,8 +284,6 @@ module system_top ( .ps_intr_7 (ps_intrs[7]), .ps_intr_8 (ps_intrs[8]), .ps_intr_9 (ps_intrs[9]), - .ad9361_dac_dma_irq (ps_intrs[12]), - .ad9361_adc_dma_irq (ps_intrs[13]), .rx_clk_in_n (rx_clk_in_n), .rx_clk_in_p (rx_clk_in_p), .rx_data_in_n (rx_data_in_n), From 17936b42952a68103e2e8bd5ae2d67ae645e086a Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 20 Mar 2015 15:29:03 +0200 Subject: [PATCH 80/91] ad9265_fmc: Correctly connected the interrupts --- projects/ad9265_fmc/common/ad9265_bd.tcl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl index ad14b6da3..4370628ad 100644 --- a/projects/ad9265_fmc/common/ad9265_bd.tcl +++ b/projects/ad9265_fmc/common/ad9265_bd.tcl @@ -165,11 +165,12 @@ if {$sys_zynq == 0} { if {$sys_zynq == 0} { delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] - connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_ports sys_concat_intc/In10] - connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports sys_concat_intc/In12] + connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_pins sys_concat_intc/In12] } else { delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] - connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports sys_concat_intc/In12] + connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net [get_bd_nets axi_ad9265_dma_irq] [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9265_dma/irq] } # interconnect (mem/adc) From 5f038d540b1e544e332032cc26a0fe402df576ca Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 20 Mar 2015 15:29:03 +0200 Subject: [PATCH 81/91] ad9265_fmc: Correctly connected the interrupts --- projects/ad9265_fmc/common/ad9265_bd.tcl | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl index ad14b6da3..4370628ad 100644 --- a/projects/ad9265_fmc/common/ad9265_bd.tcl +++ b/projects/ad9265_fmc/common/ad9265_bd.tcl @@ -165,11 +165,12 @@ if {$sys_zynq == 0} { if {$sys_zynq == 0} { delete_bd_objs [get_bd_nets mb_intr_10_s] [get_bd_ports mb_intr_10] delete_bd_objs [get_bd_nets mb_intr_12_s] [get_bd_ports mb_intr_12] - connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_ports sys_concat_intc/In10] - connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports sys_concat_intc/In12] + connect_bd_net -net axi_ad9265_spi_irq [get_bd_pins axi_ad9265_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In10] + connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_pins sys_concat_intc/In12] } else { delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] - connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_ports sys_concat_intc/In12] + connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_pins sys_concat_intc/In12] + connect_bd_net -net [get_bd_nets axi_ad9265_dma_irq] [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9265_dma/irq] } # interconnect (mem/adc) From e8bac717157f2a7ada993b1029eb853f0e923856 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 23 Mar 2015 11:52:55 +0200 Subject: [PATCH 82/91] ad9265: Fixed interrupt connection --- projects/ad9265_fmc/common/ad9265_bd.tcl | 1 - 1 file changed, 1 deletion(-) diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl index 4370628ad..3a23edece 100644 --- a/projects/ad9265_fmc/common/ad9265_bd.tcl +++ b/projects/ad9265_fmc/common/ad9265_bd.tcl @@ -170,7 +170,6 @@ if {$sys_zynq == 0} { } else { delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_pins sys_concat_intc/In12] - connect_bd_net -net [get_bd_nets axi_ad9265_dma_irq] [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9265_dma/irq] } # interconnect (mem/adc) From 807a0b6e0a4191a5377396fe92e6c482cfc30a99 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Mon, 23 Mar 2015 11:52:55 +0200 Subject: [PATCH 83/91] ad9265: Fixed interrupt connection --- projects/ad9265_fmc/common/ad9265_bd.tcl | 1 - 1 file changed, 1 deletion(-) diff --git a/projects/ad9265_fmc/common/ad9265_bd.tcl b/projects/ad9265_fmc/common/ad9265_bd.tcl index 4370628ad..3a23edece 100644 --- a/projects/ad9265_fmc/common/ad9265_bd.tcl +++ b/projects/ad9265_fmc/common/ad9265_bd.tcl @@ -170,7 +170,6 @@ if {$sys_zynq == 0} { } else { delete_bd_objs [get_bd_nets ps_intr_12_s] [get_bd_ports ps_intr_12] connect_bd_net -net axi_ad9265_dma_irq [get_bd_pins axi_ad9265_dma/irq] [get_bd_pins sys_concat_intc/In12] - connect_bd_net -net [get_bd_nets axi_ad9265_dma_irq] [get_bd_pins sys_concat_intc/In12] [get_bd_pins axi_ad9265_dma/irq] } # interconnect (mem/adc) From 2c9b7b9300df7e07ff95875aa3ed15a7e78744c5 Mon Sep 17 00:00:00 2001 From: dbogdan Date: Wed, 1 Apr 2015 13:51:32 +0300 Subject: [PATCH 84/91] projects/fmcomms2/c5soc: Add GPIO support. --- projects/fmcomms2/c5soc/system_bd.qsys | 66 +++++++++++++++++++--- projects/fmcomms2/c5soc/system_project.tcl | 8 +++ projects/fmcomms2/c5soc/system_top.v | 17 ++++-- 3 files changed, 78 insertions(+), 13 deletions(-) diff --git a/projects/fmcomms2/c5soc/system_bd.qsys b/projects/fmcomms2/c5soc/system_bd.qsys index 07e6fd46a..dc9c8c022 100644 --- a/projects/fmcomms2/c5soc/system_bd.qsys +++ b/projects/fmcomms2/c5soc/system_bd.qsys @@ -81,6 +81,22 @@ type = "String"; } } + element gpio + { + datum _sortIndex + { + value = "15"; + type = "int"; + } + } + element gpio.s1 + { + datum baseAddress + { + value = "65680"; + type = "String"; + } + } element sys_int_mem.s1 { datum baseAddress @@ -102,6 +118,14 @@ type = "String"; } } + element axi_dmac_dac.s_axi + { + datum baseAddress + { + value = "16384"; + type = "String"; + } + } element axi_ad9361.s_axi { datum baseAddress @@ -118,14 +142,6 @@ type = "String"; } } - element axi_dmac_dac.s_axi - { - datum baseAddress - { - value = "16384"; - type = "String"; - } - } element spi_ad9361 { datum _sortIndex @@ -367,6 +383,11 @@ internal="util_dac_unpack.channels_data" type="conduit" dir="end" /> + @@ -1281,6 +1302,20 @@ + + + + + + + + + + + + + + + + + + + + + Date: Wed, 1 Apr 2015 13:51:32 +0300 Subject: [PATCH 85/91] projects/fmcomms2/c5soc: Add GPIO support. --- projects/fmcomms2/c5soc/system_bd.qsys | 66 +++++++++++++++++++--- projects/fmcomms2/c5soc/system_project.tcl | 8 +++ projects/fmcomms2/c5soc/system_top.v | 17 ++++-- 3 files changed, 78 insertions(+), 13 deletions(-) diff --git a/projects/fmcomms2/c5soc/system_bd.qsys b/projects/fmcomms2/c5soc/system_bd.qsys index 07e6fd46a..dc9c8c022 100644 --- a/projects/fmcomms2/c5soc/system_bd.qsys +++ b/projects/fmcomms2/c5soc/system_bd.qsys @@ -81,6 +81,22 @@ type = "String"; } } + element gpio + { + datum _sortIndex + { + value = "15"; + type = "int"; + } + } + element gpio.s1 + { + datum baseAddress + { + value = "65680"; + type = "String"; + } + } element sys_int_mem.s1 { datum baseAddress @@ -102,6 +118,14 @@ type = "String"; } } + element axi_dmac_dac.s_axi + { + datum baseAddress + { + value = "16384"; + type = "String"; + } + } element axi_ad9361.s_axi { datum baseAddress @@ -118,14 +142,6 @@ type = "String"; } } - element axi_dmac_dac.s_axi - { - datum baseAddress - { - value = "16384"; - type = "String"; - } - } element spi_ad9361 { datum _sortIndex @@ -367,6 +383,11 @@ internal="util_dac_unpack.channels_data" type="conduit" dir="end" /> + @@ -1281,6 +1302,20 @@ + + + + + + + + + + + + + + + + + + + + + Date: Wed, 1 Apr 2015 11:52:45 +0200 Subject: [PATCH 86/91] axi_dmac: Reset data stream resize blocks when disabled When the DMA controller gets disabled in the middle of a transfer it is possible that the resize block contains a partial sample. Starting the next transfer the partial sample will appear the begining of the new stream and also cause a channel shift. To avoid this make sure to reset and flush the resize blocks when the DMA controller is disabled. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_arb.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 0d3d146d4..17b584adf 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -806,7 +806,7 @@ axi_repack #( .C_M_DATA_WIDTH(DMA_DATA_WIDTH) ) i_src_repack ( .clk(src_clk), - .resetn(src_resetn), + .resetn(src_resetn & src_enable), .s_valid(src_fifo_valid), .s_ready(src_fifo_ready), .s_data(src_fifo_data), @@ -839,7 +839,7 @@ axi_repack #( .C_M_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST) ) i_dest_repack ( .clk(dest_clk), - .resetn(dest_resetn), + .resetn(dest_resetn & dest_enable), .s_valid(dest_fifo_valid), .s_ready(dest_fifo_ready), .s_data(dest_fifo_data), From a4766c2140ec8bb08211c5d6a9d17b1bf908cf9b Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 2 Apr 2015 12:30:53 -0400 Subject: [PATCH 87/91] fmcomms7: dac lane-mux --- projects/fmcomms7/common/fmcomms7_bd.tcl | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/projects/fmcomms7/common/fmcomms7_bd.tcl b/projects/fmcomms7/common/fmcomms7_bd.tcl index 799041945..4cfcabe3a 100644 --- a/projects/fmcomms7/common/fmcomms7_bd.tcl +++ b/projects/fmcomms7/common/fmcomms7_bd.tcl @@ -138,14 +138,14 @@ if {$sys_zynq == 1} { set axi_fmcomms7_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_fmcomms7_gt] set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {8}] $axi_fmcomms7_gt set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {4}] $axi_fmcomms7_gt - set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {0}] $axi_fmcomms7_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_0 {5}] $axi_fmcomms7_gt set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_1 {3}] $axi_fmcomms7_gt - set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {1}] $axi_fmcomms7_gt - set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {2}] $axi_fmcomms7_gt - set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_4 {4}] $axi_fmcomms7_gt - set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_5 {5}] $axi_fmcomms7_gt - set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_6 {6}] $axi_fmcomms7_gt - set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_7 {7}] $axi_fmcomms7_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_2 {6}] $axi_fmcomms7_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_3 {7}] $axi_fmcomms7_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_4 {2}] $axi_fmcomms7_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_5 {0}] $axi_fmcomms7_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_6 {1}] $axi_fmcomms7_gt + set_property -dict [list CONFIG.PCORE_TX_LANE_SEL_7 {4}] $axi_fmcomms7_gt if {$sys_zynq == 1} { From 714ea29171ff63711fe93f347826d0b7d8e98f19 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 2 Apr 2015 12:30:58 -0400 Subject: [PATCH 88/91] fmcomms7: dac lane-mux --- projects/fmcomms7/zc706/system_constr.xdc | 28 +++++++++++------------ 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/projects/fmcomms7/zc706/system_constr.xdc b/projects/fmcomms7/zc706/system_constr.xdc index 32c7c0529..7238bdaf0 100644 --- a/projects/fmcomms7/zc706/system_constr.xdc +++ b/projects/fmcomms7/zc706/system_constr.xdc @@ -17,22 +17,22 @@ set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ set_property -dict {PACKAGE_PIN AD10} [get_ports tx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P set_property -dict {PACKAGE_PIN AD9 } [get_ports tx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N -set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[0]) -set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN AK2 } [get_ports tx_data_p[0]] ; ## A30 FMC_HPC_DP3_C2M_P (tx_data_p[5]) +set_property -dict {PACKAGE_PIN AK1 } [get_ports tx_data_n[0]] ; ## A31 FMC_HPC_DP3_C2M_N (tx_data_n[5]) set_property -dict {PACKAGE_PIN AK10} [get_ports tx_data_p[1]] ; ## C02 FMC_HPC_DP0_C2M_P (tx_data_p[3]) set_property -dict {PACKAGE_PIN AK9 } [get_ports tx_data_n[1]] ; ## C03 FMC_HPC_DP0_C2M_N (tx_data_n[3]) -set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[1]) -set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[1]) -set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[2]) -set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[2]) -set_property -dict {PACKAGE_PIN AH2 } [get_ports tx_data_p[4]] ; ## A34 FMC_HPC_DP4_C2M_P (tx_data_p[4]) -set_property -dict {PACKAGE_PIN AH1 } [get_ports tx_data_n[4]] ; ## A35 FMC_HPC_DP4_C2M_N (tx_data_n[4]) -set_property -dict {PACKAGE_PIN AF2 } [get_ports tx_data_p[5]] ; ## A38 FMC_HPC_DP5_C2M_P (tx_data_p[5]) -set_property -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[5]] ; ## A39 FMC_HPC_DP5_C2M_N (tx_data_n[5]) -set_property -dict {PACKAGE_PIN AE4 } [get_ports tx_data_p[6]] ; ## B36 FMC_HPC_DP6_C2M_P (tx_data_p[6]) -set_property -dict {PACKAGE_PIN AE3 } [get_ports tx_data_n[6]] ; ## B37 FMC_HPC_DP6_C2M_N (tx_data_n[6]) -set_property -dict {PACKAGE_PIN AD2 } [get_ports tx_data_p[7]] ; ## B32 FMC_HPC_DP7_C2M_P (tx_data_p[7]) -set_property -dict {PACKAGE_PIN AD1 } [get_ports tx_data_n[7]] ; ## B33 FMC_HPC_DP7_C2M_N (tx_data_n[7]) +set_property -dict {PACKAGE_PIN AJ4 } [get_ports tx_data_p[2]] ; ## A26 FMC_HPC_DP2_C2M_P (tx_data_p[6]) +set_property -dict {PACKAGE_PIN AJ3 } [get_ports tx_data_n[2]] ; ## A27 FMC_HPC_DP2_C2M_N (tx_data_n[6]) +set_property -dict {PACKAGE_PIN AK6 } [get_ports tx_data_p[3]] ; ## A22 FMC_HPC_DP1_C2M_P (tx_data_p[7]) +set_property -dict {PACKAGE_PIN AK5 } [get_ports tx_data_n[3]] ; ## A23 FMC_HPC_DP1_C2M_N (tx_data_n[7]) +set_property -dict {PACKAGE_PIN AH2 } [get_ports tx_data_p[4]] ; ## A34 FMC_HPC_DP4_C2M_P (tx_data_p[2]) +set_property -dict {PACKAGE_PIN AH1 } [get_ports tx_data_n[4]] ; ## A35 FMC_HPC_DP4_C2M_N (tx_data_n[2]) +set_property -dict {PACKAGE_PIN AF2 } [get_ports tx_data_p[5]] ; ## A38 FMC_HPC_DP5_C2M_P (tx_data_p[0]) +set_property -dict {PACKAGE_PIN AF1 } [get_ports tx_data_n[5]] ; ## A39 FMC_HPC_DP5_C2M_N (tx_data_n[0]) +set_property -dict {PACKAGE_PIN AE4 } [get_ports tx_data_p[6]] ; ## B36 FMC_HPC_DP6_C2M_P (tx_data_p[1]) +set_property -dict {PACKAGE_PIN AE3 } [get_ports tx_data_n[6]] ; ## B37 FMC_HPC_DP6_C2M_N (tx_data_n[1]) +set_property -dict {PACKAGE_PIN AD2 } [get_ports tx_data_p[7]] ; ## B32 FMC_HPC_DP7_C2M_P (tx_data_p[4]) +set_property -dict {PACKAGE_PIN AD1 } [get_ports tx_data_n[7]] ; ## B33 FMC_HPC_DP7_C2M_N (tx_data_n[4]) set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync0_p] ; ## H07 FMC_HPC_LA02_P set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync0_n] ; ## H08 FMC_HPC_LA02_N set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_sync1_p] ; ## H19 FMC_HPC_LA15_P From 6551672ce590650ebd485b1751df6e0ce7234bb5 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 23 Apr 2015 17:56:35 +0300 Subject: [PATCH 89/91] fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples. The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells. This is a the maximum BRAM FIFO depth in case of the VC707. --- projects/fmcadc2/vc707/system_bd.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/fmcadc2/vc707/system_bd.tcl b/projects/fmcadc2/vc707/system_bd.tcl index b94ea5ac4..437a6f4f6 100644 --- a/projects/fmcadc2/vc707/system_bd.tcl +++ b/projects/fmcadc2/vc707/system_bd.tcl @@ -2,7 +2,7 @@ source $ad_hdl_dir/projects/common/vc707/vc707_system_bd.tcl source $ad_hdl_dir/projects/common/xilinx/sys_dmafifo.tcl -p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 10 +p_sys_dmafifo [current_bd_instance .] axi_ad9625_fifo 256 18 source ../common/fmcadc2_bd.tcl From 1cefee4736ba78c06898572ed497280729bd2c01 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 8 May 2015 18:39:23 +0300 Subject: [PATCH 90/91] adv7511: updated AC701 project to work at full hd resolution --- projects/adv7511/ac701/system_bd.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/adv7511/ac701/system_bd.tcl b/projects/adv7511/ac701/system_bd.tcl index 60356edce..c265ed183 100644 --- a/projects/adv7511/ac701/system_bd.tcl +++ b/projects/adv7511/ac701/system_bd.tcl @@ -3,4 +3,6 @@ source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect +set_property -dict [list CONFIG.c_m_axi_mm2s_data_width {512}] $axi_hdmi_dma +set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma From c3939605769b6d39d33e912e8e7cc1b057f68068 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 8 May 2015 18:39:23 +0300 Subject: [PATCH 91/91] adv7511: updated AC701 project to work at full hd resolution --- projects/adv7511/ac701/system_bd.tcl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/adv7511/ac701/system_bd.tcl b/projects/adv7511/ac701/system_bd.tcl index 60356edce..c265ed183 100644 --- a/projects/adv7511/ac701/system_bd.tcl +++ b/projects/adv7511/ac701/system_bd.tcl @@ -3,4 +3,6 @@ source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl set_property -dict [list CONFIG.NUM_MI {7}] $axi_cpu_interconnect set_property -dict [list CONFIG.NUM_SI {8}] $axi_mem_interconnect set_property -dict [list CONFIG.NUM_MI {1}] $axi_mem_interconnect +set_property -dict [list CONFIG.c_m_axi_mm2s_data_width {512}] $axi_hdmi_dma +set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma