From 516fb62b197d27d7bd8de508f9bc54367047caca Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Wed, 1 Apr 2015 11:52:45 +0200 Subject: [PATCH] axi_dmac: Reset data stream resize blocks when disabled When the DMA controller gets disabled in the middle of a transfer it is possible that the resize block contains a partial sample. Starting the next transfer the partial sample will appear the begining of the new stream and also cause a channel shift. To avoid this make sure to reset and flush the resize blocks when the DMA controller is disabled. Signed-off-by: Lars-Peter Clausen --- library/axi_dmac/request_arb.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/library/axi_dmac/request_arb.v b/library/axi_dmac/request_arb.v index 0d3d146d4..17b584adf 100644 --- a/library/axi_dmac/request_arb.v +++ b/library/axi_dmac/request_arb.v @@ -806,7 +806,7 @@ axi_repack #( .C_M_DATA_WIDTH(DMA_DATA_WIDTH) ) i_src_repack ( .clk(src_clk), - .resetn(src_resetn), + .resetn(src_resetn & src_enable), .s_valid(src_fifo_valid), .s_ready(src_fifo_ready), .s_data(src_fifo_data), @@ -839,7 +839,7 @@ axi_repack #( .C_M_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST) ) i_dest_repack ( .clk(dest_clk), - .resetn(dest_resetn), + .resetn(dest_resetn & dest_enable), .s_valid(dest_fifo_valid), .s_ready(dest_fifo_ready), .s_data(dest_fifo_data),