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axi_dmac: Reset data stream resize blocks when disabled 

When the DMA controller gets disabled in the middle of a transfer it is
possible that the resize block contains a partial sample. Starting the next
transfer the partial sample will appear the begining of the new stream and
also cause a channel shift.

To avoid this make sure to reset and flush the resize blocks when the DMA
controller is disabled.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2015-04-01 11:52:45 +02:00
parent 28d79d27b8
commit 516fb62b19
1 changed files with 2 additions and 2 deletions
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4
library/axi_dmac/request_arb.v
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@ -806,7 +806,7 @@ axi_repack #(
.C_M_DATA_WIDTH(DMA_DATA_WIDTH) .C_M_DATA_WIDTH(DMA_DATA_WIDTH)
) i_src_repack ( ) i_src_repack (
.clk(src_clk), .clk(src_clk),
.resetn(src_resetn), .resetn(src_resetn & src_enable),
.s_valid(src_fifo_valid), .s_valid(src_fifo_valid),
.s_ready(src_fifo_ready), .s_ready(src_fifo_ready),
.s_data(src_fifo_data), .s_data(src_fifo_data),
@ -839,7 +839,7 @@ axi_repack #(
.C_M_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST) .C_M_DATA_WIDTH(C_DMA_DATA_WIDTH_DEST)
) i_dest_repack ( ) i_dest_repack (
.clk(dest_clk), .clk(dest_clk),
.resetn(dest_resetn), .resetn(dest_resetn & dest_enable),
.s_valid(dest_fifo_valid), .s_valid(dest_fifo_valid),
.s_ready(dest_fifo_ready), .s_ready(dest_fifo_ready),
.s_data(dest_fifo_data), .s_data(dest_fifo_data),