ml605: tcl updates
Rejeesh Kutty
parent
e7cbaca216
commit
51c0ee1e20
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@ -1,89 +1,60 @@
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set project_name "fmcomms2_ml605"
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set project_part "xc6vlx240tff1156-1"
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set project_board "ml605"
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set project_system_dir "./$project_name.srcs/sources_1/edk/$project_board"
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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create_project $project_name . -part $project_part -force
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set_property board $project_board [current_project]
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adi_project_create fmcomms2_ml605
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adi_project_files fmcomms2_ml605 [list \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/ad_mul_u16.v" \
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"$ad_hdl_dir/library/common/ad_dds_sine.v" \
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"$ad_hdl_dir/library/common/ad_dds_1.v" \
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"$ad_hdl_dir/library/common/ad_dds.v" \
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"$ad_hdl_dir/library/common/ad_datafmt.v" \
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"$ad_hdl_dir/library/common/ad_dcfilter.v" \
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"$ad_hdl_dir/library/common/ad_iqcor.v" \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
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"$ad_hdl_dir/library/common/up_xfer_status.v" \
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"$ad_hdl_dir/library/common/up_clock_mon.v" \
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"$ad_hdl_dir/library/common/up_delay_cntrl.v" \
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"$ad_hdl_dir/library/common/up_drp_cntrl.v" \
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"$ad_hdl_dir/library/common/up_adc_common.v" \
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"$ad_hdl_dir/library/common/up_adc_channel.v" \
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"$ad_hdl_dir/library/common/up_dac_common.v" \
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"$ad_hdl_dir/library/common/up_dac_channel.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_dev_if.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_pnlb.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx_pnmon.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx_channel.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_rx.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx_dds.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx_channel.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361_tx.v" \
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"$ad_hdl_dir/library/axi_ad9361/axi_ad9361.v" \
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"$ad_hdl_dir/library/common/sync_bits.v" \
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"$ad_hdl_dir/library/common/sync_gray.v" \
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"$ad_hdl_dir/library/axi_fifo/axi_fifo.v" \
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"$ad_hdl_dir/library/axi_fifo/address_gray.v" \
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"$ad_hdl_dir/library/axi_fifo/address_gray_pipelined.v" \
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"$ad_hdl_dir/library/axi_dmac/address_generator.v" \
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"$ad_hdl_dir/library/axi_dmac/data_mover.v" \
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"$ad_hdl_dir/library/axi_dmac/request_arb.v" \
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"$ad_hdl_dir/library/axi_dmac/request_generator.v" \
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"$ad_hdl_dir/library/axi_dmac/response_handler.v" \
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"$ad_hdl_dir/library/axi_dmac/axi_register_slice.v" \
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"$ad_hdl_dir/library/axi_dmac/2d_transfer.v" \
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"$ad_hdl_dir/library/axi_dmac/dest_axi_mm.v" \
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"$ad_hdl_dir/library/axi_dmac/dest_axi_stream.v" \
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"$ad_hdl_dir/library/axi_dmac/dest_fifo_inf.v" \
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"$ad_hdl_dir/library/axi_dmac/src_axi_mm.v" \
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"$ad_hdl_dir/library/axi_dmac/src_axi_stream.v" \
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"$ad_hdl_dir/library/axi_dmac/src_fifo_inf.v" \
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"$ad_hdl_dir/library/axi_dmac/splitter.v" \
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"$ad_hdl_dir/library/axi_dmac/response_generator.v" \
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"$ad_hdl_dir/library/axi_dmac/axi_dmac.v" \
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"$ad_hdl_dir/library/axi_dmac/axi_repack.v" \
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"system_constr.ucf" \
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"system_top.v" ]
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import_files -norecurse ../../common/ml605/system.xmp
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adi_project_run fmcomms2_ml605
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generate_target {synthesis implementation} [get_files $project_system_dir/system.xmp]
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make_wrapper -files [get_files $project_system_dir/system.xmp] -top
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import_files -force -norecurse -fileset sources_1 $project_system_dir/system_stub.v
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add_files -norecurse c:/github/hdl/library/common/ad_rst.v
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add_files -norecurse c:/github/hdl/library/common/ad_mul_u16.v
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add_files -norecurse c:/github/hdl/library/common/ad_dds_sine.v
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add_files -norecurse c:/github/hdl/library/common/ad_dds_1.v
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add_files -norecurse c:/github/hdl/library/common/ad_dds.v
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add_files -norecurse c:/github/hdl/library/common/ad_datafmt.v
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add_files -norecurse c:/github/hdl/library/common/ad_dcfilter.v
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add_files -norecurse c:/github/hdl/library/common/ad_iqcor.v
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add_files -norecurse c:/github/hdl/library/common/up_axi.v
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add_files -norecurse c:/github/hdl/library/common/up_xfer_cntrl.v
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add_files -norecurse c:/github/hdl/library/common/up_xfer_status.v
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add_files -norecurse c:/github/hdl/library/common/up_clock_mon.v
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add_files -norecurse c:/github/hdl/library/common/up_delay_cntrl.v
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add_files -norecurse c:/github/hdl/library/common/up_drp_cntrl.v
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add_files -norecurse c:/github/hdl/library/common/up_adc_common.v
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add_files -norecurse c:/github/hdl/library/common/up_adc_channel.v
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add_files -norecurse c:/github/hdl/library/common/up_dac_common.v
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add_files -norecurse c:/github/hdl/library/common/up_dac_channel.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_dev_if.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_pnlb.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_rx_pnmon.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_rx_channel.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_rx.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_tx_dds.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_tx_channel.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361_tx.v
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add_files -norecurse c:/github/hdl/library/axi_ad9361/axi_ad9361.v
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add_files -norecurse c:/github/hdl/library/common/sync_bits.v
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add_files -norecurse c:/github/hdl/library/common/sync_gray.v
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add_files -norecurse c:/github/hdl/library/axi_fifo/axi_fifo.v
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add_files -norecurse c:/github/hdl/library/axi_fifo/address_gray.v
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add_files -norecurse c:/github/hdl/library/axi_fifo/address_gray_pipelined.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/address_generator.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/data_mover.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/request_arb.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/request_generator.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/response_handler.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/axi_register_slice.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/2d_transfer.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/dest_axi_mm.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/dest_axi_stream.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/dest_fifo_inf.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/src_axi_mm.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/src_axi_stream.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/src_fifo_inf.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/splitter.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/response_generator.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/axi_dmac.v
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add_files -norecurse c:/github/hdl/library/axi_dmac/axi_repack.v
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add_files -norecurse system_constr.ucf
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add_files -norecurse system_top.v
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set_property top system_top [current_fileset]
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set_property strategy MapTiming [get_runs impl_1]
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set_property strategy TimingWithIOBPacking [get_runs synth_1]
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launch_runs synth_1
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wait_on_run synth_1
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open_run synth_1
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report_timing_summary -file timing_synth.log
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launch_runs impl_1 -to_step bitgen
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wait_on_run impl_1
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open_run impl_1
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report_timing_summary -file timing_impl.log
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if [expr [get_property SLACK [get_timing_paths]] < 0] {
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puts "ERROR: Timing Constraints NOT met."
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use_this_invalid_command_to_crash
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}
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export_hardware [get_files $project_system_dir/system.xmp] [get_runs impl_1] -bitstream
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@ -11,6 +11,11 @@ proc adi_project_create {project_name} {
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set project_part "none"
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set project_board "none"
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if [regexp "_ml605$" $project_name] {
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set xl_board "ml605"
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set project_part "xc6vlx240tff1156-1"
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set project_board "ml605"
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}
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if [regexp "_ac701$" $project_name] {
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set xl_board "ac701"
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set project_part "xc7a200tfbg676-2"
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@ -47,6 +52,26 @@ proc adi_project_create {project_name} {
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set project_board "xilinx.com:zynq:zc706:1.1"
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}
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# planahead - 6 and down
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if {$xl_board eq "ml605"} {
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set project_system_dir "./$project_name.srcs/sources_1/edk/$xl_board"
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create_project $project_name . -part $project_part -force
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set_property board $project_board [current_project]
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import_files -norecurse $ad_hdl_dir/projects/common/ml605/system.xmp
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generate_target {synthesis implementation} [get_files $project_system_dir/system.xmp]
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make_wrapper -files [get_files $project_system_dir/system.xmp] -top
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import_files -force -norecurse -fileset sources_1 $project_system_dir/system_stub.v
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return
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}
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# vivado - 7 and up
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set project_system_dir "./$project_name.srcs/sources_1/bd/system"
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create_project $project_name . -part $project_part -force
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@ -83,6 +108,39 @@ proc adi_project_run {project_name} {
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global ad_hdl_dir
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global ad_phdl_dir
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global xl_board
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# planahead - 6 and down
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if {$xl_board eq "ml605"} {
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set project_system_dir "./$project_name.srcs/sources_1/edk/$xl_board"
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set_property strategy MapTiming [get_runs impl_1]
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set_property strategy TimingWithIOBPacking [get_runs synth_1]
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launch_runs synth_1
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wait_on_run synth_1
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open_run synth_1
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report_timing -file timing_synth.log
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launch_runs impl_1 -to_step bitgen
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wait_on_run impl_1
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open_run impl_1
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report_timing -file timing_impl.log
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# -- Unable to find an equivalent
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#if [expr [get_property SLACK [get_timing_paths]] < 0] {
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# puts "ERROR: Timing Constraints NOT met."
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# use_this_invalid_command_to_crash
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#}
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export_hardware [get_files $project_system_dir/system.xmp] [get_runs impl_1] -bitstream
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return
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}
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# vivado - 7 and up
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set project_system_dir "./$project_name.srcs/sources_1/bd/system"
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