axi_ad9250: Port redeclaration as a wire is not allowed

2017-04-20 10:50:21 +03:00 · 2017-04-20 10:50:21 +03:00 · 5294e238d2
parent 6ab8624a06
commit 5294e238d2
1 changed files with 6 additions and 7 deletions
--- a/library/axi_ad9250/axi_ad9250.v
+++ b/library/axi_ad9250/axi_ad9250.v
@ -100,7 +100,6 @@ module axi_ad9250 #(
  // internal clocks & resets
  wire            adc_rst;
  wire            up_rstn;
  wire            up_clk;