daq2: Parameterize JESD204 configuration values
Added the capability to set the JESD204 configuration values from a single point in the code and to modify these default settings from the command line for the Xilinx FPGAs in the project. Signed-off-by: Dan Hotoleanu <dan.hotoleanu@analog.com>main
Dan Hotoleanu
hotoleanudan
parent
f3cf7508c8
commit
530aca9754
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@ -1,25 +1,34 @@
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#
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# Parameter description:
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_S : Number of samples per frame
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#
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl
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# JESD204B interface configurations
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set TX_NUM_OF_LANES 4 ; # L
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set TX_NUM_OF_CONVERTERS 2 ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L
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set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M
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set TX_SAMPLES_PER_FRAME $ad_project_params(TX_JESD_S) ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL [expr $TX_NUM_OF_LANES * 32 / ($TX_NUM_OF_CONVERTERS * $TX_SAMPLE_WIDTH)]
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set dac_data_width [expr $TX_SAMPLE_WIDTH * $TX_NUM_OF_CONVERTERS * $TX_SAMPLES_PER_CHANNEL]
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 2 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
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set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
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set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
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set MAX_TX_NUM_OF_LANES 4
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set MAX_RX_NUM_OF_LANES 4
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# dac peripherals
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ad_ip_instance axi_adxcvr axi_ad9144_xcvr [list \
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@ -36,9 +45,9 @@ adi_tpl_jesd204_tx_create axi_ad9144_tpl $TX_NUM_OF_LANES \
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$TX_SAMPLE_WIDTH \
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ad_ip_instance util_upack2 axi_ad9144_upack [list \
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NUM_OF_CHANNELS 2 \
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SAMPLES_PER_CHANNEL 4 \
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SAMPLE_DATA_WIDTH 16 \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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ad_ip_instance axi_dmac axi_ad9144_dma [list \
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@ -118,8 +127,8 @@ ad_connect axi_ad9680_offload/sync_ext GND
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# shared transceiver core
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ad_ip_instance util_adxcvr util_daq2_xcvr [list \
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RX_NUM_OF_LANES $RX_NUM_OF_LANES \
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TX_NUM_OF_LANES $TX_NUM_OF_LANES \
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RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \
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TX_NUM_OF_LANES $MAX_TX_NUM_OF_LANES \
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QPLL_REFCLK_DIV 1 \
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QPLL_FBDIV_RATIO 1 \
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QPLL_FBDIV 0x30 \
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@ -144,7 +153,7 @@ ad_xcvrpll axi_ad9680_xcvr/up_pll_rst util_daq2_xcvr/up_cpll_rst_*
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# connections (dac)
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ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1}
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ad_xcvrcon util_daq2_xcvr axi_ad9144_xcvr axi_ad9144_jesd {0 2 3 1} {} {} $MAX_TX_NUM_OF_LANES
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ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_tpl/link_clk
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ad_connect axi_ad9144_jesd/tx_data axi_ad9144_tpl/link
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ad_connect util_daq2_xcvr/tx_out_clk_0 axi_ad9144_upack/clk
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@ -172,7 +181,7 @@ ad_connect axi_ad9144_offload/s_axis axi_ad9144_dma/m_axis
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# connections (adc)
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ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd
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ad_xcvrcon util_daq2_xcvr axi_ad9680_xcvr axi_ad9680_jesd {} {} {} $MAX_RX_NUM_OF_LANES
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ad_connect util_daq2_xcvr/rx_out_clk_0 axi_ad9680_tpl/link_clk
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ad_connect axi_ad9680_jesd/rx_sof axi_ad9680_tpl/link_sof
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ad_connect axi_ad9680_jesd/rx_data_tdata axi_ad9680_tpl/link_data
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@ -234,4 +243,3 @@ ad_cpu_interrupt ps-10 mb-15 axi_ad9144_jesd/irq
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ad_cpu_interrupt ps-11 mb-14 axi_ad9680_jesd/irq
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ad_cpu_interrupt ps-12 mb-13 axi_ad9144_dma/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9680_dma/irq
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@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project daq2_kc705
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# get_env_param retrieves parameter value from the environment if exists,
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# other case use the default value
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#
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# Use over-writable parameters from the environment.
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#
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# e.g.
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# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
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# Parameter description:
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_S : Number of samples per frame
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adi_project daq2_kc705 0 [list \
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RX_JESD_M [get_env_param RX_JESD_M 2 ] \
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RX_JESD_L [get_env_param RX_JESD_L 4 ] \
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RX_JESD_S [get_env_param RX_JESD_S 1 ] \
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TX_JESD_M [get_env_param TX_JESD_M 2 ] \
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TX_JESD_L [get_env_param TX_JESD_L 4 ] \
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TX_JESD_S [get_env_param TX_JESD_S 1 ] \
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]
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adi_project_files daq2_kc705 [list \
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"../common/daq2_spi.v" \
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"system_top.v" \
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@ -13,4 +34,6 @@ adi_project_files daq2_kc705 [list \
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adi_project_run daq2_kc705
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## To improve timing in the axi_ad9680_offload component
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set_property strategy Performance_Retiming [get_runs impl_1]
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@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project daq2_kcu105
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# get_env_param retrieves parameter value from the environment if exists,
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# other case use the default value
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#
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# Use over-writable parameters from the environment.
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#
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# e.g.
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# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
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# Parameter description:
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_S : Number of samples per frame
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adi_project daq2_kcu105 0 [list \
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RX_JESD_M [get_env_param RX_JESD_M 2 ] \
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RX_JESD_L [get_env_param RX_JESD_L 4 ] \
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RX_JESD_S [get_env_param RX_JESD_S 1 ] \
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TX_JESD_M [get_env_param TX_JESD_M 2 ] \
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TX_JESD_L [get_env_param TX_JESD_L 4 ] \
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TX_JESD_S [get_env_param TX_JESD_S 1 ] \
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]
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adi_project_files daq2_kcu105 [list \
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"../common/daq2_spi.v" \
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"system_top.v" \
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@ -16,4 +37,3 @@ set_property strategy Performance_Retiming [get_runs impl_1]
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adi_project_run daq2_kcu105
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@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project daq2_zc706
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# get_env_param retrieves parameter value from the environment if exists,
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# other case use the default value
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#
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# Use over-writable parameters from the environment.
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#
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# e.g.
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# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
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# Parameter description:
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_S : Number of samples per frame
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adi_project daq2_zc706 0 [list \
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RX_JESD_M [get_env_param RX_JESD_M 2 ] \
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RX_JESD_L [get_env_param RX_JESD_L 4 ] \
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RX_JESD_S [get_env_param RX_JESD_S 1 ] \
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TX_JESD_M [get_env_param TX_JESD_M 2 ] \
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TX_JESD_L [get_env_param TX_JESD_L 4 ] \
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TX_JESD_S [get_env_param TX_JESD_S 1 ] \
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]
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adi_project_files daq2_zc706 [list \
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"../common/daq2_spi.v" \
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"system_top.v" \
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@ -14,4 +35,7 @@ adi_project_files daq2_zc706 [list \
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adi_project_run daq2_zc706
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## To improve timing in the axi_ad9680_offload component
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set_property strategy Performance_Retiming [get_runs impl_1]
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@ -3,7 +3,28 @@ source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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adi_project daq2_zcu102
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# get_env_param retrieves parameter value from the environment if exists,
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# other case use the default value
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#
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# Use over-writable parameters from the environment.
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#
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# e.g.
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# make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
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# Parameter description:
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# [RX/TX]_JESD_M : Number of converters per link
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# [RX/TX]_JESD_L : Number of lanes per link
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# [RX/TX]_JESD_S : Number of samples per frame
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adi_project daq2_zcu102 0 [list \
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RX_JESD_M [get_env_param RX_JESD_M 2 ] \
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RX_JESD_L [get_env_param RX_JESD_L 4 ] \
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RX_JESD_S [get_env_param RX_JESD_S 1 ] \
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TX_JESD_M [get_env_param TX_JESD_M 2 ] \
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TX_JESD_L [get_env_param TX_JESD_L 4 ] \
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TX_JESD_S [get_env_param TX_JESD_S 1 ] \
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]
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adi_project_files daq2_zcu102 [list \
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"../common/daq2_spi.v" \
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"system_top.v" \
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@ -13,4 +34,5 @@ adi_project_files daq2_zcu102 [list \
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adi_project_run daq2_zcu102
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## To improve timing in the axi_ad9680_offload component
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set_property strategy Performance_Retiming [get_runs impl_1]
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