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library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl

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Istvan Csomortani 2018-08-14 11:08:06 +01:00 committed by István Csomortáni
parent 363494ab9c
commit 5329458a62
45 changed files with 44 additions and 44 deletions
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2
library/altera/adi_jesd204/adi_jesd204_glue_hw.tcl
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@ -44,7 +44,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create adi_jesd204_glue {Glue} jesd204_phy_glue_elab

2
library/axi_ad9122/axi_ad9122_hw.tcl
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@ -3,7 +3,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create axi_ad9122 {AXI AD9122 Interface}
set_module_property VALIDATION_CALLBACK info_param_validate

2
library/axi_ad9144/axi_ad9144_hw.tcl
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@ -3,7 +3,7 @@
package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad9144
set_module_property DESCRIPTION "AXI AD9144 Interface"

2
library/axi_ad9152/axi_ad9152_hw.tcl
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@ -4,7 +4,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad9152
set_module_property DESCRIPTION "AXI AD9152 Interface"

2
library/axi_ad9250/axi_ad9250_hw.tcl
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@ -4,7 +4,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad9250
set_module_property DESCRIPTION "AXI AD9250 Interface"

2
library/axi_ad9361/axi_ad9361_hw.tcl
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@ -3,7 +3,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create axi_ad9361 {AXI AD9361 Interface} axi_ad9361_elab
set_module_property VALIDATION_CALLBACK info_param_validate

2
library/axi_ad9371/axi_ad9371_hw.tcl
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@ -4,7 +4,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad9371
set_module_property DESCRIPTION "AXI AD9371 Interface"

2
library/axi_ad9671/axi_ad9671_hw.tcl
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@ -4,7 +4,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad9671
set_module_property DESCRIPTION "AXI AD9671 Interface"

2
library/axi_ad9680/axi_ad9680_hw.tcl
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@ -4,7 +4,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_ad9680
set_module_property DESCRIPTION "AXI AD9680 Interface"

2
library/axi_ad9684/axi_ad9684_hw.tcl
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@ -3,7 +3,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create axi_ad9684 {AXI AD9684 Interface} axi_ad9684_elab
set_module_property VALIDATION_CALLBACK info_param_validate

2
library/axi_adrv9009/axi_adrv9009_hw.tcl
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@ -4,7 +4,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_adrv9009
set_module_property DESCRIPTION "AXI adrv9009 Interface"

2
library/axi_dmac/axi_dmac_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_dmac
set_module_property DESCRIPTION "AXI DMA Controller"

2
library/axi_hdmi_tx/axi_hdmi_tx_hw.tcl
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@ -4,7 +4,7 @@ package require qsys
package require quartus::device
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME axi_hdmi_tx
set_module_property DESCRIPTION "AXI HDMI Transmit Interface"

2
library/intel/adi_jesd204/adi_jesd204_hw.tcl
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@ -44,7 +44,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
#
# Wrapper module that instantiates and connects all the components required to

2
library/intel/avl_adxcvr/avl_adxcvr_hw.tcl
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@ -1,7 +1,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create avl_adxcvr {Avalon ADXCVR Core}
set_module_property COMPOSITION_CALLBACK p_avl_adxcvr

2
library/intel/avl_adxcvr_octet_swap/avl_adxcvr_octet_swap_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create avl_adxcvr_octet_swap "avl_adxcvvr_octet_swap helper" avl_adxcvr_octet_swap_elaboration
set_module_property HIDE_FROM_SOPC true

2
library/intel/avl_adxphy/avl_adxphy_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
set_module_property NAME avl_adxphy
set_module_property DESCRIPTION "Avalon ADXPHY Core"

2
library/intel/avl_dacfifo/avl_dacfifo_hw.tcl
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@ -1,7 +1,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create avl_dacfifo {Avalon DDR DAC Fifo} p_avl_dacfifo_elab
ad_ip_files avl_dacfifo [list\

2
library/intel/axi_adxcvr/axi_adxcvr_hw.tcl
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@ -3,7 +3,7 @@ package require qsys
package require quartus::device
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
set_module_property NAME axi_adxcvr
set_module_property DESCRIPTION "AXI ADXCVR Core"

2
library/intel/common/alt_ifconv/alt_ifconv_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create alt_ifconv {Altera Interface Translator} alt_ifconv_elab
ad_ip_files alt_ifconv { \

2
library/intel/common/alt_mem_asym/alt_mem_asym_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create alt_mem_asym {Altera Asymmetric Memory}
set_module_property COMPOSITION_CALLBACK p_alt_mem_asym

2
library/intel/common/alt_mul/alt_mul_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create alt_mul {Altera LPM Multiplier}
set_module_property COMPOSITION_CALLBACK p_alt_mul

2
library/intel/common/alt_serdes/alt_serdes_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create alt_serdes {Altera SERDES}
set_module_property COMPOSITION_CALLBACK p_alt_serdes

2
library/intel/jesd204_phy/jesd204_phy_glue_hw.tcl
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@ -44,7 +44,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
#
# For whatever strange reason all the interface of the native PHY become

2
library/intel/jesd204_phy/jesd204_phy_hw.tcl
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@ -45,7 +45,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
#
# Instantiates the Arria 10 native PHY and configures it for JESD204 operation.

2
library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_hw.tcl
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@ -23,7 +23,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create ad_ip_jesd204_tpl_adc "JESD204 Transport Layer for ADCs" p_ad_ip_jesd204_tpl_adc_elab
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_adc_validate

2
library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_hw.tcl
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@ -23,7 +23,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create ad_ip_jesd204_tpl_dac "JESD204 Transport Layer for DACs" p_ad_ip_jesd204_tpl_dac_elab
set_module_property VALIDATION_CALLBACK p_ad_ip_jesd204_tpl_dac_validate

2
library/jesd204/axi_jesd204_rx/axi_jesd204_rx_hw.tcl
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@ -45,7 +45,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create axi_jesd204_rx "ADI JESD204 Receive AXI Interface"

2
library/jesd204/axi_jesd204_tx/axi_jesd204_tx_hw.tcl
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@ -45,7 +45,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create axi_jesd204_tx "ADI JESD204 Transmit AXI Interface"

2
library/jesd204/jesd204_rx/jesd204_rx_hw.tcl
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@ -45,7 +45,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_rx "ADI JESD204 Receive" jesd204_rx_elaboration_callback

2
library/jesd204/jesd204_soft_pcs_rx/jesd204_soft_pcs_rx_hw.tcl
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@ -45,7 +45,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_soft_pcs_rx "ADI JESD204 Transmit Soft PCS"

2
library/jesd204/jesd204_soft_pcs_tx/jesd204_soft_pcs_tx_hw.tcl
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@ -45,7 +45,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_soft_pcs_tx "ADI JESD204 Transmit Soft PCS"

2
library/jesd204/jesd204_tx/jesd204_tx_hw.tcl
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@ -45,7 +45,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
source $ad_hdl_dir/library/scripts/adi_ip_intel.tcl
ad_ip_create jesd204_tx "ADI JESD204 Transmit" jesd204_tx_elaboration_callback

0
library/scripts/adi_ip_alt.tcl → library/scripts/adi_ip_intel.tcl
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2
library/util_adcfifo/util_adcfifo_hw.tcl
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@ -1,7 +1,7 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create util_adcfifo {UTIL ADC FIFO Interface}
set_module_property ELABORATION_CALLBACK p_util_adcfifo

2
library/util_bsplit/util_bsplit_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME util_bsplit

2
library/util_clkdiv/util_clkdiv_hw.tcl
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@ -1,7 +1,7 @@
package require -exact qsys 13.0
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME util_clkdiv

2
library/util_dacfifo/util_dacfifo_hw.tcl
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@ -1,7 +1,7 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create util_dacfifo {UTIL DAC FIFO Interface}
ad_ip_files util_dacfifo [list\

2
library/util_pack/util_cpack2/Makefile
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@ -18,7 +18,7 @@ XILINX_DEPS += util_cpack2_ip.tcl
XILINX_DEPS += ../../interfaces/fifo_wr.xml
XILINX_DEPS += ../../interfaces/fifo_wr_rtl.xml
INTEL_DEPS += ../../scripts/adi_ip_alt.tcl
INTEL_DEPS += ../../scripts/adi_ip_intel.tcl
INTEL_DEPS += util_cpack2_hw.tcl
include ../../scripts/library.mk

2
library/util_pack/util_cpack2/util_cpack2_hw.tcl
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@ -23,7 +23,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create util_cpack2 {Channel Pack Utility v2} util_cpack_elab
ad_ip_files util_cpack2_impl [list \

2
library/util_pack/util_upack2/Makefile
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@ -15,7 +15,7 @@ GENERIC_DEPS += util_upack2_impl.v
XILINX_DEPS += util_upack2.v
XILINX_DEPS += util_upack2_ip.tcl
INTEL_DEPS += ../../scripts/adi_ip_alt.tcl
INTEL_DEPS += ../../scripts/adi_ip_intel.tcl
INTEL_DEPS += util_upack2_hw.tcl
include ../../scripts/library.mk

2
library/util_pack/util_upack2/util_upack2_hw.tcl
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@ -23,7 +23,7 @@
package require qsys
source ../../scripts/adi_env.tcl
source ../../scripts/adi_ip_alt.tcl
source ../../scripts/adi_ip_intel.tcl
ad_ip_create util_upack2 {Channel Unpack Utility v2} util_upack_elab
ad_ip_files util_upack2_impl [list \

2
library/util_rfifo/util_rfifo_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
ad_ip_create util_rfifo {Utils Read FIFO} util_rfifo_elab
ad_ip_files util_rfifo [list\

2
library/util_wfifo/util_wfifo_hw.tcl
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@ -2,7 +2,7 @@
package require qsys
source ../scripts/adi_env.tcl
source ../scripts/adi_ip_alt.tcl
source ../scripts/adi_ip_intel.tcl
set_module_property NAME util_wfifo
set_module_property DESCRIPTION "Utils Write FIFO"

2
projects/dac_fmc_ebz/a10soc/system_project.tcl
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@ -31,7 +31,7 @@
#
source ../../scripts/adi_env.tcl
source ../../scripts/adi_project_alt.tcl
source ../../scripts/adi_project_intel.tcl
source ../common/config.tcl